1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL \
2; RUN:    -check-prefix=M2 -check-prefix=GP32
3; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL \
4; RUN:    -check-prefix=32R1-R5 -check-prefix=GP32
5; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL \
6; RUN:    -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
7; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=ALL \
8; RUN:    -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
9; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=ALL \
10; RUN:    -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
11; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL \
12; RUN:    -check-prefix=32R6 -check-prefix=GP32
13; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL \
14; RUN:    -check-prefix=M4 -check-prefix=GP64-NOT-R6
15; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL \
16; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64-NOT-R6
17; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL \
18; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
19; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL \
20; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
21; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL \
22; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
23; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL \
24; RUN:    -check-prefix=64R6
25
26define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
27entry:
28; ALL-LABEL: mul_i1:
29
30  ; M2:         mult    $4, $5
31  ; M2:         mflo    $[[T0:[0-9]+]]
32  ; M2:         sll     $[[T0]], $[[T0]], 31
33  ; M2:         sra     $2, $[[T0]], 31
34
35  ; 32R1-R5:    mul     $[[T0:[0-9]+]], $4, $5
36  ; 32R1-R5:    sll     $[[T0]], $[[T0]], 31
37  ; 32R1-R5:    sra     $2, $[[T0]], 31
38
39  ; 32R6:       mul     $[[T0:[0-9]+]], $4, $5
40  ; 32R6:       sll     $[[T0]], $[[T0]], 31
41  ; 32R6:       sra     $2, $[[T0]], 31
42
43  ; M4:         mult    $4, $5
44  ; M4:         mflo    $[[T0:[0-9]+]]
45  ; M4:         sll     $[[T0]], $[[T0]], 31
46  ; M4:         sra     $2, $[[T0]], 31
47
48  ; 64R1-R5:    mul     $[[T0:[0-9]+]], $4, $5
49  ; 64R1-R5:    sll     $[[T0]], $[[T0]], 31
50  ; 64R1-R5:    sra     $2, $[[T0]], 31
51
52  ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
53  ; 64R6:       sll     $[[T0]], $[[T0]], 31
54  ; 64R6:       sra     $2, $[[T0]], 31
55
56  %r = mul i1 %a, %b
57  ret i1 %r
58}
59
60define signext i8 @mul_i8(i8 signext %a, i8 signext %b) {
61entry:
62; ALL-LABEL: mul_i8:
63
64  ; M2:         mult    $4, $5
65  ; M2:         mflo    $[[T0:[0-9]+]]
66  ; M2:         sll     $[[T0]], $[[T0]], 24
67  ; M2:         sra     $2, $[[T0]], 24
68
69  ; 32R1:       mul     $[[T0:[0-9]+]], $4, $5
70  ; 32R1:       sll     $[[T0]], $[[T0]], 24
71  ; 32R1:       sra     $2, $[[T0]], 24
72
73  ; 32R2-R5:    mul     $[[T0:[0-9]+]], $4, $5
74  ; 32R2-R5:    seb     $2, $[[T0]]
75
76  ; 32R6:       mul     $[[T0:[0-9]+]], $4, $5
77  ; 32R6:       seb     $2, $[[T0]]
78
79  ; M4:         mult    $4, $5
80  ; M4:         mflo    $[[T0:[0-9]+]]
81  ; M4:         sll     $[[T0]], $[[T0]], 24
82  ; M4:         sra     $2, $[[T0]], 24
83
84  ; 64R1:       mul     $[[T0:[0-9]+]], $4, $5
85  ; 64R1:       sll     $[[T0]], $[[T0]], 24
86  ; 64R1:       sra     $2, $[[T0]], 24
87
88  ; 64R2:       mul     $[[T0:[0-9]+]], $4, $5
89  ; 64R2:       seb     $2, $[[T0]]
90
91  ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
92  ; 64R6:       seb     $2, $[[T0]]
93  %r = mul i8 %a, %b
94  ret i8 %r
95}
96
97define signext i16 @mul_i16(i16 signext %a, i16 signext %b) {
98entry:
99; ALL-LABEL: mul_i16:
100
101  ; M2:         mult    $4, $5
102  ; M2:         mflo    $[[T0:[0-9]+]]
103  ; M2:         sll     $[[T0]], $[[T0]], 16
104  ; M2:         sra     $2, $[[T0]], 16
105
106  ; 32R1:       mul     $[[T0:[0-9]+]], $4, $5
107  ; 32R1:       sll     $[[T0]], $[[T0]], 16
108  ; 32R1:       sra     $2, $[[T0]], 16
109
110  ; 32R2-R5:    mul     $[[T0:[0-9]+]], $4, $5
111  ; 32R2-R5:    seh     $2, $[[T0]]
112
113  ; 32R6:       mul     $[[T0:[0-9]+]], $4, $5
114  ; 32R6:       seh     $2, $[[T0]]
115
116  ; M4:         mult    $4, $5
117  ; M4:         mflo    $[[T0:[0-9]+]]
118  ; M4:         sll     $[[T0]], $[[T0]], 16
119  ; M4:         sra     $2, $[[T0]], 16
120
121  ; 64R1:       mul     $[[T0:[0-9]+]], $4, $5
122  ; 64R1:       sll     $[[T0]], $[[T0]], 16
123  ; 64R1:       sra     $2, $[[T0]], 16
124
125  ; 64R2:       mul     $[[T0:[0-9]+]], $4, $5
126  ; 64R2:       seh     $2, $[[T0]]
127
128  ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
129  ; 64R6:       seh     $2, $[[T0]]
130  %r = mul i16 %a, %b
131  ret i16 %r
132}
133
134define signext i32 @mul_i32(i32 signext %a, i32 signext %b) {
135entry:
136; ALL-LABEL: mul_i32:
137
138  ; M2:         mult    $4, $5
139  ; M2:         mflo    $2
140
141  ; 32R1-R5:    mul     $2, $4, $5
142  ; 32R6:       mul     $2, $4, $5
143
144  ; 64R1-R5:    mul     $2, $4, $5
145  ; 64R6:       mul     $2, $4, $5
146  %r = mul i32 %a, %b
147  ret i32 %r
148}
149
150define signext i64 @mul_i64(i64 signext %a, i64 signext %b) {
151entry:
152; ALL-LABEL: mul_i64:
153
154  ; M2:         mult    $4, $7
155  ; M2:         mflo    $[[T0:[0-9]+]]
156  ; M2:         mult    $5, $6
157  ; M2:         mflo    $[[T1:[0-9]+]]
158  ; M2:         multu   $5, $7
159  ; M2:         mflo    $3
160  ; M2:         mfhi    $4
161  ; M2:         addu    $[[T2:[0-9]+]], $4, $[[T1]]
162  ; M2:         addu    $2, $[[T2]], $[[T0]]
163
164  ; 32R1-R5:    multu   $5, $7
165  ; 32R1-R5:    mflo    $3
166  ; 32R1-R5:    mfhi    $[[T0:[0-9]+]]
167  ; 32R1-R5:    mul     $[[T1:[0-9]+]], $4, $7
168  ; 32R1-R5:    mul     $[[T2:[0-9]+]], $5, $6
169  ; 32R1-R5:    addu    $[[T0]], $[[T0]], $[[T2:[0-9]+]]
170  ; 32R1-R5:    addu    $2, $[[T0]], $[[T1]]
171
172  ; 32R6:       mul     $[[T0:[0-9]+]], $5, $6
173  ; 32R6:       muhu    $[[T1:[0-9]+]], $5, $7
174  ; 32R6:       addu    $[[T0]], $[[T1]], $[[T0]]
175  ; 32R6:       mul     $[[T2:[0-9]+]], $4, $7
176  ; 32R6:       addu    $2, $[[T0]], $[[T2]]
177  ; 32R6:       mul     $3, $5, $7
178
179  ; M4:         dmult   $4, $5
180  ; M4:         mflo    $2
181
182  ; 64R1-R5:    dmult   $4, $5
183  ; 64R1-R5:    mflo    $2
184
185  ; 64R6:       dmul    $2, $4, $5
186
187  %r = mul i64 %a, %b
188  ret i64 %r
189}
190
191define signext i128 @mul_i128(i128 signext %a, i128 signext %b) {
192entry:
193; ALL-LABEL: mul_i128:
194
195  ; GP32:           lw      $25, %call16(__multi3)($gp)
196
197  ; GP64-NOT-R6:    dmult   $4, $7
198  ; GP64-NOT-R6:    mflo    $[[T0:[0-9]+]]
199  ; GP64-NOT-R6:    dmult   $5, $6
200  ; GP64-NOT-R6:    mflo    $[[T1:[0-9]+]]
201  ; GP64-NOT-R6:    dmultu  $5, $7
202  ; GP64-NOT-R6:    mflo    $3
203  ; GP64-NOT-R6:    mfhi    $[[T2:[0-9]+]]
204  ; GP64-NOT-R6:    daddu   $[[T3:[0-9]+]], $[[T2]], $[[T1]]
205  ; GP64-NOT-R6:    daddu   $2, $[[T3:[0-9]+]], $[[T0]]
206
207  ; 64R6:           dmul    $[[T0:[0-9]+]], $5, $6
208  ; 64R6:           dmuhu   $[[T1:[0-9]+]], $5, $7
209  ; 64R6:           daddu   $[[T2:[0-9]+]], $[[T1]], $[[T0]]
210  ; 64R6:           dmul    $[[T3:[0-9]+]], $4, $7
211  ; 64R6:           daddu   $2, $[[T2]], $[[T3]]
212  ; 64R6:           dmul    $3, $5, $7
213
214  %r = mul i128 %a, %b
215  ret i128 %r
216}
217