1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2; RUN:  -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
3; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4; RUN:  -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
5; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \
6; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
7; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 \
8; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
9; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 \
10; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
11; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
12; RUN:   -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6
13; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
14; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
15; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
16; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
17; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
18; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
19; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
20; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
21; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
22; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
23; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
24; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
25; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
26; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
27; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
28; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
29; RUN:  -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6
30
31define signext i1 @srem_i1(i1 signext %a, i1 signext %b) {
32entry:
33; ALL-LABEL: srem_i1:
34
35  ; NOT-R6:       div     $zero, $4, $5
36  ; NOT-R6:       teq     $5, $zero, 7
37  ; NOT-R6:       mfhi    $[[T0:[0-9]+]]
38  ; NOT-R6:       sll     $[[T1:[0-9]+]], $[[T0]], 31
39  ; NOT-R6:       sra     $2, $[[T1]], 31
40
41  ; R6:           mod     $[[T0:[0-9]+]], $4, $5
42  ; R6:           teq     $5, $zero, 7
43  ; R6:           sll     $[[T3:[0-9]+]], $[[T0]], 31
44  ; R6:           sra     $2, $[[T3]], 31
45
46  %r = srem i1 %a, %b
47  ret i1 %r
48}
49
50define signext i8 @srem_i8(i8 signext %a, i8 signext %b) {
51entry:
52; ALL-LABEL: srem_i8:
53
54  ; NOT-R2-R6:    div     $zero, $4, $5
55  ; NOT-R2-R6:    teq     $5, $zero, 7
56  ; NOT-R2-R6:    mfhi    $[[T0:[0-9]+]]
57  ; NOT-R2-R6:    sll     $[[T1:[0-9]+]], $[[T0]], 24
58  ; NOT-R2-R6:    sra     $2, $[[T1]], 24
59
60  ; R2-R5:        div     $zero, $4, $5
61  ; R2-R5:        teq     $5, $zero, 7
62  ; R2-R5:        mfhi    $[[T0:[0-9]+]]
63  ; R2-R5:        seb     $2, $[[T0]]
64
65  ; R6:           mod     $[[T0:[0-9]+]], $4, $5
66  ; R6:           teq     $5, $zero, 7
67  ; R6:           seb     $2, $[[T0]]
68
69  %r = srem i8 %a, %b
70  ret i8 %r
71}
72
73define signext i16 @srem_i16(i16 signext %a, i16 signext %b) {
74entry:
75; ALL-LABEL: srem_i16:
76
77  ; NOT-R2-R6:    div     $zero, $4, $5
78  ; NOT-R2-R6:    teq     $5, $zero, 7
79  ; NOT-R2-R6:    mfhi    $[[T0:[0-9]+]]
80  ; NOT-R2-R6:    sll     $[[T1:[0-9]+]], $[[T0]], 16
81  ; NOT-R2-R6:    sra     $2, $[[T1]], 16
82
83  ; R2-R5:        div     $zero, $4, $5
84  ; R2-R5:        teq     $5, $zero, 7
85  ; R2-R5:        mfhi    $[[T0:[0-9]+]]
86  ; R2-R5:        seh     $2, $[[T1]]
87
88  ; R6:           mod     $[[T0:[0-9]+]], $4, $5
89  ; R6:           teq     $5, $zero, 7
90  ; R6:           seh     $2, $[[T0]]
91
92  %r = srem i16 %a, %b
93  ret i16 %r
94}
95
96define signext i32 @srem_i32(i32 signext %a, i32 signext %b) {
97entry:
98; ALL-LABEL: srem_i32:
99
100  ; NOT-R6:       div     $zero, $4, $5
101  ; NOT-R6:       teq     $5, $zero, 7
102  ; NOT-R6:       mfhi    $2
103
104  ; R6:           mod     $2, $4, $5
105  ; R6:           teq     $5, $zero, 7
106
107  %r = srem i32 %a, %b
108  ret i32 %r
109}
110
111define signext i64 @srem_i64(i64 signext %a, i64 signext %b) {
112entry:
113; ALL-LABEL: srem_i64:
114
115  ; GP32:         lw      $25, %call16(__moddi3)($gp)
116
117  ; GP64-NOT-R6:  ddiv    $zero, $4, $5
118  ; GP64-NOT-R6:  teq     $5, $zero, 7
119  ; GP64-NOT-R6:  mfhi    $2
120
121  ; 64R6:         dmod    $2, $4, $5
122  ; 64R6:         teq     $5, $zero, 7
123
124  %r = srem i64 %a, %b
125  ret i64 %r
126}
127
128define signext i128 @srem_i128(i128 signext %a, i128 signext %b) {
129entry:
130; ALL-LABEL: srem_i128:
131
132  ; GP32:         lw      $25, %call16(__modti3)($gp)
133
134  ; GP64-NOT-R6:  ld      $25, %call16(__modti3)($gp)
135  ; 64-R6:        ld      $25, %call16(__modti3)($gp)
136
137  %r = srem i128 %a, %b
138  ret i128 %r
139}
140