1; Test the MSA intrinsics that are encoded with the 3R instruction format.
2; There are lots of these so this covers those beginning with 'p'
3
4; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
6
7@llvm_mips_pckev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
8@llvm_mips_pckev_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
9@llvm_mips_pckev_b_RES  = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
10
11define void @llvm_mips_pckev_b_test() nounwind {
12entry:
13  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_pckev_b_ARG1
14  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_pckev_b_ARG2
15  %2 = tail call <16 x i8> @llvm.mips.pckev.b(<16 x i8> %0, <16 x i8> %1)
16  store <16 x i8> %2, <16 x i8>* @llvm_mips_pckev_b_RES
17  ret void
18}
19
20declare <16 x i8> @llvm.mips.pckev.b(<16 x i8>, <16 x i8>) nounwind
21
22; CHECK: llvm_mips_pckev_b_test:
23; CHECK: ld.b
24; CHECK: ld.b
25; CHECK: pckev.b
26; CHECK: st.b
27; CHECK: .size llvm_mips_pckev_b_test
28;
29@llvm_mips_pckev_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
30@llvm_mips_pckev_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
31@llvm_mips_pckev_h_RES  = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
32
33define void @llvm_mips_pckev_h_test() nounwind {
34entry:
35  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_pckev_h_ARG1
36  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_pckev_h_ARG2
37  %2 = tail call <8 x i16> @llvm.mips.pckev.h(<8 x i16> %0, <8 x i16> %1)
38  store <8 x i16> %2, <8 x i16>* @llvm_mips_pckev_h_RES
39  ret void
40}
41
42declare <8 x i16> @llvm.mips.pckev.h(<8 x i16>, <8 x i16>) nounwind
43
44; CHECK: llvm_mips_pckev_h_test:
45; CHECK: ld.h
46; CHECK: ld.h
47; CHECK: pckev.h
48; CHECK: st.h
49; CHECK: .size llvm_mips_pckev_h_test
50;
51@llvm_mips_pckev_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
52@llvm_mips_pckev_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
53@llvm_mips_pckev_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
54
55define void @llvm_mips_pckev_w_test() nounwind {
56entry:
57  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_pckev_w_ARG1
58  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_pckev_w_ARG2
59  %2 = tail call <4 x i32> @llvm.mips.pckev.w(<4 x i32> %0, <4 x i32> %1)
60  store <4 x i32> %2, <4 x i32>* @llvm_mips_pckev_w_RES
61  ret void
62}
63
64declare <4 x i32> @llvm.mips.pckev.w(<4 x i32>, <4 x i32>) nounwind
65
66; CHECK: llvm_mips_pckev_w_test:
67; CHECK: ld.w
68; CHECK: ld.w
69; CHECK: pckev.w
70; CHECK: st.w
71; CHECK: .size llvm_mips_pckev_w_test
72;
73@llvm_mips_pckev_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
74@llvm_mips_pckev_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
75@llvm_mips_pckev_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
76
77define void @llvm_mips_pckev_d_test() nounwind {
78entry:
79  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_pckev_d_ARG1
80  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_pckev_d_ARG2
81  %2 = tail call <2 x i64> @llvm.mips.pckev.d(<2 x i64> %0, <2 x i64> %1)
82  store <2 x i64> %2, <2 x i64>* @llvm_mips_pckev_d_RES
83  ret void
84}
85
86declare <2 x i64> @llvm.mips.pckev.d(<2 x i64>, <2 x i64>) nounwind
87
88; CHECK: llvm_mips_pckev_d_test:
89; CHECK: ld.d
90; CHECK: ld.d
91; CHECK: pckev.d
92; CHECK: st.d
93; CHECK: .size llvm_mips_pckev_d_test
94;
95@llvm_mips_pckod_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
96@llvm_mips_pckod_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
97@llvm_mips_pckod_b_RES  = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
98
99define void @llvm_mips_pckod_b_test() nounwind {
100entry:
101  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_pckod_b_ARG1
102  %1 = load <16 x i8>, <16 x i8>* @llvm_mips_pckod_b_ARG2
103  %2 = tail call <16 x i8> @llvm.mips.pckod.b(<16 x i8> %0, <16 x i8> %1)
104  store <16 x i8> %2, <16 x i8>* @llvm_mips_pckod_b_RES
105  ret void
106}
107
108declare <16 x i8> @llvm.mips.pckod.b(<16 x i8>, <16 x i8>) nounwind
109
110; CHECK: llvm_mips_pckod_b_test:
111; CHECK: ld.b
112; CHECK: ld.b
113; CHECK: pckod.b
114; CHECK: st.b
115; CHECK: .size llvm_mips_pckod_b_test
116;
117@llvm_mips_pckod_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
118@llvm_mips_pckod_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
119@llvm_mips_pckod_h_RES  = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
120
121define void @llvm_mips_pckod_h_test() nounwind {
122entry:
123  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_pckod_h_ARG1
124  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_pckod_h_ARG2
125  %2 = tail call <8 x i16> @llvm.mips.pckod.h(<8 x i16> %0, <8 x i16> %1)
126  store <8 x i16> %2, <8 x i16>* @llvm_mips_pckod_h_RES
127  ret void
128}
129
130declare <8 x i16> @llvm.mips.pckod.h(<8 x i16>, <8 x i16>) nounwind
131
132; CHECK: llvm_mips_pckod_h_test:
133; CHECK: ld.h
134; CHECK: ld.h
135; CHECK: pckod.h
136; CHECK: st.h
137; CHECK: .size llvm_mips_pckod_h_test
138;
139@llvm_mips_pckod_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
140@llvm_mips_pckod_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
141@llvm_mips_pckod_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
142
143define void @llvm_mips_pckod_w_test() nounwind {
144entry:
145  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_pckod_w_ARG1
146  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_pckod_w_ARG2
147  %2 = tail call <4 x i32> @llvm.mips.pckod.w(<4 x i32> %0, <4 x i32> %1)
148  store <4 x i32> %2, <4 x i32>* @llvm_mips_pckod_w_RES
149  ret void
150}
151
152declare <4 x i32> @llvm.mips.pckod.w(<4 x i32>, <4 x i32>) nounwind
153
154; CHECK: llvm_mips_pckod_w_test:
155; CHECK: ld.w
156; CHECK: ld.w
157; CHECK: pckod.w
158; CHECK: st.w
159; CHECK: .size llvm_mips_pckod_w_test
160;
161@llvm_mips_pckod_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
162@llvm_mips_pckod_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
163@llvm_mips_pckod_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
164
165define void @llvm_mips_pckod_d_test() nounwind {
166entry:
167  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_pckod_d_ARG1
168  %1 = load <2 x i64>, <2 x i64>* @llvm_mips_pckod_d_ARG2
169  %2 = tail call <2 x i64> @llvm.mips.pckod.d(<2 x i64> %0, <2 x i64> %1)
170  store <2 x i64> %2, <2 x i64>* @llvm_mips_pckod_d_RES
171  ret void
172}
173
174declare <2 x i64> @llvm.mips.pckod.d(<2 x i64>, <2 x i64>) nounwind
175
176; CHECK: llvm_mips_pckod_d_test:
177; CHECK: ld.d
178; CHECK: ld.d
179; CHECK: pckod.d
180; CHECK: st.d
181; CHECK: .size llvm_mips_pckod_d_test
182;
183