1; Test the MSA fixed-point intrinsics that are encoded with the 3RF instruction
2; format.
3
4; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
6
7@llvm_mips_mul_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
8@llvm_mips_mul_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
9@llvm_mips_mul_q_h_RES  = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
10
11define void @llvm_mips_mul_q_h_test() nounwind {
12entry:
13  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_mul_q_h_ARG1
14  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_mul_q_h_ARG2
15  %2 = tail call <8 x i16> @llvm.mips.mul.q.h(<8 x i16> %0, <8 x i16> %1)
16  store <8 x i16> %2, <8 x i16>* @llvm_mips_mul_q_h_RES
17  ret void
18}
19
20declare <8 x i16> @llvm.mips.mul.q.h(<8 x i16>, <8 x i16>) nounwind
21
22; CHECK: llvm_mips_mul_q_h_test:
23; CHECK: ld.h
24; CHECK: ld.h
25; CHECK: mul_q.h
26; CHECK: st.h
27; CHECK: .size llvm_mips_mul_q_h_test
28;
29@llvm_mips_mul_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
30@llvm_mips_mul_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
31@llvm_mips_mul_q_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
32
33define void @llvm_mips_mul_q_w_test() nounwind {
34entry:
35  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_mul_q_w_ARG1
36  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_mul_q_w_ARG2
37  %2 = tail call <4 x i32> @llvm.mips.mul.q.w(<4 x i32> %0, <4 x i32> %1)
38  store <4 x i32> %2, <4 x i32>* @llvm_mips_mul_q_w_RES
39  ret void
40}
41
42declare <4 x i32> @llvm.mips.mul.q.w(<4 x i32>, <4 x i32>) nounwind
43
44; CHECK: llvm_mips_mul_q_w_test:
45; CHECK: ld.w
46; CHECK: ld.w
47; CHECK: mul_q.w
48; CHECK: st.w
49; CHECK: .size llvm_mips_mul_q_w_test
50;
51@llvm_mips_mulr_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
52@llvm_mips_mulr_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
53@llvm_mips_mulr_q_h_RES  = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
54
55define void @llvm_mips_mulr_q_h_test() nounwind {
56entry:
57  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_mulr_q_h_ARG1
58  %1 = load <8 x i16>, <8 x i16>* @llvm_mips_mulr_q_h_ARG2
59  %2 = tail call <8 x i16> @llvm.mips.mulr.q.h(<8 x i16> %0, <8 x i16> %1)
60  store <8 x i16> %2, <8 x i16>* @llvm_mips_mulr_q_h_RES
61  ret void
62}
63
64declare <8 x i16> @llvm.mips.mulr.q.h(<8 x i16>, <8 x i16>) nounwind
65
66; CHECK: llvm_mips_mulr_q_h_test:
67; CHECK: ld.h
68; CHECK: ld.h
69; CHECK: mulr_q.h
70; CHECK: st.h
71; CHECK: .size llvm_mips_mulr_q_h_test
72;
73@llvm_mips_mulr_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
74@llvm_mips_mulr_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
75@llvm_mips_mulr_q_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
76
77define void @llvm_mips_mulr_q_w_test() nounwind {
78entry:
79  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_mulr_q_w_ARG1
80  %1 = load <4 x i32>, <4 x i32>* @llvm_mips_mulr_q_w_ARG2
81  %2 = tail call <4 x i32> @llvm.mips.mulr.q.w(<4 x i32> %0, <4 x i32> %1)
82  store <4 x i32> %2, <4 x i32>* @llvm_mips_mulr_q_w_RES
83  ret void
84}
85
86declare <4 x i32> @llvm.mips.mulr.q.w(<4 x i32>, <4 x i32>) nounwind
87
88; CHECK: llvm_mips_mulr_q_w_test:
89; CHECK: ld.w
90; CHECK: ld.w
91; CHECK: mulr_q.w
92; CHECK: st.w
93; CHECK: .size llvm_mips_mulr_q_w_test
94;
95