1; Test the MSA intrinsics that are encoded with the I5 instruction format and
2; are loads or stores.
3
4; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
6
7@llvm_mips_ld_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
8@llvm_mips_ld_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
9
10define void @llvm_mips_ld_b_test() nounwind {
11entry:
12  %0 = bitcast <16 x i8>* @llvm_mips_ld_b_ARG to i8*
13  %1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 16)
14  store <16 x i8> %1, <16 x i8>* @llvm_mips_ld_b_RES
15  ret void
16}
17
18declare <16 x i8> @llvm.mips.ld.b(i8*, i32) nounwind
19
20; CHECK: llvm_mips_ld_b_test:
21; CHECK: ld.b [[R1:\$w[0-9]+]], 16(
22; CHECK: st.b
23; CHECK: .size llvm_mips_ld_b_test
24;
25@llvm_mips_ld_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
26@llvm_mips_ld_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
27
28define void @llvm_mips_ld_h_test() nounwind {
29entry:
30  %0 = bitcast <8 x i16>* @llvm_mips_ld_h_ARG to i8*
31  %1 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 16)
32  store <8 x i16> %1, <8 x i16>* @llvm_mips_ld_h_RES
33  ret void
34}
35
36declare <8 x i16> @llvm.mips.ld.h(i8*, i32) nounwind
37
38; CHECK: llvm_mips_ld_h_test:
39; CHECK: ld.h [[R1:\$w[0-9]+]], 16(
40; CHECK: st.h
41; CHECK: .size llvm_mips_ld_h_test
42;
43@llvm_mips_ld_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
44@llvm_mips_ld_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
45
46define void @llvm_mips_ld_w_test() nounwind {
47entry:
48  %0 = bitcast <4 x i32>* @llvm_mips_ld_w_ARG to i8*
49  %1 = tail call <4 x i32> @llvm.mips.ld.w(i8* %0, i32 16)
50  store <4 x i32> %1, <4 x i32>* @llvm_mips_ld_w_RES
51  ret void
52}
53
54declare <4 x i32> @llvm.mips.ld.w(i8*, i32) nounwind
55
56; CHECK: llvm_mips_ld_w_test:
57; CHECK: ld.w [[R1:\$w[0-9]+]], 16(
58; CHECK: st.w
59; CHECK: .size llvm_mips_ld_w_test
60;
61@llvm_mips_ld_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16
62@llvm_mips_ld_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
63
64define void @llvm_mips_ld_d_test() nounwind {
65entry:
66  %0 = bitcast <2 x i64>* @llvm_mips_ld_d_ARG to i8*
67  %1 = tail call <2 x i64> @llvm.mips.ld.d(i8* %0, i32 16)
68  store <2 x i64> %1, <2 x i64>* @llvm_mips_ld_d_RES
69  ret void
70}
71
72declare <2 x i64> @llvm.mips.ld.d(i8*, i32) nounwind
73
74; CHECK: llvm_mips_ld_d_test:
75; CHECK: ld.d [[R1:\$w[0-9]+]], 16(
76; CHECK: st.d
77; CHECK: .size llvm_mips_ld_d_test
78;
79@llvm_mips_st_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
80@llvm_mips_st_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
81
82define void @llvm_mips_st_b_test() nounwind {
83entry:
84  %0 = load <16 x i8>, <16 x i8>* @llvm_mips_st_b_ARG
85  %1 = bitcast <16 x i8>* @llvm_mips_st_b_RES to i8*
86  tail call void @llvm.mips.st.b(<16 x i8> %0, i8* %1, i32 16)
87  ret void
88}
89
90declare void @llvm.mips.st.b(<16 x i8>, i8*, i32) nounwind
91
92; CHECK: llvm_mips_st_b_test:
93; CHECK: ld.b
94; CHECK: st.b [[R1:\$w[0-9]+]], 16(
95; CHECK: .size llvm_mips_st_b_test
96;
97@llvm_mips_st_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
98@llvm_mips_st_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
99
100define void @llvm_mips_st_h_test() nounwind {
101entry:
102  %0 = load <8 x i16>, <8 x i16>* @llvm_mips_st_h_ARG
103  %1 = bitcast <8 x i16>* @llvm_mips_st_h_RES to i8*
104  tail call void @llvm.mips.st.h(<8 x i16> %0, i8* %1, i32 16)
105  ret void
106}
107
108declare void @llvm.mips.st.h(<8 x i16>, i8*, i32) nounwind
109
110; CHECK: llvm_mips_st_h_test:
111; CHECK: ld.h
112; CHECK: st.h [[R1:\$w[0-9]+]], 16(
113; CHECK: .size llvm_mips_st_h_test
114;
115@llvm_mips_st_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
116@llvm_mips_st_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
117
118define void @llvm_mips_st_w_test() nounwind {
119entry:
120  %0 = load <4 x i32>, <4 x i32>* @llvm_mips_st_w_ARG
121  %1 = bitcast <4 x i32>* @llvm_mips_st_w_RES to i8*
122  tail call void @llvm.mips.st.w(<4 x i32> %0, i8* %1, i32 16)
123  ret void
124}
125
126declare void @llvm.mips.st.w(<4 x i32>, i8*, i32) nounwind
127
128; CHECK: llvm_mips_st_w_test:
129; CHECK: ld.w
130; CHECK: st.w [[R1:\$w[0-9]+]], 16(
131; CHECK: .size llvm_mips_st_w_test
132;
133@llvm_mips_st_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16
134@llvm_mips_st_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
135
136define void @llvm_mips_st_d_test() nounwind {
137entry:
138  %0 = load <2 x i64>, <2 x i64>* @llvm_mips_st_d_ARG
139  %1 = bitcast <2 x i64>* @llvm_mips_st_d_RES to i8*
140  tail call void @llvm.mips.st.d(<2 x i64> %0, i8* %1, i32 16)
141  ret void
142}
143
144declare void @llvm.mips.st.d(<2 x i64>, i8*, i32) nounwind
145
146; CHECK: llvm_mips_st_d_test:
147; CHECK: ld.d
148; CHECK: st.d [[R1:\$w[0-9]+]], 16(
149; CHECK: .size llvm_mips_st_d_test
150;
151