1; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s 2; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s 3 4;; These tests should run for all targets 5 6;;===-- Basic instruction selection tests ---------------------------------===;; 7 8 9;;; i64 10 11define i64 @icmp_eq_i64(i64 %a, i64 %b) { 12; CHECK: setp.eq.s64 %p[[P0:[0-9]+]], %rd{{[0-9]+}}, %rd{{[0-9]+}} 13; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 14; CHECK: ret 15 %cmp = icmp eq i64 %a, %b 16 %ret = zext i1 %cmp to i64 17 ret i64 %ret 18} 19 20define i64 @icmp_ne_i64(i64 %a, i64 %b) { 21; CHECK: setp.ne.s64 %p[[P0:[0-9]+]], %rd{{[0-9]+}}, %rd{{[0-9]+}} 22; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 23; CHECK: ret 24 %cmp = icmp ne i64 %a, %b 25 %ret = zext i1 %cmp to i64 26 ret i64 %ret 27} 28 29define i64 @icmp_ugt_i64(i64 %a, i64 %b) { 30; CHECK: setp.gt.u64 %p[[P0:[0-9]+]], %rd{{[0-9]+}}, %rd{{[0-9]+}} 31; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 32; CHECK: ret 33 %cmp = icmp ugt i64 %a, %b 34 %ret = zext i1 %cmp to i64 35 ret i64 %ret 36} 37 38define i64 @icmp_uge_i64(i64 %a, i64 %b) { 39; CHECK: setp.ge.u64 %p[[P0:[0-9]+]], %rd{{[0-9]+}}, %rd{{[0-9]+}} 40; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 41; CHECK: ret 42 %cmp = icmp uge i64 %a, %b 43 %ret = zext i1 %cmp to i64 44 ret i64 %ret 45} 46 47define i64 @icmp_ult_i64(i64 %a, i64 %b) { 48; CHECK: setp.lt.u64 %p[[P0:[0-9]+]], %rd{{[0-9]+}}, %rd{{[0-9]+}} 49; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 50; CHECK: ret 51 %cmp = icmp ult i64 %a, %b 52 %ret = zext i1 %cmp to i64 53 ret i64 %ret 54} 55 56define i64 @icmp_ule_i64(i64 %a, i64 %b) { 57; CHECK: setp.le.u64 %p[[P0:[0-9]+]], %rd{{[0-9]+}}, %rd{{[0-9]+}} 58; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 59; CHECK: ret 60 %cmp = icmp ule i64 %a, %b 61 %ret = zext i1 %cmp to i64 62 ret i64 %ret 63} 64 65define i64 @icmp_sgt_i64(i64 %a, i64 %b) { 66; CHECK: setp.gt.s64 %p[[P0:[0-9]+]], %rd{{[0-9]+}}, %rd{{[0-9]+}} 67; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 68; CHECK: ret 69 %cmp = icmp sgt i64 %a, %b 70 %ret = zext i1 %cmp to i64 71 ret i64 %ret 72} 73 74define i64 @icmp_sge_i64(i64 %a, i64 %b) { 75; CHECK: setp.ge.s64 %p[[P0:[0-9]+]], %rd{{[0-9]+}}, %rd{{[0-9]+}} 76; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 77; CHECK: ret 78 %cmp = icmp sge i64 %a, %b 79 %ret = zext i1 %cmp to i64 80 ret i64 %ret 81} 82 83define i64 @icmp_slt_i64(i64 %a, i64 %b) { 84; CHECK: setp.lt.s64 %p[[P0:[0-9]+]], %rd{{[0-9]+}}, %rd{{[0-9]+}} 85; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 86; CHECK: ret 87 %cmp = icmp slt i64 %a, %b 88 %ret = zext i1 %cmp to i64 89 ret i64 %ret 90} 91 92define i64 @icmp_sle_i64(i64 %a, i64 %b) { 93; CHECK: setp.le.s64 %p[[P0:[0-9]+]], %rd{{[0-9]+}}, %rd{{[0-9]+}} 94; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]] 95; CHECK: ret 96 %cmp = icmp sle i64 %a, %b 97 %ret = zext i1 %cmp to i64 98 ret i64 %ret 99} 100 101;;; i32 102 103define i32 @icmp_eq_i32(i32 %a, i32 %b) { 104; CHECK: setp.eq.s32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 105; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 106; CHECK: ret 107 %cmp = icmp eq i32 %a, %b 108 %ret = zext i1 %cmp to i32 109 ret i32 %ret 110} 111 112define i32 @icmp_ne_i32(i32 %a, i32 %b) { 113; CHECK: setp.ne.s32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 114; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 115; CHECK: ret 116 %cmp = icmp ne i32 %a, %b 117 %ret = zext i1 %cmp to i32 118 ret i32 %ret 119} 120 121define i32 @icmp_ugt_i32(i32 %a, i32 %b) { 122; CHECK: setp.gt.u32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 123; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 124; CHECK: ret 125 %cmp = icmp ugt i32 %a, %b 126 %ret = zext i1 %cmp to i32 127 ret i32 %ret 128} 129 130define i32 @icmp_uge_i32(i32 %a, i32 %b) { 131; CHECK: setp.ge.u32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 132; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 133; CHECK: ret 134 %cmp = icmp uge i32 %a, %b 135 %ret = zext i1 %cmp to i32 136 ret i32 %ret 137} 138 139define i32 @icmp_ult_i32(i32 %a, i32 %b) { 140; CHECK: setp.lt.u32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 141; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 142; CHECK: ret 143 %cmp = icmp ult i32 %a, %b 144 %ret = zext i1 %cmp to i32 145 ret i32 %ret 146} 147 148define i32 @icmp_ule_i32(i32 %a, i32 %b) { 149; CHECK: setp.le.u32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 150; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 151; CHECK: ret 152 %cmp = icmp ule i32 %a, %b 153 %ret = zext i1 %cmp to i32 154 ret i32 %ret 155} 156 157define i32 @icmp_sgt_i32(i32 %a, i32 %b) { 158; CHECK: setp.gt.s32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 159; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 160; CHECK: ret 161 %cmp = icmp sgt i32 %a, %b 162 %ret = zext i1 %cmp to i32 163 ret i32 %ret 164} 165 166define i32 @icmp_sge_i32(i32 %a, i32 %b) { 167; CHECK: setp.ge.s32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 168; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 169; CHECK: ret 170 %cmp = icmp sge i32 %a, %b 171 %ret = zext i1 %cmp to i32 172 ret i32 %ret 173} 174 175define i32 @icmp_slt_i32(i32 %a, i32 %b) { 176; CHECK: setp.lt.s32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 177; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 178; CHECK: ret 179 %cmp = icmp slt i32 %a, %b 180 %ret = zext i1 %cmp to i32 181 ret i32 %ret 182} 183 184define i32 @icmp_sle_i32(i32 %a, i32 %b) { 185; CHECK: setp.le.s32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}} 186; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 187; CHECK: ret 188 %cmp = icmp sle i32 %a, %b 189 %ret = zext i1 %cmp to i32 190 ret i32 %ret 191} 192 193 194;;; i16 195 196define i16 @icmp_eq_i16(i16 %a, i16 %b) { 197; CHECK: setp.eq.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 198; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 199; CHECK: ret 200 %cmp = icmp eq i16 %a, %b 201 %ret = zext i1 %cmp to i16 202 ret i16 %ret 203} 204 205define i16 @icmp_ne_i16(i16 %a, i16 %b) { 206; CHECK: setp.ne.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 207; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 208; CHECK: ret 209 %cmp = icmp ne i16 %a, %b 210 %ret = zext i1 %cmp to i16 211 ret i16 %ret 212} 213 214define i16 @icmp_ugt_i16(i16 %a, i16 %b) { 215; CHECK: setp.gt.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 216; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 217; CHECK: ret 218 %cmp = icmp ugt i16 %a, %b 219 %ret = zext i1 %cmp to i16 220 ret i16 %ret 221} 222 223define i16 @icmp_uge_i16(i16 %a, i16 %b) { 224; CHECK: setp.ge.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 225; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 226; CHECK: ret 227 %cmp = icmp uge i16 %a, %b 228 %ret = zext i1 %cmp to i16 229 ret i16 %ret 230} 231 232define i16 @icmp_ult_i16(i16 %a, i16 %b) { 233; CHECK: setp.lt.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 234; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 235; CHECK: ret 236 %cmp = icmp ult i16 %a, %b 237 %ret = zext i1 %cmp to i16 238 ret i16 %ret 239} 240 241define i16 @icmp_ule_i16(i16 %a, i16 %b) { 242; CHECK: setp.le.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 243; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 244; CHECK: ret 245 %cmp = icmp ule i16 %a, %b 246 %ret = zext i1 %cmp to i16 247 ret i16 %ret 248} 249 250define i16 @icmp_sgt_i16(i16 %a, i16 %b) { 251; CHECK: setp.gt.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 252; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 253; CHECK: ret 254 %cmp = icmp sgt i16 %a, %b 255 %ret = zext i1 %cmp to i16 256 ret i16 %ret 257} 258 259define i16 @icmp_sge_i16(i16 %a, i16 %b) { 260; CHECK: setp.ge.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 261; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 262; CHECK: ret 263 %cmp = icmp sge i16 %a, %b 264 %ret = zext i1 %cmp to i16 265 ret i16 %ret 266} 267 268define i16 @icmp_slt_i16(i16 %a, i16 %b) { 269; CHECK: setp.lt.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 270; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 271; CHECK: ret 272 %cmp = icmp slt i16 %a, %b 273 %ret = zext i1 %cmp to i16 274 ret i16 %ret 275} 276 277define i16 @icmp_sle_i16(i16 %a, i16 %b) { 278; CHECK: setp.le.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 279; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 280; CHECK: ret 281 %cmp = icmp sle i16 %a, %b 282 %ret = zext i1 %cmp to i16 283 ret i16 %ret 284} 285 286 287;;; i8 288 289define i8 @icmp_eq_i8(i8 %a, i8 %b) { 290; Comparison happens in 16-bit 291; CHECK: setp.eq.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 292; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 293; CHECK: ret 294 %cmp = icmp eq i8 %a, %b 295 %ret = zext i1 %cmp to i8 296 ret i8 %ret 297} 298 299define i8 @icmp_ne_i8(i8 %a, i8 %b) { 300; Comparison happens in 16-bit 301; CHECK: setp.ne.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 302; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 303; CHECK: ret 304 %cmp = icmp ne i8 %a, %b 305 %ret = zext i1 %cmp to i8 306 ret i8 %ret 307} 308 309define i8 @icmp_ugt_i8(i8 %a, i8 %b) { 310; Comparison happens in 16-bit 311; CHECK: setp.gt.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 312; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 313; CHECK: ret 314 %cmp = icmp ugt i8 %a, %b 315 %ret = zext i1 %cmp to i8 316 ret i8 %ret 317} 318 319define i8 @icmp_uge_i8(i8 %a, i8 %b) { 320; Comparison happens in 16-bit 321; CHECK: setp.ge.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 322; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 323; CHECK: ret 324 %cmp = icmp uge i8 %a, %b 325 %ret = zext i1 %cmp to i8 326 ret i8 %ret 327} 328 329define i8 @icmp_ult_i8(i8 %a, i8 %b) { 330; Comparison happens in 16-bit 331; CHECK: setp.lt.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 332; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 333; CHECK: ret 334 %cmp = icmp ult i8 %a, %b 335 %ret = zext i1 %cmp to i8 336 ret i8 %ret 337} 338 339define i8 @icmp_ule_i8(i8 %a, i8 %b) { 340; Comparison happens in 16-bit 341; CHECK: setp.le.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 342; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 343; CHECK: ret 344 %cmp = icmp ule i8 %a, %b 345 %ret = zext i1 %cmp to i8 346 ret i8 %ret 347} 348 349define i8 @icmp_sgt_i8(i8 %a, i8 %b) { 350; Comparison happens in 16-bit 351; CHECK: setp.gt.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 352; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 353; CHECK: ret 354 %cmp = icmp sgt i8 %a, %b 355 %ret = zext i1 %cmp to i8 356 ret i8 %ret 357} 358 359define i8 @icmp_sge_i8(i8 %a, i8 %b) { 360; Comparison happens in 16-bit 361; CHECK: setp.ge.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 362; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 363; CHECK: ret 364 %cmp = icmp sge i8 %a, %b 365 %ret = zext i1 %cmp to i8 366 ret i8 %ret 367} 368 369define i8 @icmp_slt_i8(i8 %a, i8 %b) { 370; Comparison happens in 16-bit 371; CHECK: setp.lt.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 372; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 373; CHECK: ret 374 %cmp = icmp slt i8 %a, %b 375 %ret = zext i1 %cmp to i8 376 ret i8 %ret 377} 378 379define i8 @icmp_sle_i8(i8 %a, i8 %b) { 380; Comparison happens in 16-bit 381; CHECK: setp.le.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}} 382; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]] 383; CHECK: ret 384 %cmp = icmp sle i8 %a, %b 385 %ret = zext i1 %cmp to i8 386 ret i8 %ret 387} 388