1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "evergreend.h"
25
26 #include "pipe/p_shader_tokens.h"
27 #include "util/u_pack_color.h"
28 #include "util/u_memory.h"
29 #include "util/u_framebuffer.h"
30 #include "util/u_dual_blend.h"
31 #include "evergreen_compute.h"
32
eg_num_banks(uint32_t nbanks)33 static uint32_t eg_num_banks(uint32_t nbanks)
34 {
35 switch (nbanks) {
36 case 2:
37 return 0;
38 case 4:
39 return 1;
40 case 8:
41 default:
42 return 2;
43 case 16:
44 return 3;
45 }
46 }
47
48
eg_tile_split(unsigned tile_split)49 static unsigned eg_tile_split(unsigned tile_split)
50 {
51 switch (tile_split) {
52 case 64: tile_split = 0; break;
53 case 128: tile_split = 1; break;
54 case 256: tile_split = 2; break;
55 case 512: tile_split = 3; break;
56 default:
57 case 1024: tile_split = 4; break;
58 case 2048: tile_split = 5; break;
59 case 4096: tile_split = 6; break;
60 }
61 return tile_split;
62 }
63
eg_macro_tile_aspect(unsigned macro_tile_aspect)64 static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
65 {
66 switch (macro_tile_aspect) {
67 default:
68 case 1: macro_tile_aspect = 0; break;
69 case 2: macro_tile_aspect = 1; break;
70 case 4: macro_tile_aspect = 2; break;
71 case 8: macro_tile_aspect = 3; break;
72 }
73 return macro_tile_aspect;
74 }
75
eg_bank_wh(unsigned bankwh)76 static unsigned eg_bank_wh(unsigned bankwh)
77 {
78 switch (bankwh) {
79 default:
80 case 1: bankwh = 0; break;
81 case 2: bankwh = 1; break;
82 case 4: bankwh = 2; break;
83 case 8: bankwh = 3; break;
84 }
85 return bankwh;
86 }
87
r600_translate_blend_function(int blend_func)88 static uint32_t r600_translate_blend_function(int blend_func)
89 {
90 switch (blend_func) {
91 case PIPE_BLEND_ADD:
92 return V_028780_COMB_DST_PLUS_SRC;
93 case PIPE_BLEND_SUBTRACT:
94 return V_028780_COMB_SRC_MINUS_DST;
95 case PIPE_BLEND_REVERSE_SUBTRACT:
96 return V_028780_COMB_DST_MINUS_SRC;
97 case PIPE_BLEND_MIN:
98 return V_028780_COMB_MIN_DST_SRC;
99 case PIPE_BLEND_MAX:
100 return V_028780_COMB_MAX_DST_SRC;
101 default:
102 R600_ERR("Unknown blend function %d\n", blend_func);
103 assert(0);
104 break;
105 }
106 return 0;
107 }
108
r600_translate_blend_factor(int blend_fact)109 static uint32_t r600_translate_blend_factor(int blend_fact)
110 {
111 switch (blend_fact) {
112 case PIPE_BLENDFACTOR_ONE:
113 return V_028780_BLEND_ONE;
114 case PIPE_BLENDFACTOR_SRC_COLOR:
115 return V_028780_BLEND_SRC_COLOR;
116 case PIPE_BLENDFACTOR_SRC_ALPHA:
117 return V_028780_BLEND_SRC_ALPHA;
118 case PIPE_BLENDFACTOR_DST_ALPHA:
119 return V_028780_BLEND_DST_ALPHA;
120 case PIPE_BLENDFACTOR_DST_COLOR:
121 return V_028780_BLEND_DST_COLOR;
122 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
123 return V_028780_BLEND_SRC_ALPHA_SATURATE;
124 case PIPE_BLENDFACTOR_CONST_COLOR:
125 return V_028780_BLEND_CONST_COLOR;
126 case PIPE_BLENDFACTOR_CONST_ALPHA:
127 return V_028780_BLEND_CONST_ALPHA;
128 case PIPE_BLENDFACTOR_ZERO:
129 return V_028780_BLEND_ZERO;
130 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
131 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
132 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
133 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
134 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
135 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
136 case PIPE_BLENDFACTOR_INV_DST_COLOR:
137 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
138 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
139 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
140 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
141 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
142 case PIPE_BLENDFACTOR_SRC1_COLOR:
143 return V_028780_BLEND_SRC1_COLOR;
144 case PIPE_BLENDFACTOR_SRC1_ALPHA:
145 return V_028780_BLEND_SRC1_ALPHA;
146 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
147 return V_028780_BLEND_INV_SRC1_COLOR;
148 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
149 return V_028780_BLEND_INV_SRC1_ALPHA;
150 default:
151 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
152 assert(0);
153 break;
154 }
155 return 0;
156 }
157
r600_tex_dim(unsigned dim,unsigned nr_samples)158 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
159 {
160 switch (dim) {
161 default:
162 case PIPE_TEXTURE_1D:
163 return V_030000_SQ_TEX_DIM_1D;
164 case PIPE_TEXTURE_1D_ARRAY:
165 return V_030000_SQ_TEX_DIM_1D_ARRAY;
166 case PIPE_TEXTURE_2D:
167 case PIPE_TEXTURE_RECT:
168 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
169 V_030000_SQ_TEX_DIM_2D;
170 case PIPE_TEXTURE_2D_ARRAY:
171 return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
172 V_030000_SQ_TEX_DIM_2D_ARRAY;
173 case PIPE_TEXTURE_3D:
174 return V_030000_SQ_TEX_DIM_3D;
175 case PIPE_TEXTURE_CUBE:
176 return V_030000_SQ_TEX_DIM_CUBEMAP;
177 }
178 }
179
r600_translate_dbformat(enum pipe_format format)180 static uint32_t r600_translate_dbformat(enum pipe_format format)
181 {
182 switch (format) {
183 case PIPE_FORMAT_Z16_UNORM:
184 return V_028040_Z_16;
185 case PIPE_FORMAT_Z24X8_UNORM:
186 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
187 return V_028040_Z_24;
188 case PIPE_FORMAT_Z32_FLOAT:
189 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
190 return V_028040_Z_32_FLOAT;
191 default:
192 return ~0U;
193 }
194 }
195
r600_translate_colorswap(enum pipe_format format)196 static uint32_t r600_translate_colorswap(enum pipe_format format)
197 {
198 switch (format) {
199 /* 8-bit buffers. */
200 case PIPE_FORMAT_L4A4_UNORM:
201 case PIPE_FORMAT_A4R4_UNORM:
202 return V_028C70_SWAP_ALT;
203
204 case PIPE_FORMAT_A8_UNORM:
205 case PIPE_FORMAT_A8_SNORM:
206 case PIPE_FORMAT_A8_UINT:
207 case PIPE_FORMAT_A8_SINT:
208 case PIPE_FORMAT_A16_UNORM:
209 case PIPE_FORMAT_A16_SNORM:
210 case PIPE_FORMAT_A16_UINT:
211 case PIPE_FORMAT_A16_SINT:
212 case PIPE_FORMAT_A16_FLOAT:
213 case PIPE_FORMAT_A32_UINT:
214 case PIPE_FORMAT_A32_SINT:
215 case PIPE_FORMAT_A32_FLOAT:
216 case PIPE_FORMAT_R4A4_UNORM:
217 return V_028C70_SWAP_ALT_REV;
218 case PIPE_FORMAT_I8_UNORM:
219 case PIPE_FORMAT_I8_SNORM:
220 case PIPE_FORMAT_I8_UINT:
221 case PIPE_FORMAT_I8_SINT:
222 case PIPE_FORMAT_I16_UNORM:
223 case PIPE_FORMAT_I16_SNORM:
224 case PIPE_FORMAT_I16_UINT:
225 case PIPE_FORMAT_I16_SINT:
226 case PIPE_FORMAT_I16_FLOAT:
227 case PIPE_FORMAT_I32_UINT:
228 case PIPE_FORMAT_I32_SINT:
229 case PIPE_FORMAT_I32_FLOAT:
230 case PIPE_FORMAT_L8_UNORM:
231 case PIPE_FORMAT_L8_SNORM:
232 case PIPE_FORMAT_L8_UINT:
233 case PIPE_FORMAT_L8_SINT:
234 case PIPE_FORMAT_L8_SRGB:
235 case PIPE_FORMAT_L16_UNORM:
236 case PIPE_FORMAT_L16_SNORM:
237 case PIPE_FORMAT_L16_UINT:
238 case PIPE_FORMAT_L16_SINT:
239 case PIPE_FORMAT_L16_FLOAT:
240 case PIPE_FORMAT_L32_UINT:
241 case PIPE_FORMAT_L32_SINT:
242 case PIPE_FORMAT_L32_FLOAT:
243 case PIPE_FORMAT_R8_UNORM:
244 case PIPE_FORMAT_R8_SNORM:
245 case PIPE_FORMAT_R8_UINT:
246 case PIPE_FORMAT_R8_SINT:
247 return V_028C70_SWAP_STD;
248
249 /* 16-bit buffers. */
250 case PIPE_FORMAT_B5G6R5_UNORM:
251 return V_028C70_SWAP_STD_REV;
252
253 case PIPE_FORMAT_B5G5R5A1_UNORM:
254 case PIPE_FORMAT_B5G5R5X1_UNORM:
255 return V_028C70_SWAP_ALT;
256
257 case PIPE_FORMAT_B4G4R4A4_UNORM:
258 case PIPE_FORMAT_B4G4R4X4_UNORM:
259 return V_028C70_SWAP_ALT;
260
261 case PIPE_FORMAT_Z16_UNORM:
262 return V_028C70_SWAP_STD;
263
264 case PIPE_FORMAT_L8A8_UNORM:
265 case PIPE_FORMAT_L8A8_SNORM:
266 case PIPE_FORMAT_L8A8_UINT:
267 case PIPE_FORMAT_L8A8_SINT:
268 case PIPE_FORMAT_L8A8_SRGB:
269 case PIPE_FORMAT_L16A16_UNORM:
270 case PIPE_FORMAT_L16A16_SNORM:
271 case PIPE_FORMAT_L16A16_UINT:
272 case PIPE_FORMAT_L16A16_SINT:
273 case PIPE_FORMAT_L16A16_FLOAT:
274 case PIPE_FORMAT_L32A32_UINT:
275 case PIPE_FORMAT_L32A32_SINT:
276 case PIPE_FORMAT_L32A32_FLOAT:
277 return V_028C70_SWAP_ALT;
278 case PIPE_FORMAT_R8G8_UNORM:
279 case PIPE_FORMAT_R8G8_SNORM:
280 case PIPE_FORMAT_R8G8_UINT:
281 case PIPE_FORMAT_R8G8_SINT:
282 return V_028C70_SWAP_STD;
283
284 case PIPE_FORMAT_R16_UNORM:
285 case PIPE_FORMAT_R16_SNORM:
286 case PIPE_FORMAT_R16_UINT:
287 case PIPE_FORMAT_R16_SINT:
288 case PIPE_FORMAT_R16_FLOAT:
289 return V_028C70_SWAP_STD;
290
291 /* 32-bit buffers. */
292 case PIPE_FORMAT_A8B8G8R8_SRGB:
293 return V_028C70_SWAP_STD_REV;
294 case PIPE_FORMAT_B8G8R8A8_SRGB:
295 return V_028C70_SWAP_ALT;
296
297 case PIPE_FORMAT_B8G8R8A8_UNORM:
298 case PIPE_FORMAT_B8G8R8X8_UNORM:
299 return V_028C70_SWAP_ALT;
300
301 case PIPE_FORMAT_A8R8G8B8_UNORM:
302 case PIPE_FORMAT_X8R8G8B8_UNORM:
303 return V_028C70_SWAP_ALT_REV;
304 case PIPE_FORMAT_R8G8B8A8_SNORM:
305 case PIPE_FORMAT_R8G8B8A8_UNORM:
306 case PIPE_FORMAT_R8G8B8A8_SINT:
307 case PIPE_FORMAT_R8G8B8A8_UINT:
308 case PIPE_FORMAT_R8G8B8X8_UNORM:
309 return V_028C70_SWAP_STD;
310
311 case PIPE_FORMAT_A8B8G8R8_UNORM:
312 case PIPE_FORMAT_X8B8G8R8_UNORM:
313 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
314 return V_028C70_SWAP_STD_REV;
315
316 case PIPE_FORMAT_Z24X8_UNORM:
317 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
318 return V_028C70_SWAP_STD;
319
320 case PIPE_FORMAT_X8Z24_UNORM:
321 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
322 return V_028C70_SWAP_STD;
323
324 case PIPE_FORMAT_R10G10B10A2_UNORM:
325 case PIPE_FORMAT_R10G10B10X2_SNORM:
326 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
327 return V_028C70_SWAP_STD;
328
329 case PIPE_FORMAT_B10G10R10A2_UNORM:
330 case PIPE_FORMAT_B10G10R10A2_UINT:
331 return V_028C70_SWAP_ALT;
332
333 case PIPE_FORMAT_R11G11B10_FLOAT:
334 case PIPE_FORMAT_R32_FLOAT:
335 case PIPE_FORMAT_R32_UINT:
336 case PIPE_FORMAT_R32_SINT:
337 case PIPE_FORMAT_Z32_FLOAT:
338 case PIPE_FORMAT_R16G16_FLOAT:
339 case PIPE_FORMAT_R16G16_UNORM:
340 case PIPE_FORMAT_R16G16_SNORM:
341 case PIPE_FORMAT_R16G16_UINT:
342 case PIPE_FORMAT_R16G16_SINT:
343 return V_028C70_SWAP_STD;
344
345 /* 64-bit buffers. */
346 case PIPE_FORMAT_R32G32_FLOAT:
347 case PIPE_FORMAT_R32G32_UINT:
348 case PIPE_FORMAT_R32G32_SINT:
349 case PIPE_FORMAT_R16G16B16A16_UNORM:
350 case PIPE_FORMAT_R16G16B16A16_SNORM:
351 case PIPE_FORMAT_R16G16B16A16_UINT:
352 case PIPE_FORMAT_R16G16B16A16_SINT:
353 case PIPE_FORMAT_R16G16B16A16_FLOAT:
354 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
355
356 /* 128-bit buffers. */
357 case PIPE_FORMAT_R32G32B32A32_FLOAT:
358 case PIPE_FORMAT_R32G32B32A32_SNORM:
359 case PIPE_FORMAT_R32G32B32A32_UNORM:
360 case PIPE_FORMAT_R32G32B32A32_SINT:
361 case PIPE_FORMAT_R32G32B32A32_UINT:
362 return V_028C70_SWAP_STD;
363 default:
364 R600_ERR("unsupported colorswap format %d\n", format);
365 return ~0U;
366 }
367 return ~0U;
368 }
369
r600_translate_colorformat(enum pipe_format format)370 static uint32_t r600_translate_colorformat(enum pipe_format format)
371 {
372 switch (format) {
373 /* 8-bit buffers. */
374 case PIPE_FORMAT_A8_UNORM:
375 case PIPE_FORMAT_A8_SNORM:
376 case PIPE_FORMAT_A8_UINT:
377 case PIPE_FORMAT_A8_SINT:
378 case PIPE_FORMAT_I8_UNORM:
379 case PIPE_FORMAT_I8_SNORM:
380 case PIPE_FORMAT_I8_UINT:
381 case PIPE_FORMAT_I8_SINT:
382 case PIPE_FORMAT_L8_UNORM:
383 case PIPE_FORMAT_L8_SNORM:
384 case PIPE_FORMAT_L8_UINT:
385 case PIPE_FORMAT_L8_SINT:
386 case PIPE_FORMAT_L8_SRGB:
387 case PIPE_FORMAT_R8_UNORM:
388 case PIPE_FORMAT_R8_SNORM:
389 case PIPE_FORMAT_R8_UINT:
390 case PIPE_FORMAT_R8_SINT:
391 return V_028C70_COLOR_8;
392
393 /* 16-bit buffers. */
394 case PIPE_FORMAT_B5G6R5_UNORM:
395 return V_028C70_COLOR_5_6_5;
396
397 case PIPE_FORMAT_B5G5R5A1_UNORM:
398 case PIPE_FORMAT_B5G5R5X1_UNORM:
399 return V_028C70_COLOR_1_5_5_5;
400
401 case PIPE_FORMAT_B4G4R4A4_UNORM:
402 case PIPE_FORMAT_B4G4R4X4_UNORM:
403 return V_028C70_COLOR_4_4_4_4;
404
405 case PIPE_FORMAT_Z16_UNORM:
406 return V_028C70_COLOR_16;
407
408 case PIPE_FORMAT_L8A8_UNORM:
409 case PIPE_FORMAT_L8A8_SNORM:
410 case PIPE_FORMAT_L8A8_UINT:
411 case PIPE_FORMAT_L8A8_SINT:
412 case PIPE_FORMAT_L8A8_SRGB:
413 case PIPE_FORMAT_R8G8_UNORM:
414 case PIPE_FORMAT_R8G8_SNORM:
415 case PIPE_FORMAT_R8G8_UINT:
416 case PIPE_FORMAT_R8G8_SINT:
417 return V_028C70_COLOR_8_8;
418
419 case PIPE_FORMAT_R16_UNORM:
420 case PIPE_FORMAT_R16_SNORM:
421 case PIPE_FORMAT_R16_UINT:
422 case PIPE_FORMAT_R16_SINT:
423 case PIPE_FORMAT_A16_UNORM:
424 case PIPE_FORMAT_A16_SNORM:
425 case PIPE_FORMAT_A16_UINT:
426 case PIPE_FORMAT_A16_SINT:
427 case PIPE_FORMAT_L16_UNORM:
428 case PIPE_FORMAT_L16_SNORM:
429 case PIPE_FORMAT_L16_UINT:
430 case PIPE_FORMAT_L16_SINT:
431 case PIPE_FORMAT_I16_UNORM:
432 case PIPE_FORMAT_I16_SNORM:
433 case PIPE_FORMAT_I16_UINT:
434 case PIPE_FORMAT_I16_SINT:
435 return V_028C70_COLOR_16;
436
437 case PIPE_FORMAT_R16_FLOAT:
438 case PIPE_FORMAT_A16_FLOAT:
439 case PIPE_FORMAT_L16_FLOAT:
440 case PIPE_FORMAT_I16_FLOAT:
441 return V_028C70_COLOR_16_FLOAT;
442
443 /* 32-bit buffers. */
444 case PIPE_FORMAT_A8B8G8R8_SRGB:
445 case PIPE_FORMAT_A8B8G8R8_UNORM:
446 case PIPE_FORMAT_A8R8G8B8_UNORM:
447 case PIPE_FORMAT_B8G8R8A8_SRGB:
448 case PIPE_FORMAT_B8G8R8A8_UNORM:
449 case PIPE_FORMAT_B8G8R8X8_UNORM:
450 case PIPE_FORMAT_R8G8B8A8_SNORM:
451 case PIPE_FORMAT_R8G8B8A8_UNORM:
452 case PIPE_FORMAT_R8G8B8X8_UNORM:
453 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
454 case PIPE_FORMAT_X8B8G8R8_UNORM:
455 case PIPE_FORMAT_X8R8G8B8_UNORM:
456 case PIPE_FORMAT_R8G8B8_UNORM:
457 case PIPE_FORMAT_R8G8B8A8_SINT:
458 case PIPE_FORMAT_R8G8B8A8_UINT:
459 return V_028C70_COLOR_8_8_8_8;
460
461 case PIPE_FORMAT_R10G10B10A2_UNORM:
462 case PIPE_FORMAT_R10G10B10X2_SNORM:
463 case PIPE_FORMAT_B10G10R10A2_UNORM:
464 case PIPE_FORMAT_B10G10R10A2_UINT:
465 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
466 return V_028C70_COLOR_2_10_10_10;
467
468 case PIPE_FORMAT_Z24X8_UNORM:
469 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
470 return V_028C70_COLOR_8_24;
471
472 case PIPE_FORMAT_X8Z24_UNORM:
473 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
474 return V_028C70_COLOR_24_8;
475
476 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
477 return V_028C70_COLOR_X24_8_32_FLOAT;
478
479 case PIPE_FORMAT_R32_UINT:
480 case PIPE_FORMAT_R32_SINT:
481 case PIPE_FORMAT_A32_UINT:
482 case PIPE_FORMAT_A32_SINT:
483 case PIPE_FORMAT_L32_UINT:
484 case PIPE_FORMAT_L32_SINT:
485 case PIPE_FORMAT_I32_UINT:
486 case PIPE_FORMAT_I32_SINT:
487 return V_028C70_COLOR_32;
488
489 case PIPE_FORMAT_R32_FLOAT:
490 case PIPE_FORMAT_A32_FLOAT:
491 case PIPE_FORMAT_L32_FLOAT:
492 case PIPE_FORMAT_I32_FLOAT:
493 case PIPE_FORMAT_Z32_FLOAT:
494 return V_028C70_COLOR_32_FLOAT;
495
496 case PIPE_FORMAT_R16G16_FLOAT:
497 case PIPE_FORMAT_L16A16_FLOAT:
498 return V_028C70_COLOR_16_16_FLOAT;
499
500 case PIPE_FORMAT_R16G16_UNORM:
501 case PIPE_FORMAT_R16G16_SNORM:
502 case PIPE_FORMAT_R16G16_UINT:
503 case PIPE_FORMAT_R16G16_SINT:
504 case PIPE_FORMAT_L16A16_UNORM:
505 case PIPE_FORMAT_L16A16_SNORM:
506 case PIPE_FORMAT_L16A16_UINT:
507 case PIPE_FORMAT_L16A16_SINT:
508 return V_028C70_COLOR_16_16;
509
510 case PIPE_FORMAT_R11G11B10_FLOAT:
511 return V_028C70_COLOR_10_11_11_FLOAT;
512
513 /* 64-bit buffers. */
514 case PIPE_FORMAT_R16G16B16A16_UINT:
515 case PIPE_FORMAT_R16G16B16A16_SINT:
516 case PIPE_FORMAT_R16G16B16A16_UNORM:
517 case PIPE_FORMAT_R16G16B16A16_SNORM:
518 return V_028C70_COLOR_16_16_16_16;
519
520 case PIPE_FORMAT_R16G16B16A16_FLOAT:
521 return V_028C70_COLOR_16_16_16_16_FLOAT;
522
523 case PIPE_FORMAT_R32G32_FLOAT:
524 case PIPE_FORMAT_L32A32_FLOAT:
525 return V_028C70_COLOR_32_32_FLOAT;
526
527 case PIPE_FORMAT_R32G32_SINT:
528 case PIPE_FORMAT_R32G32_UINT:
529 case PIPE_FORMAT_L32A32_UINT:
530 case PIPE_FORMAT_L32A32_SINT:
531 return V_028C70_COLOR_32_32;
532
533 /* 128-bit buffers. */
534 case PIPE_FORMAT_R32G32B32A32_SNORM:
535 case PIPE_FORMAT_R32G32B32A32_UNORM:
536 case PIPE_FORMAT_R32G32B32A32_SINT:
537 case PIPE_FORMAT_R32G32B32A32_UINT:
538 return V_028C70_COLOR_32_32_32_32;
539 case PIPE_FORMAT_R32G32B32A32_FLOAT:
540 return V_028C70_COLOR_32_32_32_32_FLOAT;
541
542 /* YUV buffers. */
543 case PIPE_FORMAT_UYVY:
544 case PIPE_FORMAT_YUYV:
545 default:
546 return ~0U; /* Unsupported. */
547 }
548 }
549
r600_colorformat_endian_swap(uint32_t colorformat)550 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
551 {
552 if (R600_BIG_ENDIAN) {
553 switch(colorformat) {
554
555 /* 8-bit buffers. */
556 case V_028C70_COLOR_8:
557 return ENDIAN_NONE;
558
559 /* 16-bit buffers. */
560 case V_028C70_COLOR_5_6_5:
561 case V_028C70_COLOR_1_5_5_5:
562 case V_028C70_COLOR_4_4_4_4:
563 case V_028C70_COLOR_16:
564 case V_028C70_COLOR_8_8:
565 return ENDIAN_8IN16;
566
567 /* 32-bit buffers. */
568 case V_028C70_COLOR_8_8_8_8:
569 case V_028C70_COLOR_2_10_10_10:
570 case V_028C70_COLOR_8_24:
571 case V_028C70_COLOR_24_8:
572 case V_028C70_COLOR_32_FLOAT:
573 case V_028C70_COLOR_16_16_FLOAT:
574 case V_028C70_COLOR_16_16:
575 return ENDIAN_8IN32;
576
577 /* 64-bit buffers. */
578 case V_028C70_COLOR_16_16_16_16:
579 case V_028C70_COLOR_16_16_16_16_FLOAT:
580 return ENDIAN_8IN16;
581
582 case V_028C70_COLOR_32_32_FLOAT:
583 case V_028C70_COLOR_32_32:
584 case V_028C70_COLOR_X24_8_32_FLOAT:
585 return ENDIAN_8IN32;
586
587 /* 96-bit buffers. */
588 case V_028C70_COLOR_32_32_32_FLOAT:
589 /* 128-bit buffers. */
590 case V_028C70_COLOR_32_32_32_32_FLOAT:
591 case V_028C70_COLOR_32_32_32_32:
592 return ENDIAN_8IN32;
593 default:
594 return ENDIAN_NONE; /* Unsupported. */
595 }
596 } else {
597 return ENDIAN_NONE;
598 }
599 }
600
r600_is_sampler_format_supported(struct pipe_screen * screen,enum pipe_format format)601 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
602 {
603 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
604 }
605
r600_is_colorbuffer_format_supported(enum pipe_format format)606 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
607 {
608 return r600_translate_colorformat(format) != ~0U &&
609 r600_translate_colorswap(format) != ~0U;
610 }
611
r600_is_zs_format_supported(enum pipe_format format)612 static bool r600_is_zs_format_supported(enum pipe_format format)
613 {
614 return r600_translate_dbformat(format) != ~0U;
615 }
616
evergreen_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned usage)617 boolean evergreen_is_format_supported(struct pipe_screen *screen,
618 enum pipe_format format,
619 enum pipe_texture_target target,
620 unsigned sample_count,
621 unsigned usage)
622 {
623 struct r600_screen *rscreen = (struct r600_screen*)screen;
624 unsigned retval = 0;
625
626 if (target >= PIPE_MAX_TEXTURE_TYPES) {
627 R600_ERR("r600: unsupported texture type %d\n", target);
628 return FALSE;
629 }
630
631 if (!util_format_is_supported(format, usage))
632 return FALSE;
633
634 if (sample_count > 1) {
635 if (rscreen->info.drm_minor < 19)
636 return FALSE;
637
638 switch (sample_count) {
639 case 2:
640 case 4:
641 case 8:
642 break;
643 default:
644 return FALSE;
645 }
646 }
647
648 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
649 r600_is_sampler_format_supported(screen, format)) {
650 retval |= PIPE_BIND_SAMPLER_VIEW;
651 }
652
653 if ((usage & (PIPE_BIND_RENDER_TARGET |
654 PIPE_BIND_DISPLAY_TARGET |
655 PIPE_BIND_SCANOUT |
656 PIPE_BIND_SHARED)) &&
657 r600_is_colorbuffer_format_supported(format)) {
658 retval |= usage &
659 (PIPE_BIND_RENDER_TARGET |
660 PIPE_BIND_DISPLAY_TARGET |
661 PIPE_BIND_SCANOUT |
662 PIPE_BIND_SHARED);
663 }
664
665 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
666 r600_is_zs_format_supported(format)) {
667 retval |= PIPE_BIND_DEPTH_STENCIL;
668 }
669
670 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
671 r600_is_vertex_format_supported(format)) {
672 retval |= PIPE_BIND_VERTEX_BUFFER;
673 }
674
675 if (usage & PIPE_BIND_TRANSFER_READ)
676 retval |= PIPE_BIND_TRANSFER_READ;
677 if (usage & PIPE_BIND_TRANSFER_WRITE)
678 retval |= PIPE_BIND_TRANSFER_WRITE;
679
680 return retval == usage;
681 }
682
evergreen_create_blend_state_mode(struct pipe_context * ctx,const struct pipe_blend_state * state,int mode)683 static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
684 const struct pipe_blend_state *state, int mode)
685 {
686 struct r600_context *rctx = (struct r600_context *)ctx;
687 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
688 struct r600_pipe_state *rstate;
689 uint32_t color_control = 0, target_mask;
690 /* XXX there is more then 8 framebuffer */
691 unsigned blend_cntl[8];
692
693 if (blend == NULL) {
694 return NULL;
695 }
696
697 rstate = &blend->rstate;
698
699 rstate->id = R600_PIPE_STATE_BLEND;
700
701 target_mask = 0;
702 if (state->logicop_enable) {
703 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
704 } else {
705 color_control |= (0xcc << 16);
706 }
707 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
708 if (state->independent_blend_enable) {
709 for (int i = 0; i < 8; i++) {
710 target_mask |= (state->rt[i].colormask << (4 * i));
711 }
712 } else {
713 for (int i = 0; i < 8; i++) {
714 target_mask |= (state->rt[0].colormask << (4 * i));
715 }
716 }
717 blend->cb_target_mask = target_mask;
718
719 if (target_mask)
720 color_control |= S_028808_MODE(mode);
721 else
722 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
723
724 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
725 color_control);
726 /* only have dual source on MRT0 */
727 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
728 for (int i = 0; i < 8; i++) {
729 /* state->rt entries > 0 only written if independent blending */
730 const int j = state->independent_blend_enable ? i : 0;
731
732 unsigned eqRGB = state->rt[j].rgb_func;
733 unsigned srcRGB = state->rt[j].rgb_src_factor;
734 unsigned dstRGB = state->rt[j].rgb_dst_factor;
735 unsigned eqA = state->rt[j].alpha_func;
736 unsigned srcA = state->rt[j].alpha_src_factor;
737 unsigned dstA = state->rt[j].alpha_dst_factor;
738
739 blend_cntl[i] = 0;
740 if (!state->rt[j].blend_enable)
741 continue;
742
743 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
744 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
745 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
746 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
747
748 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
749 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
750 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
751 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
752 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
753 }
754 }
755 for (int i = 0; i < 8; i++) {
756 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
757 }
758
759 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK,
760 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
761 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
762 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
763 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
764 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
765
766 blend->alpha_to_one = state->alpha_to_one;
767 return rstate;
768 }
769
evergreen_create_blend_state(struct pipe_context * ctx,const struct pipe_blend_state * state)770 static void *evergreen_create_blend_state(struct pipe_context *ctx,
771 const struct pipe_blend_state *state)
772 {
773
774 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
775 }
776
evergreen_create_dsa_state(struct pipe_context * ctx,const struct pipe_depth_stencil_alpha_state * state)777 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
778 const struct pipe_depth_stencil_alpha_state *state)
779 {
780 struct r600_context *rctx = (struct r600_context *)ctx;
781 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
782 unsigned db_depth_control, alpha_test_control, alpha_ref;
783 struct r600_pipe_state *rstate;
784
785 if (dsa == NULL) {
786 return NULL;
787 }
788
789 dsa->valuemask[0] = state->stencil[0].valuemask;
790 dsa->valuemask[1] = state->stencil[1].valuemask;
791 dsa->writemask[0] = state->stencil[0].writemask;
792 dsa->writemask[1] = state->stencil[1].writemask;
793
794 rstate = &dsa->rstate;
795
796 rstate->id = R600_PIPE_STATE_DSA;
797 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
798 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
799 S_028800_ZFUNC(state->depth.func);
800
801 /* stencil */
802 if (state->stencil[0].enabled) {
803 db_depth_control |= S_028800_STENCIL_ENABLE(1);
804 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
805 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
806 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
807 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
808
809 if (state->stencil[1].enabled) {
810 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
811 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
812 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
813 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
814 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
815 }
816 }
817
818 /* alpha */
819 alpha_test_control = 0;
820 alpha_ref = 0;
821 if (state->alpha.enabled) {
822 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
823 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
824 alpha_ref = fui(state->alpha.ref_value);
825 }
826 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
827 dsa->alpha_ref = alpha_ref;
828
829 /* misc */
830 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
831 return rstate;
832 }
833
evergreen_create_rs_state(struct pipe_context * ctx,const struct pipe_rasterizer_state * state)834 static void *evergreen_create_rs_state(struct pipe_context *ctx,
835 const struct pipe_rasterizer_state *state)
836 {
837 struct r600_context *rctx = (struct r600_context *)ctx;
838 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
839 struct r600_pipe_state *rstate;
840 unsigned tmp;
841 unsigned prov_vtx = 1, polygon_dual_mode;
842 float psize_min, psize_max;
843
844 if (rs == NULL) {
845 return NULL;
846 }
847
848 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
849 state->fill_back != PIPE_POLYGON_MODE_FILL);
850
851 if (state->flatshade_first)
852 prov_vtx = 0;
853
854 rstate = &rs->rstate;
855 rs->flatshade = state->flatshade;
856 rs->sprite_coord_enable = state->sprite_coord_enable;
857 rs->two_side = state->light_twoside;
858 rs->clip_plane_enable = state->clip_plane_enable;
859 rs->pa_sc_line_stipple = state->line_stipple_enable ?
860 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
861 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
862 rs->pa_cl_clip_cntl =
863 S_028810_PS_UCP_MODE(3) |
864 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
865 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
866 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
867 rs->multisample_enable = state->multisample;
868
869 /* offset */
870 rs->offset_units = state->offset_units;
871 rs->offset_scale = state->offset_scale * 12.0f;
872
873 rstate->id = R600_PIPE_STATE_RASTERIZER;
874 tmp = S_0286D4_FLAT_SHADE_ENA(1);
875 if (state->sprite_coord_enable) {
876 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
877 S_0286D4_PNT_SPRITE_OVRD_X(2) |
878 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
879 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
880 S_0286D4_PNT_SPRITE_OVRD_W(1);
881 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
882 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
883 }
884 }
885 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
886
887 /* point size 12.4 fixed point */
888 tmp = (unsigned)(state->point_size * 8.0);
889 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
890
891 if (state->point_size_per_vertex) {
892 psize_min = util_get_min_point_size(state);
893 psize_max = 8192;
894 } else {
895 /* Force the point size to be as if the vertex output was disabled. */
896 psize_min = state->point_size;
897 psize_max = state->point_size;
898 }
899 /* Divide by two, because 0.5 = 1 pixel. */
900 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
901 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
902 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
903
904 tmp = (unsigned)state->line_width * 8;
905 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
906 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
907 S_028A48_MSAA_ENABLE(state->multisample) |
908 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
909 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
910
911 if (rctx->chip_class == CAYMAN) {
912 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
913 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
914 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
915 } else {
916 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
917 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
918 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
919 }
920 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
921 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
922 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
923 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
924 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
925 S_028814_FACE(!state->front_ccw) |
926 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
927 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
928 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
929 S_028814_POLY_MODE(polygon_dual_mode) |
930 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
931 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
932 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
933 return rstate;
934 }
935
evergreen_create_sampler_state(struct pipe_context * ctx,const struct pipe_sampler_state * state)936 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
937 const struct pipe_sampler_state *state)
938 {
939 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
940 union util_color uc;
941 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
942
943 if (ss == NULL) {
944 return NULL;
945 }
946
947 /* directly into sampler avoid r6xx code to emit useless reg */
948 ss->seamless_cube_map = false;
949 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
950 ss->border_color_use = false;
951 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
952 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
953 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
954 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
955 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
956 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
957 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
958 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
959 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
960 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
961 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
962 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
963 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
964 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
965 ss->tex_sampler_words[2] = S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
966 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
967 S_03C008_TYPE(1);
968 if (uc.ui) {
969 ss->border_color_use = true;
970 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
971 ss->border_color[0] = fui(state->border_color.f[0]);
972 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
973 ss->border_color[1] = fui(state->border_color.f[1]);
974 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
975 ss->border_color[2] = fui(state->border_color.f[2]);
976 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
977 ss->border_color[3] = fui(state->border_color.f[3]);
978 }
979 return ss;
980 }
981
evergreen_create_sampler_view(struct pipe_context * ctx,struct pipe_resource * texture,const struct pipe_sampler_view * state)982 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
983 struct pipe_resource *texture,
984 const struct pipe_sampler_view *state)
985 {
986 struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
987 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
988 struct r600_texture *tmp = (struct r600_texture*)texture;
989 unsigned format, endian;
990 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
991 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
992 unsigned height, depth, width;
993 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
994
995 if (view == NULL)
996 return NULL;
997
998 /* initialize base object */
999 view->base = *state;
1000 view->base.texture = NULL;
1001 pipe_reference(NULL, &texture->reference);
1002 view->base.texture = texture;
1003 view->base.reference.count = 1;
1004 view->base.context = ctx;
1005
1006 swizzle[0] = state->swizzle_r;
1007 swizzle[1] = state->swizzle_g;
1008 swizzle[2] = state->swizzle_b;
1009 swizzle[3] = state->swizzle_a;
1010
1011 format = r600_translate_texformat(ctx->screen, state->format,
1012 swizzle,
1013 &word4, &yuv_format);
1014 assert(format != ~0);
1015 if (format == ~0) {
1016 FREE(view);
1017 return NULL;
1018 }
1019
1020 if (tmp->is_depth && !tmp->is_flushing_texture) {
1021 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1022 FREE(view);
1023 return NULL;
1024 }
1025 tmp = tmp->flushed_depth_texture;
1026 }
1027
1028 endian = r600_colorformat_endian_swap(format);
1029
1030 width = tmp->surface.level[0].npix_x;
1031 height = tmp->surface.level[0].npix_y;
1032 depth = tmp->surface.level[0].npix_z;
1033 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1034 tile_type = tmp->tile_type;
1035
1036 switch (tmp->surface.level[0].mode) {
1037 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1038 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1039 break;
1040 case RADEON_SURF_MODE_2D:
1041 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1042 break;
1043 case RADEON_SURF_MODE_1D:
1044 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1045 break;
1046 case RADEON_SURF_MODE_LINEAR:
1047 default:
1048 array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1049 break;
1050 }
1051 tile_split = tmp->surface.tile_split;
1052 macro_aspect = tmp->surface.mtilea;
1053 bankw = tmp->surface.bankw;
1054 bankh = tmp->surface.bankh;
1055 tile_split = eg_tile_split(tile_split);
1056 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1057 bankw = eg_bank_wh(bankw);
1058 bankh = eg_bank_wh(bankh);
1059
1060 /* 128 bit formats require tile type = 1 */
1061 if (rscreen->chip_class == CAYMAN) {
1062 if (util_format_get_blocksize(state->format) >= 16)
1063 tile_type = 1;
1064 }
1065 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1066
1067 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1068 height = 1;
1069 depth = texture->array_size;
1070 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1071 depth = texture->array_size;
1072 }
1073
1074 view->tex_resource = &tmp->resource;
1075 view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1076 S_030000_PITCH((pitch / 8) - 1) |
1077 S_030000_TEX_WIDTH(width - 1));
1078 if (rscreen->chip_class == CAYMAN)
1079 view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1080 else
1081 view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1082 view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1083 S_030004_TEX_DEPTH(depth - 1) |
1084 S_030004_ARRAY_MODE(array_mode));
1085 view->tex_resource_words[2] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1086 if (state->u.tex.last_level && texture->nr_samples <= 1) {
1087 view->tex_resource_words[3] = (tmp->surface.level[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1088 } else {
1089 view->tex_resource_words[3] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1090 }
1091 view->tex_resource_words[4] = (word4 |
1092 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1093 S_030010_ENDIAN_SWAP(endian));
1094 view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1095 S_030014_LAST_ARRAY(state->u.tex.last_layer);
1096 if (texture->nr_samples > 1) {
1097 unsigned log_samples = util_logbase2(texture->nr_samples);
1098 if (rscreen->chip_class == CAYMAN) {
1099 view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
1100 }
1101 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1102 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
1103 } else {
1104 view->tex_resource_words[4] |= S_030010_BASE_LEVEL(state->u.tex.first_level);
1105 view->tex_resource_words[5] |= S_030014_LAST_LEVEL(state->u.tex.last_level);
1106 }
1107 /* aniso max 16 samples */
1108 view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
1109 (S_030018_TILE_SPLIT(tile_split));
1110 view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1111 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1112 S_03001C_BANK_WIDTH(bankw) |
1113 S_03001C_BANK_HEIGHT(bankh) |
1114 S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1115 S_03001C_NUM_BANKS(nbanks);
1116 return &view->base;
1117 }
1118
evergreen_set_vs_sampler_views(struct pipe_context * ctx,unsigned count,struct pipe_sampler_view ** views)1119 static void evergreen_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1120 struct pipe_sampler_view **views)
1121 {
1122 r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
1123 }
1124
evergreen_set_ps_sampler_views(struct pipe_context * ctx,unsigned count,struct pipe_sampler_view ** views)1125 static void evergreen_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1126 struct pipe_sampler_view **views)
1127 {
1128 r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
1129 }
1130
evergreen_set_clip_state(struct pipe_context * ctx,const struct pipe_clip_state * state)1131 static void evergreen_set_clip_state(struct pipe_context *ctx,
1132 const struct pipe_clip_state *state)
1133 {
1134 struct r600_context *rctx = (struct r600_context *)ctx;
1135 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1136 struct pipe_constant_buffer cb;
1137
1138 if (rstate == NULL)
1139 return;
1140
1141 rctx->clip = *state;
1142 rstate->id = R600_PIPE_STATE_CLIP;
1143 for (int i = 0; i < 6; i++) {
1144 r600_pipe_state_add_reg(rstate,
1145 R_0285BC_PA_CL_UCP0_X + i * 16,
1146 fui(state->ucp[i][0]));
1147 r600_pipe_state_add_reg(rstate,
1148 R_0285C0_PA_CL_UCP0_Y + i * 16,
1149 fui(state->ucp[i][1]) );
1150 r600_pipe_state_add_reg(rstate,
1151 R_0285C4_PA_CL_UCP0_Z + i * 16,
1152 fui(state->ucp[i][2]));
1153 r600_pipe_state_add_reg(rstate,
1154 R_0285C8_PA_CL_UCP0_W + i * 16,
1155 fui(state->ucp[i][3]));
1156 }
1157
1158 free(rctx->states[R600_PIPE_STATE_CLIP]);
1159 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1160 r600_context_pipe_state_set(rctx, rstate);
1161
1162 cb.buffer = NULL;
1163 cb.user_buffer = state->ucp;
1164 cb.buffer_offset = 0;
1165 cb.buffer_size = 4*4*8;
1166 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1167 pipe_resource_reference(&cb.buffer, NULL);
1168 }
1169
evergreen_set_polygon_stipple(struct pipe_context * ctx,const struct pipe_poly_stipple * state)1170 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1171 const struct pipe_poly_stipple *state)
1172 {
1173 }
1174
evergreen_get_scissor_rect(struct r600_context * rctx,unsigned tl_x,unsigned tl_y,unsigned br_x,unsigned br_y,uint32_t * tl,uint32_t * br)1175 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1176 unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1177 uint32_t *tl, uint32_t *br)
1178 {
1179 /* EG hw workaround */
1180 if (br_x == 0)
1181 tl_x = 1;
1182 if (br_y == 0)
1183 tl_y = 1;
1184
1185 /* cayman hw workaround */
1186 if (rctx->chip_class == CAYMAN) {
1187 if (br_x == 1 && br_y == 1)
1188 br_x = 2;
1189 }
1190
1191 *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1192 *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1193 }
1194
evergreen_set_scissor_state(struct pipe_context * ctx,const struct pipe_scissor_state * state)1195 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1196 const struct pipe_scissor_state *state)
1197 {
1198 struct r600_context *rctx = (struct r600_context *)ctx;
1199 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1200 uint32_t tl, br;
1201
1202 if (rstate == NULL)
1203 return;
1204
1205 evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1206
1207 rstate->id = R600_PIPE_STATE_SCISSOR;
1208 r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1209 r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1210
1211 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1212 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1213 r600_context_pipe_state_set(rctx, rstate);
1214 }
1215
evergreen_set_viewport_state(struct pipe_context * ctx,const struct pipe_viewport_state * state)1216 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1217 const struct pipe_viewport_state *state)
1218 {
1219 struct r600_context *rctx = (struct r600_context *)ctx;
1220 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1221
1222 if (rstate == NULL)
1223 return;
1224
1225 rctx->viewport = *state;
1226 rstate->id = R600_PIPE_STATE_VIEWPORT;
1227 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1228 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1229 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1230 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1231 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1232 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1233
1234 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1235 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1236 r600_context_pipe_state_set(rctx, rstate);
1237 }
1238
evergreen_init_color_surface(struct r600_context * rctx,struct r600_surface * surf)1239 void evergreen_init_color_surface(struct r600_context *rctx,
1240 struct r600_surface *surf)
1241 {
1242 struct r600_screen *rscreen = rctx->screen;
1243 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1244 struct pipe_resource *pipe_tex = surf->base.texture;
1245 unsigned level = surf->base.u.tex.level;
1246 unsigned pitch, slice;
1247 unsigned color_info, color_attrib, color_dim = 0;
1248 unsigned format, swap, ntype, endian;
1249 uint64_t offset, base_offset;
1250 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1251 const struct util_format_description *desc;
1252 int i;
1253 bool blend_clamp = 0, blend_bypass = 0;
1254
1255 if (rtex->is_depth && !rtex->is_flushing_texture) {
1256 r600_init_flushed_depth_texture(&rctx->context, pipe_tex, NULL);
1257 rtex = rtex->flushed_depth_texture;
1258 assert(rtex);
1259 }
1260
1261 offset = rtex->surface.level[level].offset;
1262 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1263 offset += rtex->surface.level[level].slice_size *
1264 surf->base.u.tex.first_layer;
1265 }
1266 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1267 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1268 if (slice) {
1269 slice = slice - 1;
1270 }
1271 color_info = 0;
1272 switch (rtex->surface.level[level].mode) {
1273 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1274 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1275 tile_type = 1;
1276 break;
1277 case RADEON_SURF_MODE_1D:
1278 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1279 tile_type = rtex->tile_type;
1280 break;
1281 case RADEON_SURF_MODE_2D:
1282 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1283 tile_type = rtex->tile_type;
1284 break;
1285 case RADEON_SURF_MODE_LINEAR:
1286 default:
1287 color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1288 tile_type = 1;
1289 break;
1290 }
1291 tile_split = rtex->surface.tile_split;
1292 macro_aspect = rtex->surface.mtilea;
1293 bankw = rtex->surface.bankw;
1294 bankh = rtex->surface.bankh;
1295 fmask_bankh = rtex->fmask_bank_height;
1296 tile_split = eg_tile_split(tile_split);
1297 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1298 bankw = eg_bank_wh(bankw);
1299 bankh = eg_bank_wh(bankh);
1300 fmask_bankh = eg_bank_wh(fmask_bankh);
1301
1302 /* 128 bit formats require tile type = 1 */
1303 if (rscreen->chip_class == CAYMAN) {
1304 if (util_format_get_blocksize(surf->base.format) >= 16)
1305 tile_type = 1;
1306 }
1307 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1308 desc = util_format_description(surf->base.format);
1309 for (i = 0; i < 4; i++) {
1310 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1311 break;
1312 }
1313 }
1314
1315 color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1316 S_028C74_NUM_BANKS(nbanks) |
1317 S_028C74_BANK_WIDTH(bankw) |
1318 S_028C74_BANK_HEIGHT(bankh) |
1319 S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1320 S_028C74_NON_DISP_TILING_ORDER(tile_type) |
1321 S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1322
1323 if (rctx->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1324 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1325 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1326 S_028C74_NUM_FRAGMENTS(log_samples);
1327 }
1328
1329 ntype = V_028C70_NUMBER_UNORM;
1330 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1331 ntype = V_028C70_NUMBER_SRGB;
1332 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1333 if (desc->channel[i].normalized)
1334 ntype = V_028C70_NUMBER_SNORM;
1335 else if (desc->channel[i].pure_integer)
1336 ntype = V_028C70_NUMBER_SINT;
1337 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1338 if (desc->channel[i].normalized)
1339 ntype = V_028C70_NUMBER_UNORM;
1340 else if (desc->channel[i].pure_integer)
1341 ntype = V_028C70_NUMBER_UINT;
1342 }
1343
1344 format = r600_translate_colorformat(surf->base.format);
1345 assert(format != ~0);
1346
1347 swap = r600_translate_colorswap(surf->base.format);
1348 assert(swap != ~0);
1349
1350 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1351 endian = ENDIAN_NONE;
1352 } else {
1353 endian = r600_colorformat_endian_swap(format);
1354 }
1355
1356 /* blend clamp should be set for all NORM/SRGB types */
1357 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1358 ntype == V_028C70_NUMBER_SRGB)
1359 blend_clamp = 1;
1360
1361 /* set blend bypass according to docs if SINT/UINT or
1362 8/24 COLOR variants */
1363 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1364 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1365 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1366 blend_clamp = 0;
1367 blend_bypass = 1;
1368 }
1369
1370 surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1371
1372 color_info |= S_028C70_FORMAT(format) |
1373 S_028C70_COMP_SWAP(swap) |
1374 S_028C70_BLEND_CLAMP(blend_clamp) |
1375 S_028C70_BLEND_BYPASS(blend_bypass) |
1376 S_028C70_NUMBER_TYPE(ntype) |
1377 S_028C70_ENDIAN(endian);
1378
1379 if (rtex->is_rat) {
1380 color_info |= S_028C70_RAT(1);
1381 color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0)
1382 | S_028C78_HEIGHT_MAX(pipe_tex->height0);
1383 }
1384
1385 /* EXPORT_NORM is an optimzation that can be enabled for better
1386 * performance in certain cases.
1387 * EXPORT_NORM can be enabled if:
1388 * - 11-bit or smaller UNORM/SNORM/SRGB
1389 * - 16-bit or smaller FLOAT
1390 */
1391 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1392 ((desc->channel[i].size < 12 &&
1393 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1394 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1395 (desc->channel[i].size < 17 &&
1396 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1397 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1398 surf->export_16bpc = true;
1399 }
1400
1401 if (rtex->fmask_size && rtex->cmask_size) {
1402 color_info |= S_028C70_COMPRESSION(1) | S_028C70_FAST_CLEAR(1);
1403 }
1404
1405 base_offset = r600_resource_va(rctx->context.screen, pipe_tex);
1406
1407 /* XXX handle enabling of CB beyond BASE8 which has different offset */
1408 surf->cb_color_base = (base_offset + offset) >> 8;
1409 surf->cb_color_dim = color_dim;
1410 surf->cb_color_info = color_info;
1411 surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1412 surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1413 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1414 surf->cb_color_view = 0;
1415 } else {
1416 surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1417 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1418 }
1419 surf->cb_color_attrib = color_attrib;
1420 if (rtex->fmask_size && rtex->cmask_size) {
1421 surf->cb_color_fmask = (base_offset + rtex->fmask_offset) >> 8;
1422 surf->cb_color_cmask = (base_offset + rtex->cmask_offset) >> 8;
1423 } else {
1424 surf->cb_color_fmask = surf->cb_color_base;
1425 surf->cb_color_cmask = surf->cb_color_base;
1426 }
1427 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1428 surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask_slice_tile_max);
1429
1430 surf->color_initialized = true;
1431 }
1432
evergreen_init_depth_surface(struct r600_context * rctx,struct r600_surface * surf)1433 static void evergreen_init_depth_surface(struct r600_context *rctx,
1434 struct r600_surface *surf)
1435 {
1436 struct r600_screen *rscreen = rctx->screen;
1437 struct pipe_screen *screen = &rscreen->screen;
1438 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1439 uint64_t offset;
1440 unsigned level, pitch, slice, format, array_mode;
1441 unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1442
1443 level = surf->base.u.tex.level;
1444 format = r600_translate_dbformat(surf->base.format);
1445 assert(format != ~0);
1446
1447 offset = r600_resource_va(screen, surf->base.texture);
1448 offset += rtex->surface.level[level].offset;
1449 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1450 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1451 if (slice) {
1452 slice = slice - 1;
1453 }
1454 switch (rtex->surface.level[level].mode) {
1455 case RADEON_SURF_MODE_2D:
1456 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1457 break;
1458 case RADEON_SURF_MODE_1D:
1459 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1460 case RADEON_SURF_MODE_LINEAR:
1461 default:
1462 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1463 break;
1464 }
1465 tile_split = rtex->surface.tile_split;
1466 macro_aspect = rtex->surface.mtilea;
1467 bankw = rtex->surface.bankw;
1468 bankh = rtex->surface.bankh;
1469 tile_split = eg_tile_split(tile_split);
1470 macro_aspect = eg_macro_tile_aspect(macro_aspect);
1471 bankw = eg_bank_wh(bankw);
1472 bankh = eg_bank_wh(bankh);
1473 nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1474 offset >>= 8;
1475
1476 surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1477 S_028040_FORMAT(format) |
1478 S_028040_TILE_SPLIT(tile_split)|
1479 S_028040_NUM_BANKS(nbanks) |
1480 S_028040_BANK_WIDTH(bankw) |
1481 S_028040_BANK_HEIGHT(bankh) |
1482 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1483 if (rscreen->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1484 surf->db_depth_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1485 }
1486 surf->db_depth_base = offset;
1487 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1488 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1489 surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1490 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1491
1492 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1493 uint64_t stencil_offset = rtex->surface.stencil_offset;
1494 unsigned i, stile_split = rtex->surface.stencil_tile_split;
1495
1496 stile_split = eg_tile_split(stile_split);
1497 stencil_offset += r600_resource_va(screen, surf->base.texture);
1498 stencil_offset += rtex->surface.level[level].offset / 4;
1499 stencil_offset >>= 8;
1500
1501 /* We're guessing the stencil offset from the depth offset.
1502 * Make sure each mipmap level has a unique offset. */
1503 for (i = 1; i <= level; i++) {
1504 /* If two levels have the same address, add 256
1505 * to the offset of the smaller level. */
1506 if ((rtex->surface.level[i-1].offset / 4) >> 8 ==
1507 (rtex->surface.level[i].offset / 4) >> 8) {
1508 stencil_offset++;
1509 }
1510 }
1511
1512 surf->db_stencil_base = stencil_offset;
1513 surf->db_stencil_info = 1 | S_028044_TILE_SPLIT(stile_split);
1514 } else {
1515 surf->db_stencil_base = offset;
1516 surf->db_stencil_info = 1;
1517 }
1518
1519 surf->depth_initialized = true;
1520 }
1521
1522 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1523 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1524 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1525 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1526 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1527
evergreen_set_ms_pos(struct pipe_context * ctx,struct r600_pipe_state * rstate,int nsample)1528 static uint32_t evergreen_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1529 {
1530 /* 2xMSAA
1531 * There are two locations (-4, 4), (4, -4). */
1532 static uint32_t sample_locs_2x[] = {
1533 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1534 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1535 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1536 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1537 };
1538 static unsigned max_dist_2x = 4;
1539 /* 4xMSAA
1540 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1541 static uint32_t sample_locs_4x[] = {
1542 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1543 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1544 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1545 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1546 };
1547 static unsigned max_dist_4x = 6;
1548 /* 8xMSAA */
1549 static uint32_t sample_locs_8x[] = {
1550 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1551 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1552 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1553 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1554 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1555 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1556 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1557 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1558 };
1559 static unsigned max_dist_8x = 8;
1560 struct r600_context *rctx = (struct r600_context *)ctx;
1561 unsigned i;
1562
1563 switch (nsample) {
1564 case 2:
1565 for (i = 0; i < Elements(sample_locs_2x); i++) {
1566 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
1567 sample_locs_2x[i]);
1568 }
1569 return max_dist_2x;
1570 case 4:
1571 for (i = 0; i < Elements(sample_locs_4x); i++) {
1572 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
1573 sample_locs_4x[i]);
1574 }
1575 return max_dist_4x;
1576 case 8:
1577 for (i = 0; i < Elements(sample_locs_8x); i++) {
1578 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
1579 sample_locs_8x[i]);
1580 }
1581 return max_dist_8x;
1582 default:
1583 R600_ERR("Invalid nr_samples %i\n", nsample);
1584 return 0;
1585 }
1586 }
1587
cayman_set_ms_pos(struct pipe_context * ctx,struct r600_pipe_state * rstate,int nsample)1588 static uint32_t cayman_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1589 {
1590 /* 2xMSAA
1591 * There are two locations (-4, 4), (4, -4). */
1592 static uint32_t sample_locs_2x[] = {
1593 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1594 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1595 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1596 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1597 };
1598 static unsigned max_dist_2x = 4;
1599 /* 4xMSAA
1600 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1601 static uint32_t sample_locs_4x[] = {
1602 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1603 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1604 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1605 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1606 };
1607 static unsigned max_dist_4x = 6;
1608 /* 8xMSAA */
1609 static uint32_t sample_locs_8x[] = {
1610 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1611 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1612 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1613 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1614 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1615 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1616 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1617 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1618 };
1619 static unsigned max_dist_8x = 8;
1620 /* 16xMSAA */
1621 static uint32_t sample_locs_16x[] = {
1622 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1623 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1624 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1625 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1626 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1627 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1628 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1629 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1630 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1631 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1632 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1633 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1634 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1635 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1636 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1637 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1638 };
1639 static unsigned max_dist_16x = 8;
1640 struct r600_context *rctx = (struct r600_context *)ctx;
1641 uint32_t max_dist, num_regs, *sample_locs;
1642
1643 switch (nsample) {
1644 case 2:
1645 sample_locs = sample_locs_2x;
1646 num_regs = Elements(sample_locs_2x);
1647 max_dist = max_dist_2x;
1648 break;
1649 case 4:
1650 sample_locs = sample_locs_4x;
1651 num_regs = Elements(sample_locs_4x);
1652 max_dist = max_dist_4x;
1653 break;
1654 case 8:
1655 sample_locs = sample_locs_8x;
1656 num_regs = Elements(sample_locs_8x);
1657 max_dist = max_dist_8x;
1658 break;
1659 case 16:
1660 sample_locs = sample_locs_16x;
1661 num_regs = Elements(sample_locs_16x);
1662 max_dist = max_dist_16x;
1663 break;
1664 default:
1665 R600_ERR("Invalid nr_samples %i\n", nsample);
1666 return 0;
1667 }
1668
1669 r600_pipe_state_add_reg(rstate, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs[0]);
1670 r600_pipe_state_add_reg(rstate, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs[1]);
1671 r600_pipe_state_add_reg(rstate, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs[2]);
1672 r600_pipe_state_add_reg(rstate, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs[3]);
1673 if (num_regs <= 8) {
1674 r600_pipe_state_add_reg(rstate, CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs[4]);
1675 r600_pipe_state_add_reg(rstate, CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs[5]);
1676 r600_pipe_state_add_reg(rstate, CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs[6]);
1677 r600_pipe_state_add_reg(rstate, CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs[7]);
1678 }
1679 if (num_regs <= 16) {
1680 r600_pipe_state_add_reg(rstate, CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, sample_locs[8]);
1681 r600_pipe_state_add_reg(rstate, CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, sample_locs[9]);
1682 r600_pipe_state_add_reg(rstate, CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, sample_locs[10]);
1683 r600_pipe_state_add_reg(rstate, CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, sample_locs[11]);
1684 r600_pipe_state_add_reg(rstate, CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, sample_locs[12]);
1685 r600_pipe_state_add_reg(rstate, CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, sample_locs[13]);
1686 r600_pipe_state_add_reg(rstate, CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, sample_locs[14]);
1687 r600_pipe_state_add_reg(rstate, CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, sample_locs[15]);
1688 }
1689 return max_dist;
1690 }
1691
evergreen_set_framebuffer_state(struct pipe_context * ctx,const struct pipe_framebuffer_state * state)1692 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1693 const struct pipe_framebuffer_state *state)
1694 {
1695 struct r600_context *rctx = (struct r600_context *)ctx;
1696 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1697 struct r600_surface *surf;
1698 struct r600_resource *res;
1699 struct r600_texture *rtex;
1700 uint32_t tl, br, i, nr_samples, log_samples;
1701
1702 if (rstate == NULL)
1703 return;
1704
1705 r600_flush_framebuffer(rctx, false);
1706
1707 /* unreference old buffer and reference new one */
1708 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1709
1710 util_copy_framebuffer_state(&rctx->framebuffer, state);
1711
1712 /* Colorbuffers. */
1713 rctx->export_16bpc = true;
1714 rctx->nr_cbufs = state->nr_cbufs;
1715 rctx->cb0_is_integer = state->nr_cbufs &&
1716 util_format_is_pure_integer(state->cbufs[0]->format);
1717 rctx->compressed_cb_mask = 0;
1718
1719 for (i = 0; i < state->nr_cbufs; i++) {
1720 surf = (struct r600_surface*)state->cbufs[i];
1721 res = (struct r600_resource*)surf->base.texture;
1722 rtex = (struct r600_texture*)res;
1723
1724 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1725
1726 if (!surf->color_initialized) {
1727 evergreen_init_color_surface(rctx, surf);
1728 }
1729
1730 if (!surf->export_16bpc) {
1731 rctx->export_16bpc = false;
1732 }
1733
1734 r600_pipe_state_add_reg_bo(rstate, R_028C60_CB_COLOR0_BASE + i * 0x3C,
1735 surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1736 r600_pipe_state_add_reg(rstate, R_028C78_CB_COLOR0_DIM + i * 0x3C,
1737 surf->cb_color_dim);
1738 r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1739 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1740 r600_pipe_state_add_reg(rstate, R_028C64_CB_COLOR0_PITCH + i * 0x3C,
1741 surf->cb_color_pitch);
1742 r600_pipe_state_add_reg(rstate, R_028C68_CB_COLOR0_SLICE + i * 0x3C,
1743 surf->cb_color_slice);
1744 r600_pipe_state_add_reg(rstate, R_028C6C_CB_COLOR0_VIEW + i * 0x3C,
1745 surf->cb_color_view);
1746 r600_pipe_state_add_reg_bo(rstate, R_028C74_CB_COLOR0_ATTRIB + i * 0x3C,
1747 surf->cb_color_attrib, res, RADEON_USAGE_READWRITE);
1748 r600_pipe_state_add_reg_bo(rstate, R_028C7C_CB_COLOR0_CMASK + i * 0x3c,
1749 surf->cb_color_cmask, res, RADEON_USAGE_READWRITE);
1750 r600_pipe_state_add_reg(rstate, R_028C80_CB_COLOR0_CMASK_SLICE + i * 0x3c,
1751 surf->cb_color_cmask_slice);
1752 r600_pipe_state_add_reg_bo(rstate, R_028C84_CB_COLOR0_FMASK + i * 0x3c,
1753 surf->cb_color_fmask, res, RADEON_USAGE_READWRITE);
1754 r600_pipe_state_add_reg(rstate, R_028C88_CB_COLOR0_FMASK_SLICE + i * 0x3c,
1755 surf->cb_color_fmask_slice);
1756
1757 /* Cayman can fetch from a compressed MSAA colorbuffer,
1758 * so it's pointless to track them. */
1759 if (rctx->chip_class != CAYMAN && rtex->fmask_size && rtex->cmask_size) {
1760 rctx->compressed_cb_mask |= 1 << i;
1761 }
1762 }
1763 /* set CB_COLOR1_INFO for possible dual-src blending */
1764 if (i == 1 && !((struct r600_texture*)res)->is_rat) {
1765 r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1766 surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1767 i++;
1768 }
1769 for (; i < 8 ; i++) {
1770 r600_pipe_state_add_reg(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1771 }
1772
1773 /* Update alpha-test state dependencies.
1774 * Alpha-test is done on the first colorbuffer only. */
1775 if (state->nr_cbufs) {
1776 surf = (struct r600_surface*)state->cbufs[0];
1777 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1778 rctx->alphatest_state.bypass = surf->alphatest_bypass;
1779 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1780 }
1781 if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
1782 rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
1783 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1784 }
1785 }
1786
1787 /* ZS buffer. */
1788 if (state->zsbuf) {
1789 surf = (struct r600_surface*)state->zsbuf;
1790 res = (struct r600_resource*)surf->base.texture;
1791
1792 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1793
1794 if (!surf->depth_initialized) {
1795 evergreen_init_depth_surface(rctx, surf);
1796 }
1797
1798 r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE, surf->db_depth_base,
1799 res, RADEON_USAGE_READWRITE);
1800 r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE, surf->db_depth_base,
1801 res, RADEON_USAGE_READWRITE);
1802 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, surf->db_depth_view);
1803
1804 r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE, surf->db_stencil_base,
1805 res, RADEON_USAGE_READWRITE);
1806 r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE, surf->db_stencil_base,
1807 res, RADEON_USAGE_READWRITE);
1808 r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO, surf->db_stencil_info,
1809 res, RADEON_USAGE_READWRITE);
1810
1811 r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, surf->db_depth_info,
1812 res, RADEON_USAGE_READWRITE);
1813 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE, surf->db_depth_size);
1814 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE, surf->db_depth_slice);
1815 }
1816
1817 /* Framebuffer dimensions. */
1818 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1819
1820 r600_pipe_state_add_reg(rstate,
1821 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1822 r600_pipe_state_add_reg(rstate,
1823 R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1824
1825 /* Multisampling */
1826 if (state->nr_cbufs)
1827 nr_samples = state->cbufs[0]->texture->nr_samples;
1828 else if (state->zsbuf)
1829 nr_samples = state->zsbuf->texture->nr_samples;
1830 else
1831 nr_samples = 0;
1832
1833 if (nr_samples > 1) {
1834 unsigned line_cntl = S_028C00_LAST_PIXEL(1) |
1835 S_028C00_EXPAND_LINE_WIDTH(1);
1836 log_samples = util_logbase2(nr_samples);
1837
1838 if (rctx->chip_class == CAYMAN) {
1839 unsigned max_dist = cayman_set_ms_pos(ctx, rstate, nr_samples);
1840
1841 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, line_cntl);
1842 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1843 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1844 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
1845 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
1846 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA,
1847 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1848 S_028804_PS_ITER_SAMPLES(log_samples) |
1849 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1850 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
1851 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1852 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1853 } else {
1854 unsigned max_dist = evergreen_set_ms_pos(ctx, rstate, nr_samples);
1855
1856 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, line_cntl);
1857 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1858 S_028C04_MSAA_NUM_SAMPLES(log_samples) |
1859 S_028C04_MAX_SAMPLE_DIST(max_dist));
1860 }
1861 } else {
1862 log_samples = 0;
1863
1864 if (rctx->chip_class == CAYMAN) {
1865 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1866 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG, 0);
1867 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA,
1868 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1869 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1870
1871 } else {
1872 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1873 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0);
1874 }
1875 }
1876
1877 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1878 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1879 r600_context_pipe_state_set(rctx, rstate);
1880
1881 if (state->zsbuf) {
1882 evergreen_polygon_offset_update(rctx);
1883 }
1884
1885 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1886 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1887 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1888 }
1889
1890 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1891 rctx->alphatest_state.bypass = false;
1892 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1893 }
1894
1895 if (rctx->chip_class == CAYMAN && rctx->db_misc_state.log_samples != log_samples) {
1896 rctx->db_misc_state.log_samples = log_samples;
1897 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1898 }
1899 }
1900
evergreen_emit_cb_misc_state(struct r600_context * rctx,struct r600_atom * atom)1901 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1902 {
1903 struct radeon_winsys_cs *cs = rctx->cs;
1904 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1905 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1906 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1907
1908 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1909 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1910 /* Always enable the first colorbuffer in CB_SHADER_MASK. This
1911 * will assure that the alpha-test will work even if there is
1912 * no colorbuffer bound. */
1913 r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1914 }
1915
evergreen_emit_db_misc_state(struct r600_context * rctx,struct r600_atom * atom)1916 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1917 {
1918 struct radeon_winsys_cs *cs = rctx->cs;
1919 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1920 unsigned db_render_control = 0;
1921 unsigned db_count_control = 0;
1922 unsigned db_render_override =
1923 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1924 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1925 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1926
1927 if (a->occlusion_query_enabled) {
1928 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1929 if (rctx->chip_class == CAYMAN) {
1930 db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1931 }
1932 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1933 }
1934
1935 if (a->flush_depthstencil_through_cb) {
1936 assert(a->copy_depth || a->copy_stencil);
1937
1938 db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1939 S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1940 S_028000_COPY_CENTROID(1) |
1941 S_028000_COPY_SAMPLE(a->copy_sample);
1942 }
1943
1944 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1945 r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1946 r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1947 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1948 }
1949
evergreen_emit_vertex_buffers(struct r600_context * rctx,struct r600_vertexbuf_state * state,unsigned resource_offset,unsigned pkt_flags)1950 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1951 struct r600_vertexbuf_state *state,
1952 unsigned resource_offset,
1953 unsigned pkt_flags)
1954 {
1955 struct radeon_winsys_cs *cs = rctx->cs;
1956 uint32_t dirty_mask = state->dirty_mask;
1957
1958 while (dirty_mask) {
1959 struct pipe_vertex_buffer *vb;
1960 struct r600_resource *rbuffer;
1961 uint64_t va;
1962 unsigned buffer_index = u_bit_scan(&dirty_mask);
1963
1964 vb = &state->vb[buffer_index];
1965 rbuffer = (struct r600_resource*)vb->buffer;
1966 assert(rbuffer);
1967
1968 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1969 va += vb->buffer_offset;
1970
1971 /* fetch resources start at index 992 */
1972 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1973 r600_write_value(cs, (resource_offset + buffer_index) * 8);
1974 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1975 r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1976 r600_write_value(cs, /* RESOURCEi_WORD2 */
1977 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1978 S_030008_STRIDE(vb->stride) |
1979 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1980 r600_write_value(cs, /* RESOURCEi_WORD3 */
1981 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1982 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1983 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1984 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1985 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1986 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1987 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1988 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1989
1990 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1991 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1992 }
1993 state->dirty_mask = 0;
1994 }
1995
evergreen_fs_emit_vertex_buffers(struct r600_context * rctx,struct r600_atom * atom)1996 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1997 {
1998 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
1999 }
2000
evergreen_cs_emit_vertex_buffers(struct r600_context * rctx,struct r600_atom * atom)2001 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2002 {
2003 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
2004 RADEON_CP_PACKET3_COMPUTE_MODE);
2005 }
2006
evergreen_emit_constant_buffers(struct r600_context * rctx,struct r600_constbuf_state * state,unsigned buffer_id_base,unsigned reg_alu_constbuf_size,unsigned reg_alu_const_cache)2007 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2008 struct r600_constbuf_state *state,
2009 unsigned buffer_id_base,
2010 unsigned reg_alu_constbuf_size,
2011 unsigned reg_alu_const_cache)
2012 {
2013 struct radeon_winsys_cs *cs = rctx->cs;
2014 uint32_t dirty_mask = state->dirty_mask;
2015
2016 while (dirty_mask) {
2017 struct pipe_constant_buffer *cb;
2018 struct r600_resource *rbuffer;
2019 uint64_t va;
2020 unsigned buffer_index = ffs(dirty_mask) - 1;
2021
2022 cb = &state->cb[buffer_index];
2023 rbuffer = (struct r600_resource*)cb->buffer;
2024 assert(rbuffer);
2025
2026 va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
2027 va += cb->buffer_offset;
2028
2029 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2030 ALIGN_DIVUP(cb->buffer_size >> 4, 16));
2031 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
2032
2033 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2034 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2035
2036 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2037 r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
2038 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
2039 r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2040 r600_write_value(cs, /* RESOURCEi_WORD2 */
2041 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2042 S_030008_STRIDE(16) |
2043 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2044 r600_write_value(cs, /* RESOURCEi_WORD3 */
2045 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2046 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2047 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2048 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2049 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2050 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2051 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
2052 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2053
2054 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2055 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2056
2057 dirty_mask &= ~(1 << buffer_index);
2058 }
2059 state->dirty_mask = 0;
2060 }
2061
evergreen_emit_vs_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)2062 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2063 {
2064 evergreen_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 176,
2065 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2066 R_028980_ALU_CONST_CACHE_VS_0);
2067 }
2068
evergreen_emit_ps_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)2069 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2070 {
2071 evergreen_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
2072 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2073 R_028940_ALU_CONST_CACHE_PS_0);
2074 }
2075
evergreen_emit_sampler_views(struct r600_context * rctx,struct r600_samplerview_state * state,unsigned resource_id_base)2076 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2077 struct r600_samplerview_state *state,
2078 unsigned resource_id_base)
2079 {
2080 struct radeon_winsys_cs *cs = rctx->cs;
2081 uint32_t dirty_mask = state->dirty_mask;
2082
2083 while (dirty_mask) {
2084 struct r600_pipe_sampler_view *rview;
2085 unsigned resource_index = u_bit_scan(&dirty_mask);
2086 unsigned reloc;
2087
2088 rview = state->views[resource_index];
2089 assert(rview);
2090
2091 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2092 r600_write_value(cs, (resource_id_base + resource_index) * 8);
2093 r600_write_array(cs, 8, rview->tex_resource_words);
2094
2095 /* XXX The kernel needs two relocations. This is stupid. */
2096 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
2097 RADEON_USAGE_READ);
2098 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2099 r600_write_value(cs, reloc);
2100 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2101 r600_write_value(cs, reloc);
2102 }
2103 state->dirty_mask = 0;
2104 }
2105
evergreen_emit_vs_sampler_views(struct r600_context * rctx,struct r600_atom * atom)2106 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2107 {
2108 evergreen_emit_sampler_views(rctx, &rctx->vs_samplers.views, 176 + R600_MAX_CONST_BUFFERS);
2109 }
2110
evergreen_emit_ps_sampler_views(struct r600_context * rctx,struct r600_atom * atom)2111 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2112 {
2113 evergreen_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
2114 }
2115
evergreen_emit_sampler(struct r600_context * rctx,struct r600_textures_info * texinfo,unsigned resource_id_base,unsigned border_index_reg)2116 static void evergreen_emit_sampler(struct r600_context *rctx,
2117 struct r600_textures_info *texinfo,
2118 unsigned resource_id_base,
2119 unsigned border_index_reg)
2120 {
2121 struct radeon_winsys_cs *cs = rctx->cs;
2122 unsigned i;
2123
2124 for (i = 0; i < texinfo->n_samplers; i++) {
2125
2126 if (texinfo->samplers[i] == NULL) {
2127 continue;
2128 }
2129 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2130 r600_write_value(cs, (resource_id_base + i) * 3);
2131 r600_write_array(cs, 3, texinfo->samplers[i]->tex_sampler_words);
2132
2133 if (texinfo->samplers[i]->border_color_use) {
2134 r600_write_config_reg_seq(cs, border_index_reg, 5);
2135 r600_write_value(cs, i);
2136 r600_write_array(cs, 4, texinfo->samplers[i]->border_color);
2137 }
2138 }
2139 }
2140
evergreen_emit_vs_sampler(struct r600_context * rctx,struct r600_atom * atom)2141 static void evergreen_emit_vs_sampler(struct r600_context *rctx, struct r600_atom *atom)
2142 {
2143 evergreen_emit_sampler(rctx, &rctx->vs_samplers, 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
2144 }
2145
evergreen_emit_ps_sampler(struct r600_context * rctx,struct r600_atom * atom)2146 static void evergreen_emit_ps_sampler(struct r600_context *rctx, struct r600_atom *atom)
2147 {
2148 evergreen_emit_sampler(rctx, &rctx->ps_samplers, 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
2149 }
2150
evergreen_emit_sample_mask(struct r600_context * rctx,struct r600_atom * a)2151 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2152 {
2153 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2154 uint8_t mask = s->sample_mask;
2155
2156 r600_write_context_reg(rctx->cs, R_028C3C_PA_SC_AA_MASK,
2157 mask | (mask << 8) | (mask << 16) | (mask << 24));
2158 }
2159
cayman_emit_sample_mask(struct r600_context * rctx,struct r600_atom * a)2160 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2161 {
2162 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2163 struct radeon_winsys_cs *cs = rctx->cs;
2164 uint16_t mask = s->sample_mask;
2165
2166 r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2167 r600_write_value(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2168 r600_write_value(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2169 }
2170
evergreen_init_state_functions(struct r600_context * rctx)2171 void evergreen_init_state_functions(struct r600_context *rctx)
2172 {
2173 r600_init_atom(&rctx->cb_misc_state.atom, evergreen_emit_cb_misc_state, 0, 0);
2174 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
2175 r600_init_atom(&rctx->db_misc_state.atom, evergreen_emit_db_misc_state, 7, 0);
2176 r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
2177 r600_init_atom(&rctx->vertex_buffer_state.atom, evergreen_fs_emit_vertex_buffers, 0, 0);
2178 r600_init_atom(&rctx->cs_vertex_buffer_state.atom, evergreen_cs_emit_vertex_buffers, 0, 0);
2179 r600_init_atom(&rctx->vs_constbuf_state.atom, evergreen_emit_vs_constant_buffers, 0, 0);
2180 r600_init_atom(&rctx->ps_constbuf_state.atom, evergreen_emit_ps_constant_buffers, 0, 0);
2181 r600_init_atom(&rctx->vs_samplers.views.atom, evergreen_emit_vs_sampler_views, 0, 0);
2182 r600_init_atom(&rctx->ps_samplers.views.atom, evergreen_emit_ps_sampler_views, 0, 0);
2183 r600_init_atom(&rctx->cs_shader_state.atom, evergreen_emit_cs_shader, 0, 0);
2184 r600_init_atom(&rctx->vs_samplers.atom_sampler, evergreen_emit_vs_sampler, 0, 0);
2185 r600_init_atom(&rctx->ps_samplers.atom_sampler, evergreen_emit_ps_sampler, 0, 0);
2186
2187 if (rctx->chip_class == EVERGREEN)
2188 r600_init_atom(&rctx->sample_mask.atom, evergreen_emit_sample_mask, 3, 0);
2189 else
2190 r600_init_atom(&rctx->sample_mask.atom, cayman_emit_sample_mask, 4, 0);
2191 rctx->sample_mask.sample_mask = ~0;
2192 r600_atom_dirty(rctx, &rctx->sample_mask.atom);
2193
2194 rctx->context.create_blend_state = evergreen_create_blend_state;
2195 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
2196 rctx->context.create_fs_state = r600_create_shader_state_ps;
2197 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
2198 rctx->context.create_sampler_state = evergreen_create_sampler_state;
2199 rctx->context.create_sampler_view = evergreen_create_sampler_view;
2200 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
2201 rctx->context.create_vs_state = r600_create_shader_state_vs;
2202 rctx->context.bind_blend_state = r600_bind_blend_state;
2203 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2204 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
2205 rctx->context.bind_fs_state = r600_bind_ps_shader;
2206 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
2207 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
2208 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
2209 rctx->context.bind_vs_state = r600_bind_vs_shader;
2210 rctx->context.delete_blend_state = r600_delete_state;
2211 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
2212 rctx->context.delete_fs_state = r600_delete_ps_shader;
2213 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
2214 rctx->context.delete_sampler_state = r600_delete_sampler;
2215 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
2216 rctx->context.delete_vs_state = r600_delete_vs_shader;
2217 rctx->context.set_blend_color = r600_set_blend_color;
2218 rctx->context.set_clip_state = evergreen_set_clip_state;
2219 rctx->context.set_constant_buffer = r600_set_constant_buffer;
2220 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_views;
2221 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
2222 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
2223 rctx->context.set_sample_mask = r600_set_sample_mask;
2224 rctx->context.set_scissor_state = evergreen_set_scissor_state;
2225 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
2226 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
2227 rctx->context.set_index_buffer = r600_set_index_buffer;
2228 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_views;
2229 rctx->context.set_viewport_state = evergreen_set_viewport_state;
2230 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
2231 rctx->context.texture_barrier = r600_texture_barrier;
2232 rctx->context.create_stream_output_target = r600_create_so_target;
2233 rctx->context.stream_output_target_destroy = r600_so_target_destroy;
2234 rctx->context.set_stream_output_targets = r600_set_so_targets;
2235 evergreen_init_compute_state_functions(rctx);
2236 }
2237
cayman_init_atom_start_cs(struct r600_context * rctx)2238 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2239 {
2240 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2241
2242 r600_init_command_buffer(cb, 256, EMIT_EARLY);
2243
2244 /* This must be first. */
2245 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2246 r600_store_value(cb, 0x80000000);
2247 r600_store_value(cb, 0x80000000);
2248
2249 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2250 r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2251 /* always set the temp clauses */
2252 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2253
2254 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2255 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2256 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2257
2258 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2259
2260 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2261
2262 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2263 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2264 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2265 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2266 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2267 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2268 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2269 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2270 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2271 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2272 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2273 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2274 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2275 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2276
2277 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2278 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2279 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2280
2281 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2282 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2283 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2284
2285 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2286
2287 r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2288
2289 r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2290 r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2291 r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2292
2293 r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
2294 r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2295 r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2296
2297 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2298 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2299 r600_store_value(cb, 0);
2300 r600_store_value(cb, 0);
2301 r600_store_value(cb, 0);
2302 r600_store_value(cb, 0);
2303 r600_store_value(cb, 0);
2304 r600_store_value(cb, 0);
2305 r600_store_value(cb, 0);
2306 r600_store_value(cb, 0);
2307 r600_store_value(cb, 0);
2308 r600_store_value(cb, 0);
2309 r600_store_value(cb, 0);
2310 r600_store_value(cb, 0);
2311 r600_store_value(cb, 0);
2312 r600_store_value(cb, 0);
2313 r600_store_value(cb, 0);
2314 r600_store_value(cb, 0);
2315 r600_store_value(cb, 0);
2316 r600_store_value(cb, 0);
2317 r600_store_value(cb, 0);
2318 r600_store_value(cb, 0);
2319 r600_store_value(cb, 0);
2320 r600_store_value(cb, 0);
2321 r600_store_value(cb, 0);
2322 r600_store_value(cb, 0);
2323 r600_store_value(cb, 0);
2324 r600_store_value(cb, 0);
2325 r600_store_value(cb, 0);
2326 r600_store_value(cb, 0);
2327 r600_store_value(cb, 0);
2328 r600_store_value(cb, 0);
2329 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2330 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2331 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2332
2333 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2334
2335 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2336 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2337 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2338
2339 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2340
2341 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2342 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2343 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2344 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2345
2346 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2347 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2348
2349 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2350 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2351 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2352
2353 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2354 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2355 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2356
2357 r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2358 r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2359 r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2360 r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2361 r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2362
2363 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2364 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2365 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2366
2367 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2368 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2369 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2370
2371 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2372 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2373 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2374
2375 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2376 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2377 if (rctx->screen->has_streamout) {
2378 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2379 }
2380
2381 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2382 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2383 }
2384
evergreen_init_common_regs(struct r600_command_buffer * cb,enum chip_class ctx_chip_class,enum radeon_family ctx_family,int ctx_drm_minor)2385 void evergreen_init_common_regs(struct r600_command_buffer *cb,
2386 enum chip_class ctx_chip_class,
2387 enum radeon_family ctx_family,
2388 int ctx_drm_minor)
2389 {
2390 int ps_prio;
2391 int vs_prio;
2392 int gs_prio;
2393 int es_prio;
2394
2395 int hs_prio;
2396 int cs_prio;
2397 int ls_prio;
2398
2399 int num_ps_gprs;
2400 int num_vs_gprs;
2401 int num_gs_gprs;
2402 int num_es_gprs;
2403 int num_hs_gprs;
2404 int num_ls_gprs;
2405 int num_temp_gprs;
2406
2407 unsigned tmp;
2408
2409 ps_prio = 0;
2410 vs_prio = 1;
2411 gs_prio = 2;
2412 es_prio = 3;
2413 hs_prio = 0;
2414 ls_prio = 0;
2415 cs_prio = 0;
2416
2417 switch (ctx_family) {
2418 case CHIP_CEDAR:
2419 default:
2420 num_ps_gprs = 93;
2421 num_vs_gprs = 46;
2422 num_temp_gprs = 4;
2423 num_gs_gprs = 31;
2424 num_es_gprs = 31;
2425 num_hs_gprs = 23;
2426 num_ls_gprs = 23;
2427 break;
2428 case CHIP_REDWOOD:
2429 num_ps_gprs = 93;
2430 num_vs_gprs = 46;
2431 num_temp_gprs = 4;
2432 num_gs_gprs = 31;
2433 num_es_gprs = 31;
2434 num_hs_gprs = 23;
2435 num_ls_gprs = 23;
2436 break;
2437 case CHIP_JUNIPER:
2438 num_ps_gprs = 93;
2439 num_vs_gprs = 46;
2440 num_temp_gprs = 4;
2441 num_gs_gprs = 31;
2442 num_es_gprs = 31;
2443 num_hs_gprs = 23;
2444 num_ls_gprs = 23;
2445 break;
2446 case CHIP_CYPRESS:
2447 case CHIP_HEMLOCK:
2448 num_ps_gprs = 93;
2449 num_vs_gprs = 46;
2450 num_temp_gprs = 4;
2451 num_gs_gprs = 31;
2452 num_es_gprs = 31;
2453 num_hs_gprs = 23;
2454 num_ls_gprs = 23;
2455 break;
2456 case CHIP_PALM:
2457 num_ps_gprs = 93;
2458 num_vs_gprs = 46;
2459 num_temp_gprs = 4;
2460 num_gs_gprs = 31;
2461 num_es_gprs = 31;
2462 num_hs_gprs = 23;
2463 num_ls_gprs = 23;
2464 break;
2465 case CHIP_SUMO:
2466 num_ps_gprs = 93;
2467 num_vs_gprs = 46;
2468 num_temp_gprs = 4;
2469 num_gs_gprs = 31;
2470 num_es_gprs = 31;
2471 num_hs_gprs = 23;
2472 num_ls_gprs = 23;
2473 break;
2474 case CHIP_SUMO2:
2475 num_ps_gprs = 93;
2476 num_vs_gprs = 46;
2477 num_temp_gprs = 4;
2478 num_gs_gprs = 31;
2479 num_es_gprs = 31;
2480 num_hs_gprs = 23;
2481 num_ls_gprs = 23;
2482 break;
2483 case CHIP_BARTS:
2484 num_ps_gprs = 93;
2485 num_vs_gprs = 46;
2486 num_temp_gprs = 4;
2487 num_gs_gprs = 31;
2488 num_es_gprs = 31;
2489 num_hs_gprs = 23;
2490 num_ls_gprs = 23;
2491 break;
2492 case CHIP_TURKS:
2493 num_ps_gprs = 93;
2494 num_vs_gprs = 46;
2495 num_temp_gprs = 4;
2496 num_gs_gprs = 31;
2497 num_es_gprs = 31;
2498 num_hs_gprs = 23;
2499 num_ls_gprs = 23;
2500 break;
2501 case CHIP_CAICOS:
2502 num_ps_gprs = 93;
2503 num_vs_gprs = 46;
2504 num_temp_gprs = 4;
2505 num_gs_gprs = 31;
2506 num_es_gprs = 31;
2507 num_hs_gprs = 23;
2508 num_ls_gprs = 23;
2509 break;
2510 }
2511
2512 tmp = 0;
2513 switch (ctx_family) {
2514 case CHIP_CEDAR:
2515 case CHIP_PALM:
2516 case CHIP_SUMO:
2517 case CHIP_SUMO2:
2518 case CHIP_CAICOS:
2519 break;
2520 default:
2521 tmp |= S_008C00_VC_ENABLE(1);
2522 break;
2523 }
2524 tmp |= S_008C00_EXPORT_SRC_C(1);
2525 tmp |= S_008C00_CS_PRIO(cs_prio);
2526 tmp |= S_008C00_LS_PRIO(ls_prio);
2527 tmp |= S_008C00_HS_PRIO(hs_prio);
2528 tmp |= S_008C00_PS_PRIO(ps_prio);
2529 tmp |= S_008C00_VS_PRIO(vs_prio);
2530 tmp |= S_008C00_GS_PRIO(gs_prio);
2531 tmp |= S_008C00_ES_PRIO(es_prio);
2532
2533 /* enable dynamic GPR resource management */
2534 if (ctx_drm_minor >= 7) {
2535 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2536 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2537 /* always set temp clauses */
2538 r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2539 r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2540 r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2541 r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2542 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2543 r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2544 S_028838_PS_GPRS(0x1e) |
2545 S_028838_VS_GPRS(0x1e) |
2546 S_028838_GS_GPRS(0x1e) |
2547 S_028838_ES_GPRS(0x1e) |
2548 S_028838_HS_GPRS(0x1e) |
2549 S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2550 } else {
2551 r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2552 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2553
2554 tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2555 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2556 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2557 r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2558
2559 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2560 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2561 r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2562
2563 tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2564 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2565 r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2566 }
2567
2568 r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2569 S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2570
2571 r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2572
2573 r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2574 r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2575 r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2576
2577 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2578
2579 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2580 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2581 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2582
2583 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2584 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2585 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2586 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2587
2588 r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2589 r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2590
2591 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2592
2593 return;
2594 }
2595
evergreen_init_atom_start_cs(struct r600_context * rctx)2596 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2597 {
2598 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2599 int num_ps_threads;
2600 int num_vs_threads;
2601 int num_gs_threads;
2602 int num_es_threads;
2603 int num_hs_threads;
2604 int num_ls_threads;
2605
2606 int num_ps_stack_entries;
2607 int num_vs_stack_entries;
2608 int num_gs_stack_entries;
2609 int num_es_stack_entries;
2610 int num_hs_stack_entries;
2611 int num_ls_stack_entries;
2612 enum radeon_family family;
2613 unsigned tmp;
2614
2615 if (rctx->chip_class == CAYMAN) {
2616 cayman_init_atom_start_cs(rctx);
2617 return;
2618 }
2619
2620 r600_init_command_buffer(cb, 256, EMIT_EARLY);
2621
2622 /* This must be first. */
2623 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2624 r600_store_value(cb, 0x80000000);
2625 r600_store_value(cb, 0x80000000);
2626
2627 evergreen_init_common_regs(cb, rctx->chip_class
2628 , rctx->family, rctx->screen->info.drm_minor);
2629
2630 family = rctx->family;
2631 switch (family) {
2632 case CHIP_CEDAR:
2633 default:
2634 num_ps_threads = 96;
2635 num_vs_threads = 16;
2636 num_gs_threads = 16;
2637 num_es_threads = 16;
2638 num_hs_threads = 16;
2639 num_ls_threads = 16;
2640 num_ps_stack_entries = 42;
2641 num_vs_stack_entries = 42;
2642 num_gs_stack_entries = 42;
2643 num_es_stack_entries = 42;
2644 num_hs_stack_entries = 42;
2645 num_ls_stack_entries = 42;
2646 break;
2647 case CHIP_REDWOOD:
2648 num_ps_threads = 128;
2649 num_vs_threads = 20;
2650 num_gs_threads = 20;
2651 num_es_threads = 20;
2652 num_hs_threads = 20;
2653 num_ls_threads = 20;
2654 num_ps_stack_entries = 42;
2655 num_vs_stack_entries = 42;
2656 num_gs_stack_entries = 42;
2657 num_es_stack_entries = 42;
2658 num_hs_stack_entries = 42;
2659 num_ls_stack_entries = 42;
2660 break;
2661 case CHIP_JUNIPER:
2662 num_ps_threads = 128;
2663 num_vs_threads = 20;
2664 num_gs_threads = 20;
2665 num_es_threads = 20;
2666 num_hs_threads = 20;
2667 num_ls_threads = 20;
2668 num_ps_stack_entries = 85;
2669 num_vs_stack_entries = 85;
2670 num_gs_stack_entries = 85;
2671 num_es_stack_entries = 85;
2672 num_hs_stack_entries = 85;
2673 num_ls_stack_entries = 85;
2674 break;
2675 case CHIP_CYPRESS:
2676 case CHIP_HEMLOCK:
2677 num_ps_threads = 128;
2678 num_vs_threads = 20;
2679 num_gs_threads = 20;
2680 num_es_threads = 20;
2681 num_hs_threads = 20;
2682 num_ls_threads = 20;
2683 num_ps_stack_entries = 85;
2684 num_vs_stack_entries = 85;
2685 num_gs_stack_entries = 85;
2686 num_es_stack_entries = 85;
2687 num_hs_stack_entries = 85;
2688 num_ls_stack_entries = 85;
2689 break;
2690 case CHIP_PALM:
2691 num_ps_threads = 96;
2692 num_vs_threads = 16;
2693 num_gs_threads = 16;
2694 num_es_threads = 16;
2695 num_hs_threads = 16;
2696 num_ls_threads = 16;
2697 num_ps_stack_entries = 42;
2698 num_vs_stack_entries = 42;
2699 num_gs_stack_entries = 42;
2700 num_es_stack_entries = 42;
2701 num_hs_stack_entries = 42;
2702 num_ls_stack_entries = 42;
2703 break;
2704 case CHIP_SUMO:
2705 num_ps_threads = 96;
2706 num_vs_threads = 25;
2707 num_gs_threads = 25;
2708 num_es_threads = 25;
2709 num_hs_threads = 25;
2710 num_ls_threads = 25;
2711 num_ps_stack_entries = 42;
2712 num_vs_stack_entries = 42;
2713 num_gs_stack_entries = 42;
2714 num_es_stack_entries = 42;
2715 num_hs_stack_entries = 42;
2716 num_ls_stack_entries = 42;
2717 break;
2718 case CHIP_SUMO2:
2719 num_ps_threads = 96;
2720 num_vs_threads = 25;
2721 num_gs_threads = 25;
2722 num_es_threads = 25;
2723 num_hs_threads = 25;
2724 num_ls_threads = 25;
2725 num_ps_stack_entries = 85;
2726 num_vs_stack_entries = 85;
2727 num_gs_stack_entries = 85;
2728 num_es_stack_entries = 85;
2729 num_hs_stack_entries = 85;
2730 num_ls_stack_entries = 85;
2731 break;
2732 case CHIP_BARTS:
2733 num_ps_threads = 128;
2734 num_vs_threads = 20;
2735 num_gs_threads = 20;
2736 num_es_threads = 20;
2737 num_hs_threads = 20;
2738 num_ls_threads = 20;
2739 num_ps_stack_entries = 85;
2740 num_vs_stack_entries = 85;
2741 num_gs_stack_entries = 85;
2742 num_es_stack_entries = 85;
2743 num_hs_stack_entries = 85;
2744 num_ls_stack_entries = 85;
2745 break;
2746 case CHIP_TURKS:
2747 num_ps_threads = 128;
2748 num_vs_threads = 20;
2749 num_gs_threads = 20;
2750 num_es_threads = 20;
2751 num_hs_threads = 20;
2752 num_ls_threads = 20;
2753 num_ps_stack_entries = 42;
2754 num_vs_stack_entries = 42;
2755 num_gs_stack_entries = 42;
2756 num_es_stack_entries = 42;
2757 num_hs_stack_entries = 42;
2758 num_ls_stack_entries = 42;
2759 break;
2760 case CHIP_CAICOS:
2761 num_ps_threads = 128;
2762 num_vs_threads = 10;
2763 num_gs_threads = 10;
2764 num_es_threads = 10;
2765 num_hs_threads = 10;
2766 num_ls_threads = 10;
2767 num_ps_stack_entries = 42;
2768 num_vs_stack_entries = 42;
2769 num_gs_stack_entries = 42;
2770 num_es_stack_entries = 42;
2771 num_hs_stack_entries = 42;
2772 num_ls_stack_entries = 42;
2773 break;
2774 }
2775
2776 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2777 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2778 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2779 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2780
2781 r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2782 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2783
2784 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2785 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2786 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2787
2788 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2789 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2790 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2791
2792 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2793 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2794 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2795
2796 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2797 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2798 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2799
2800 r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2801 r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2802
2803 r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2804 r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2805 r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2806 r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2807 r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2808 r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2809 r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2810
2811 r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2812 r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2813 r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2814 r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2815 r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2816
2817 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2818 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2819 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2820 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2821 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2822 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2823 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2824 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2825 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2826 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2827 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2828 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2829 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2830 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2831
2832 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2833 r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2834 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2835
2836 r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2837
2838 r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2839 r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2840 r600_store_value(cb, 0);
2841 r600_store_value(cb, 0);
2842 r600_store_value(cb, 0);
2843 r600_store_value(cb, 0);
2844 r600_store_value(cb, 0);
2845 r600_store_value(cb, 0);
2846 r600_store_value(cb, 0);
2847 r600_store_value(cb, 0);
2848 r600_store_value(cb, 0);
2849 r600_store_value(cb, 0);
2850 r600_store_value(cb, 0);
2851 r600_store_value(cb, 0);
2852 r600_store_value(cb, 0);
2853 r600_store_value(cb, 0);
2854 r600_store_value(cb, 0);
2855 r600_store_value(cb, 0);
2856 r600_store_value(cb, 0);
2857 r600_store_value(cb, 0);
2858 r600_store_value(cb, 0);
2859 r600_store_value(cb, 0);
2860 r600_store_value(cb, 0);
2861 r600_store_value(cb, 0);
2862 r600_store_value(cb, 0);
2863 r600_store_value(cb, 0);
2864 r600_store_value(cb, 0);
2865 r600_store_value(cb, 0);
2866 r600_store_value(cb, 0);
2867 r600_store_value(cb, 0);
2868 r600_store_value(cb, 0);
2869 r600_store_value(cb, 0);
2870 r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2871 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2872 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2873
2874 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2875
2876 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2877 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2878 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2879
2880 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2881 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2882
2883 r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2884 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2885 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2886
2887 r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2888 r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2889 r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2890 r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2891
2892 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2893 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2894 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2895 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2896 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2897
2898 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2899 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2900 r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2901
2902 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2903 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2904 r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2905
2906 r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2907
2908 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2909 if (rctx->screen->has_streamout) {
2910 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2911 }
2912
2913 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2914 eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2915 }
2916
evergreen_polygon_offset_update(struct r600_context * rctx)2917 void evergreen_polygon_offset_update(struct r600_context *rctx)
2918 {
2919 struct r600_pipe_state state;
2920
2921 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2922 state.nregs = 0;
2923 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2924 float offset_units = rctx->rasterizer->offset_units;
2925 unsigned offset_db_fmt_cntl = 0, depth;
2926
2927 switch (rctx->framebuffer.zsbuf->format) {
2928 case PIPE_FORMAT_Z24X8_UNORM:
2929 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2930 depth = -24;
2931 offset_units *= 2.0f;
2932 break;
2933 case PIPE_FORMAT_Z32_FLOAT:
2934 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2935 depth = -23;
2936 offset_units *= 1.0f;
2937 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2938 break;
2939 case PIPE_FORMAT_Z16_UNORM:
2940 depth = -16;
2941 offset_units *= 4.0f;
2942 break;
2943 default:
2944 return;
2945 }
2946 /* XXX some of those reg can be computed with cso */
2947 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2948 r600_pipe_state_add_reg(&state,
2949 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2950 fui(rctx->rasterizer->offset_scale));
2951 r600_pipe_state_add_reg(&state,
2952 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2953 fui(offset_units));
2954 r600_pipe_state_add_reg(&state,
2955 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2956 fui(rctx->rasterizer->offset_scale));
2957 r600_pipe_state_add_reg(&state,
2958 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2959 fui(offset_units));
2960 r600_pipe_state_add_reg(&state,
2961 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2962 offset_db_fmt_cntl);
2963 r600_context_pipe_state_set(rctx, &state);
2964 }
2965 }
2966
evergreen_pipe_shader_ps(struct pipe_context * ctx,struct r600_pipe_shader * shader)2967 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2968 {
2969 struct r600_context *rctx = (struct r600_context *)ctx;
2970 struct r600_pipe_state *rstate = &shader->rstate;
2971 struct r600_shader *rshader = &shader->shader;
2972 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2973 int pos_index = -1, face_index = -1;
2974 int ninterp = 0;
2975 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2976 unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2977 unsigned z_export = 0, stencil_export = 0;
2978
2979 rstate->nregs = 0;
2980
2981 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2982 for (i = 0; i < rshader->ninput; i++) {
2983 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2984 POSITION goes via GPRs from the SC so isn't counted */
2985 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2986 pos_index = i;
2987 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2988 face_index = i;
2989 else {
2990 ninterp++;
2991 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2992 have_linear = TRUE;
2993 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2994 have_perspective = TRUE;
2995 if (rshader->input[i].centroid)
2996 have_centroid = TRUE;
2997 }
2998
2999 sid = rshader->input[i].spi_sid;
3000
3001 if (sid) {
3002
3003 tmp = S_028644_SEMANTIC(sid);
3004
3005 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
3006 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
3007 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
3008 rctx->rasterizer && rctx->rasterizer->flatshade)) {
3009 tmp |= S_028644_FLAT_SHADE(1);
3010 }
3011
3012 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
3013 (rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
3014 tmp |= S_028644_PT_SPRITE_TEX(1);
3015 }
3016
3017 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
3018 tmp);
3019
3020 idx++;
3021 }
3022 }
3023
3024 for (i = 0; i < rshader->noutput; i++) {
3025 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3026 z_export = 1;
3027 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3028 stencil_export = 1;
3029 }
3030 if (rshader->uses_kill)
3031 db_shader_control |= S_02880C_KILL_ENABLE(1);
3032
3033 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3034 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3035
3036 exports_ps = 0;
3037 for (i = 0; i < rshader->noutput; i++) {
3038 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3039 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3040 exports_ps |= 1;
3041 }
3042
3043 num_cout = rshader->nr_ps_color_exports;
3044
3045 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3046 if (!exports_ps) {
3047 /* always at least export 1 component per pixel */
3048 exports_ps = 2;
3049 }
3050 shader->nr_ps_color_outputs = num_cout;
3051 if (ninterp == 0) {
3052 ninterp = 1;
3053 have_perspective = TRUE;
3054 }
3055
3056 if (!have_perspective && !have_linear)
3057 have_perspective = TRUE;
3058
3059 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3060 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3061 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3062 spi_input_z = 0;
3063 if (pos_index != -1) {
3064 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
3065 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
3066 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3067 spi_input_z |= 1;
3068 }
3069
3070 spi_ps_in_control_1 = 0;
3071 if (face_index != -1) {
3072 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3073 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3074 }
3075
3076 spi_baryc_cntl = 0;
3077 if (have_perspective)
3078 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
3079 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
3080 if (have_linear)
3081 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
3082 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
3083
3084 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
3085 spi_ps_in_control_0);
3086 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
3087 spi_ps_in_control_1);
3088 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
3089 0);
3090 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
3091 r600_pipe_state_add_reg(rstate,
3092 R_0286E0_SPI_BARYC_CNTL,
3093 spi_baryc_cntl);
3094
3095 r600_pipe_state_add_reg_bo(rstate,
3096 R_028840_SQ_PGM_START_PS,
3097 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3098 shader->bo, RADEON_USAGE_READ);
3099 r600_pipe_state_add_reg(rstate,
3100 R_028844_SQ_PGM_RESOURCES_PS,
3101 S_028844_NUM_GPRS(rshader->bc.ngpr) |
3102 S_028844_PRIME_CACHE_ON_DRAW(1) |
3103 S_028844_STACK_SIZE(rshader->bc.nstack));
3104 r600_pipe_state_add_reg(rstate,
3105 R_02884C_SQ_PGM_EXPORTS_PS,
3106 exports_ps);
3107
3108 shader->db_shader_control = db_shader_control;
3109 shader->ps_depth_export = z_export | stencil_export;
3110
3111 shader->sprite_coord_enable = rctx->sprite_coord_enable;
3112 if (rctx->rasterizer)
3113 shader->flatshade = rctx->rasterizer->flatshade;
3114 }
3115
evergreen_pipe_shader_vs(struct pipe_context * ctx,struct r600_pipe_shader * shader)3116 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3117 {
3118 struct r600_context *rctx = (struct r600_context *)ctx;
3119 struct r600_pipe_state *rstate = &shader->rstate;
3120 struct r600_shader *rshader = &shader->shader;
3121 unsigned spi_vs_out_id[10] = {};
3122 unsigned i, tmp, nparams = 0;
3123
3124 /* clear previous register */
3125 rstate->nregs = 0;
3126
3127 for (i = 0; i < rshader->noutput; i++) {
3128 if (rshader->output[i].spi_sid) {
3129 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3130 spi_vs_out_id[nparams / 4] |= tmp;
3131 nparams++;
3132 }
3133 }
3134
3135 for (i = 0; i < 10; i++) {
3136 r600_pipe_state_add_reg(rstate,
3137 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
3138 spi_vs_out_id[i]);
3139 }
3140
3141 /* Certain attributes (position, psize, etc.) don't count as params.
3142 * VS is required to export at least one param and r600_shader_from_tgsi()
3143 * takes care of adding a dummy export.
3144 */
3145 if (nparams < 1)
3146 nparams = 1;
3147
3148 r600_pipe_state_add_reg(rstate,
3149 R_0286C4_SPI_VS_OUT_CONFIG,
3150 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3151 r600_pipe_state_add_reg(rstate,
3152 R_028860_SQ_PGM_RESOURCES_VS,
3153 S_028860_NUM_GPRS(rshader->bc.ngpr) |
3154 S_028860_STACK_SIZE(rshader->bc.nstack));
3155 r600_pipe_state_add_reg_bo(rstate,
3156 R_02885C_SQ_PGM_START_VS,
3157 r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3158 shader->bo, RADEON_USAGE_READ);
3159
3160 shader->pa_cl_vs_out_cntl =
3161 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3162 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3163 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3164 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
3165 }
3166
evergreen_fetch_shader(struct pipe_context * ctx,struct r600_vertex_element * ve)3167 void evergreen_fetch_shader(struct pipe_context *ctx,
3168 struct r600_vertex_element *ve)
3169 {
3170 struct r600_context *rctx = (struct r600_context *)ctx;
3171 struct r600_pipe_state *rstate = &ve->rstate;
3172 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
3173 rstate->nregs = 0;
3174 r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
3175 r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
3176 ve->fetch_shader, RADEON_USAGE_READ);
3177 }
3178
evergreen_create_resolve_blend(struct r600_context * rctx)3179 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3180 {
3181 struct pipe_blend_state blend;
3182 struct r600_pipe_state *rstate;
3183
3184 memset(&blend, 0, sizeof(blend));
3185 blend.independent_blend_enable = true;
3186 blend.rt[0].colormask = 0xf;
3187 rstate = evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_RESOLVE);
3188 return rstate;
3189 }
3190
evergreen_create_decompress_blend(struct r600_context * rctx)3191 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3192 {
3193 struct pipe_blend_state blend;
3194 struct r600_pipe_state *rstate;
3195
3196 memset(&blend, 0, sizeof(blend));
3197 blend.independent_blend_enable = true;
3198 blend.rt[0].colormask = 0xf;
3199 rstate = evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_DECOMPRESS);
3200 return rstate;
3201 }
3202
evergreen_create_db_flush_dsa(struct r600_context * rctx)3203 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3204 {
3205 struct pipe_depth_stencil_alpha_state dsa = {{0}};
3206
3207 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
3208 }
3209
evergreen_update_dual_export_state(struct r600_context * rctx)3210 void evergreen_update_dual_export_state(struct r600_context * rctx)
3211 {
3212 unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
3213 !rctx->ps_shader->current->ps_depth_export;
3214
3215 unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
3216 V_02880C_EXPORT_DB_FULL;
3217
3218 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
3219 S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3220 S_02880C_DB_SOURCE_FORMAT(db_source_format) |
3221 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->cb0_is_integer);
3222
3223 if (db_shader_control != rctx->db_shader_control) {
3224 struct r600_pipe_state rstate;
3225
3226 rctx->db_shader_control = db_shader_control;
3227
3228 rstate.nregs = 0;
3229 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
3230 r600_context_pipe_state_set(rctx, &rstate);
3231 }
3232 }
3233