1 /*
2 * Copyright © 2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include "main/mtypes.h"
29 #include "intel_batchbuffer.h"
30
31 #include "brw_context.h"
32 #include "brw_defines.h"
33
34 static void
35 batch_out(struct brw_context *brw, const char *name, uint32_t offset,
36 int index, char *fmt, ...) PRINTFLIKE(5, 6);
37
38 static void
batch_out(struct brw_context * brw,const char * name,uint32_t offset,int index,char * fmt,...)39 batch_out(struct brw_context *brw, const char *name, uint32_t offset,
40 int index, char *fmt, ...)
41 {
42 struct intel_context *intel = &brw->intel;
43 uint32_t *data = intel->batch.bo->virtual + offset;
44 va_list va;
45
46 fprintf(stderr, "0x%08x: 0x%08x: %8s: ",
47 offset + index * 4, data[index], name);
48 va_start(va, fmt);
49 vfprintf(stderr, fmt, va);
50 va_end(va);
51 }
52
53 static const char *
get_965_surfacetype(unsigned int surfacetype)54 get_965_surfacetype(unsigned int surfacetype)
55 {
56 switch (surfacetype) {
57 case 0: return "1D";
58 case 1: return "2D";
59 case 2: return "3D";
60 case 3: return "CUBE";
61 case 4: return "BUFFER";
62 case 7: return "NULL";
63 default: return "unknown";
64 }
65 }
66
67 static const char *
get_965_surface_format(unsigned int surface_format)68 get_965_surface_format(unsigned int surface_format)
69 {
70 switch (surface_format) {
71 case 0x000: return "r32g32b32a32_float";
72 case 0x0c1: return "b8g8r8a8_unorm";
73 case 0x100: return "b5g6r5_unorm";
74 case 0x102: return "b5g5r5a1_unorm";
75 case 0x104: return "b4g4r4a4_unorm";
76 default: return "unknown";
77 }
78 }
79
dump_vs_state(struct brw_context * brw,uint32_t offset)80 static void dump_vs_state(struct brw_context *brw, uint32_t offset)
81 {
82 struct intel_context *intel = &brw->intel;
83 const char *name = "VS_STATE";
84 struct brw_vs_unit_state *vs = intel->batch.bo->virtual + offset;
85
86 batch_out(brw, name, offset, 0, "thread0\n");
87 batch_out(brw, name, offset, 1, "thread1\n");
88 batch_out(brw, name, offset, 2, "thread2\n");
89 batch_out(brw, name, offset, 3, "thread3\n");
90 batch_out(brw, name, offset, 4, "thread4: %d threads\n",
91 vs->thread4.max_threads + 1);
92 batch_out(brw, name, offset, 5, "vs5\n");
93 batch_out(brw, name, offset, 6, "vs6\n");
94 }
95
dump_gs_state(struct brw_context * brw,uint32_t offset)96 static void dump_gs_state(struct brw_context *brw, uint32_t offset)
97 {
98 struct intel_context *intel = &brw->intel;
99 const char *name = "GS_STATE";
100 struct brw_gs_unit_state *gs = intel->batch.bo->virtual + offset;
101
102 batch_out(brw, name, offset, 0, "thread0\n");
103 batch_out(brw, name, offset, 1, "thread1\n");
104 batch_out(brw, name, offset, 2, "thread2\n");
105 batch_out(brw, name, offset, 3, "thread3\n");
106 batch_out(brw, name, offset, 4, "thread4: %d threads\n",
107 gs->thread4.max_threads + 1);
108 batch_out(brw, name, offset, 5, "vs5\n");
109 batch_out(brw, name, offset, 6, "vs6\n");
110 }
111
dump_clip_state(struct brw_context * brw,uint32_t offset)112 static void dump_clip_state(struct brw_context *brw, uint32_t offset)
113 {
114 struct intel_context *intel = &brw->intel;
115 const char *name = "CLIP_STATE";
116 struct brw_clip_unit_state *clip = intel->batch.bo->virtual + offset;
117
118 batch_out(brw, name, offset, 0, "thread0\n");
119 batch_out(brw, name, offset, 1, "thread1\n");
120 batch_out(brw, name, offset, 2, "thread2\n");
121 batch_out(brw, name, offset, 3, "thread3\n");
122 batch_out(brw, name, offset, 4, "thread4: %d threads\n",
123 clip->thread4.max_threads + 1);
124 batch_out(brw, name, offset, 5, "clip5\n");
125 batch_out(brw, name, offset, 6, "clip6\n");
126 batch_out(brw, name, offset, 7, "vp xmin %f\n", clip->viewport_xmin);
127 batch_out(brw, name, offset, 8, "vp xmax %f\n", clip->viewport_xmax);
128 batch_out(brw, name, offset, 9, "vp ymin %f\n", clip->viewport_ymin);
129 batch_out(brw, name, offset, 10, "vp ymax %f\n", clip->viewport_ymax);
130 }
131
dump_sf_state(struct brw_context * brw,uint32_t offset)132 static void dump_sf_state(struct brw_context *brw, uint32_t offset)
133 {
134 struct intel_context *intel = &brw->intel;
135 const char *name = "SF_STATE";
136 struct brw_sf_unit_state *sf = intel->batch.bo->virtual + offset;
137
138 batch_out(brw, name, offset, 0, "thread0\n");
139 batch_out(brw, name, offset, 1, "thread1\n");
140 batch_out(brw, name, offset, 2, "thread2\n");
141 batch_out(brw, name, offset, 3, "thread3\n");
142 batch_out(brw, name, offset, 4, "thread4: %d threads\n",
143 sf->thread4.max_threads + 1);
144 batch_out(brw, name, offset, 5, "sf5: viewport offset\n");
145 batch_out(brw, name, offset, 6, "sf6\n");
146 batch_out(brw, name, offset, 7, "sf7\n");
147 }
148
dump_wm_state(struct brw_context * brw,uint32_t offset)149 static void dump_wm_state(struct brw_context *brw, uint32_t offset)
150 {
151 struct intel_context *intel = &brw->intel;
152 const char *name = "WM_STATE";
153 struct brw_wm_unit_state *wm = intel->batch.bo->virtual + offset;
154
155 batch_out(brw, name, offset, 0, "thread0\n");
156 batch_out(brw, name, offset, 1, "thread1\n");
157 batch_out(brw, name, offset, 2, "thread2\n");
158 batch_out(brw, name, offset, 3, "thread3\n");
159 batch_out(brw, name, offset, 4, "wm4\n");
160 batch_out(brw, name, offset, 5, "wm5: %s%s%s%s%s%s, %d threads\n",
161 wm->wm5.enable_8_pix ? "8pix" : "",
162 wm->wm5.enable_16_pix ? "16pix" : "",
163 wm->wm5.program_uses_depth ? ", uses depth" : "",
164 wm->wm5.program_computes_depth ? ", computes depth" : "",
165 wm->wm5.program_uses_killpixel ? ", kills" : "",
166 wm->wm5.thread_dispatch_enable ? "" : ", no dispatch",
167 wm->wm5.max_threads + 1);
168 batch_out(brw, name, offset, 6, "depth offset constant %f\n",
169 wm->global_depth_offset_constant);
170 batch_out(brw, name, offset, 7, "depth offset scale %f\n",
171 wm->global_depth_offset_scale);
172 batch_out(brw, name, offset, 8, "wm8: kernel 1 (gen5+)\n");
173 batch_out(brw, name, offset, 9, "wm9: kernel 2 (gen5+)\n");
174 batch_out(brw, name, offset, 10, "wm10: kernel 3 (gen5+)\n");
175 }
176
dump_surface_state(struct brw_context * brw,uint32_t offset)177 static void dump_surface_state(struct brw_context *brw, uint32_t offset)
178 {
179 const char *name = "SURF";
180 uint32_t *surf = brw->intel.batch.bo->virtual + offset;
181
182 batch_out(brw, name, offset, 0, "%s %s\n",
183 get_965_surfacetype(GET_FIELD(surf[0], BRW_SURFACE_TYPE)),
184 get_965_surface_format(GET_FIELD(surf[0], BRW_SURFACE_FORMAT)));
185 batch_out(brw, name, offset, 1, "offset\n");
186 batch_out(brw, name, offset, 2, "%dx%d size, %d mips\n",
187 GET_FIELD(surf[2], BRW_SURFACE_WIDTH) + 1,
188 GET_FIELD(surf[2], BRW_SURFACE_HEIGHT) + 1,
189 GET_FIELD(surf[2], BRW_SURFACE_LOD));
190 batch_out(brw, name, offset, 3, "pitch %d, %s tiled\n",
191 GET_FIELD(surf[3], BRW_SURFACE_PITCH) + 1,
192 (surf[3] & BRW_SURFACE_TILED) ?
193 ((surf[3] & BRW_SURFACE_TILED_Y) ? "Y" : "X") : "not");
194 batch_out(brw, name, offset, 4, "mip base %d\n",
195 GET_FIELD(surf[4], BRW_SURFACE_MIN_LOD));
196 batch_out(brw, name, offset, 5, "x,y offset: %d,%d\n",
197 GET_FIELD(surf[5], BRW_SURFACE_X_OFFSET),
198 GET_FIELD(surf[5], BRW_SURFACE_Y_OFFSET));
199 }
200
dump_gen7_surface_state(struct brw_context * brw,uint32_t offset)201 static void dump_gen7_surface_state(struct brw_context *brw, uint32_t offset)
202 {
203 const char *name = "SURF";
204 struct gen7_surface_state *surf = brw->intel.batch.bo->virtual + offset;
205
206 batch_out(brw, name, offset, 0, "%s %s\n",
207 get_965_surfacetype(surf->ss0.surface_type),
208 get_965_surface_format(surf->ss0.surface_format));
209 batch_out(brw, name, offset, 1, "offset\n");
210 batch_out(brw, name, offset, 2, "%dx%d size, %d mips\n",
211 surf->ss2.width + 1, surf->ss2.height + 1, surf->ss5.mip_count);
212 batch_out(brw, name, offset, 3, "pitch %d, %stiled\n",
213 surf->ss3.pitch + 1, surf->ss0.tiled_surface ? "" : "not ");
214 batch_out(brw, name, offset, 4, "mip base %d\n",
215 surf->ss5.min_lod);
216 batch_out(brw, name, offset, 5, "x,y offset: %d,%d\n",
217 surf->ss5.x_offset, surf->ss5.y_offset);
218 }
219
220 static void
dump_sdc(struct brw_context * brw,uint32_t offset)221 dump_sdc(struct brw_context *brw, uint32_t offset)
222 {
223 const char *name = "SDC";
224 struct intel_context *intel = &brw->intel;
225
226 if (intel->gen >= 5 && intel->gen <= 6) {
227 struct gen5_sampler_default_color *sdc = (intel->batch.bo->virtual +
228 offset);
229 batch_out(brw, name, offset, 0, "unorm rgba\n");
230 batch_out(brw, name, offset, 1, "r %f\n", sdc->f[0]);
231 batch_out(brw, name, offset, 2, "b %f\n", sdc->f[1]);
232 batch_out(brw, name, offset, 3, "g %f\n", sdc->f[2]);
233 batch_out(brw, name, offset, 4, "a %f\n", sdc->f[3]);
234 batch_out(brw, name, offset, 5, "half float rg\n");
235 batch_out(brw, name, offset, 6, "half float ba\n");
236 batch_out(brw, name, offset, 7, "u16 rg\n");
237 batch_out(brw, name, offset, 8, "u16 ba\n");
238 batch_out(brw, name, offset, 9, "s16 rg\n");
239 batch_out(brw, name, offset, 10, "s16 ba\n");
240 batch_out(brw, name, offset, 11, "s8 rgba\n");
241 } else {
242 struct brw_sampler_default_color *sdc = (intel->batch.bo->virtual +
243 offset);
244 batch_out(brw, name, offset, 0, "r %f\n", sdc->color[0]);
245 batch_out(brw, name, offset, 1, "g %f\n", sdc->color[1]);
246 batch_out(brw, name, offset, 2, "b %f\n", sdc->color[2]);
247 batch_out(brw, name, offset, 3, "a %f\n", sdc->color[3]);
248 }
249 }
250
dump_sampler_state(struct brw_context * brw,uint32_t offset,uint32_t size)251 static void dump_sampler_state(struct brw_context *brw,
252 uint32_t offset, uint32_t size)
253 {
254 struct intel_context *intel = &brw->intel;
255 int i;
256 struct brw_sampler_state *samp = intel->batch.bo->virtual + offset;
257
258 assert(intel->gen < 7);
259
260 for (i = 0; i < size / sizeof(*samp); i++) {
261 char name[20];
262
263 sprintf(name, "WM SAMP%d", i);
264 batch_out(brw, name, offset, 0, "filtering\n");
265 batch_out(brw, name, offset, 1, "wrapping, lod\n");
266 batch_out(brw, name, offset, 2, "default color pointer\n");
267 batch_out(brw, name, offset, 3, "chroma key, aniso\n");
268
269 samp++;
270 offset += sizeof(*samp);
271 }
272 }
273
dump_gen7_sampler_state(struct brw_context * brw,uint32_t offset,uint32_t size)274 static void dump_gen7_sampler_state(struct brw_context *brw,
275 uint32_t offset, uint32_t size)
276 {
277 struct intel_context *intel = &brw->intel;
278 struct gen7_sampler_state *samp = intel->batch.bo->virtual + offset;
279 int i;
280
281 assert(intel->gen >= 7);
282
283 for (i = 0; i < size / sizeof(*samp); i++) {
284 char name[20];
285
286 sprintf(name, "WM SAMP%d", i);
287 batch_out(brw, name, offset, 0, "filtering\n");
288 batch_out(brw, name, offset, 1, "wrapping, lod\n");
289 batch_out(brw, name, offset, 2, "default color pointer\n");
290 batch_out(brw, name, offset, 3, "chroma key, aniso\n");
291
292 samp++;
293 offset += sizeof(*samp);
294 }
295 }
296
297
dump_sf_viewport_state(struct brw_context * brw,uint32_t offset)298 static void dump_sf_viewport_state(struct brw_context *brw,
299 uint32_t offset)
300 {
301 struct intel_context *intel = &brw->intel;
302 const char *name = "SF VP";
303 struct brw_sf_viewport *vp = intel->batch.bo->virtual + offset;
304
305 assert(intel->gen < 7);
306
307 batch_out(brw, name, offset, 0, "m00 = %f\n", vp->viewport.m00);
308 batch_out(brw, name, offset, 1, "m11 = %f\n", vp->viewport.m11);
309 batch_out(brw, name, offset, 2, "m22 = %f\n", vp->viewport.m22);
310 batch_out(brw, name, offset, 3, "m30 = %f\n", vp->viewport.m30);
311 batch_out(brw, name, offset, 4, "m31 = %f\n", vp->viewport.m31);
312 batch_out(brw, name, offset, 5, "m32 = %f\n", vp->viewport.m32);
313
314 batch_out(brw, name, offset, 6, "top left = %d,%d\n",
315 vp->scissor.xmin, vp->scissor.ymin);
316 batch_out(brw, name, offset, 7, "bottom right = %d,%d\n",
317 vp->scissor.xmax, vp->scissor.ymax);
318 }
319
dump_clip_viewport_state(struct brw_context * brw,uint32_t offset)320 static void dump_clip_viewport_state(struct brw_context *brw,
321 uint32_t offset)
322 {
323 struct intel_context *intel = &brw->intel;
324 const char *name = "CLIP VP";
325 struct brw_clipper_viewport *vp = intel->batch.bo->virtual + offset;
326
327 assert(intel->gen < 7);
328
329 batch_out(brw, name, offset, 0, "xmin = %f\n", vp->xmin);
330 batch_out(brw, name, offset, 1, "xmax = %f\n", vp->xmax);
331 batch_out(brw, name, offset, 2, "ymin = %f\n", vp->ymin);
332 batch_out(brw, name, offset, 3, "ymax = %f\n", vp->ymax);
333 }
334
dump_sf_clip_viewport_state(struct brw_context * brw,uint32_t offset)335 static void dump_sf_clip_viewport_state(struct brw_context *brw,
336 uint32_t offset)
337 {
338 struct intel_context *intel = &brw->intel;
339 const char *name = "SF_CLIP VP";
340 struct gen7_sf_clip_viewport *vp = intel->batch.bo->virtual + offset;
341
342 assert(intel->gen >= 7);
343
344 batch_out(brw, name, offset, 0, "m00 = %f\n", vp->viewport.m00);
345 batch_out(brw, name, offset, 1, "m11 = %f\n", vp->viewport.m11);
346 batch_out(brw, name, offset, 2, "m22 = %f\n", vp->viewport.m22);
347 batch_out(brw, name, offset, 3, "m30 = %f\n", vp->viewport.m30);
348 batch_out(brw, name, offset, 4, "m31 = %f\n", vp->viewport.m31);
349 batch_out(brw, name, offset, 5, "m32 = %f\n", vp->viewport.m32);
350 batch_out(brw, name, offset, 6, "guardband xmin = %f\n", vp->guardband.xmin);
351 batch_out(brw, name, offset, 7, "guardband xmax = %f\n", vp->guardband.xmax);
352 batch_out(brw, name, offset, 8, "guardband ymin = %f\n", vp->guardband.ymin);
353 batch_out(brw, name, offset, 9, "guardband ymax = %f\n", vp->guardband.ymax);
354 }
355
356
dump_cc_viewport_state(struct brw_context * brw,uint32_t offset)357 static void dump_cc_viewport_state(struct brw_context *brw, uint32_t offset)
358 {
359 const char *name = "CC VP";
360 struct brw_cc_viewport *vp = brw->intel.batch.bo->virtual + offset;
361
362 batch_out(brw, name, offset, 0, "min_depth = %f\n", vp->min_depth);
363 batch_out(brw, name, offset, 1, "max_depth = %f\n", vp->max_depth);
364 }
365
dump_depth_stencil_state(struct brw_context * brw,uint32_t offset)366 static void dump_depth_stencil_state(struct brw_context *brw, uint32_t offset)
367 {
368 const char *name = "D_S";
369 struct gen6_depth_stencil_state *ds = brw->intel.batch.bo->virtual + offset;
370
371 batch_out(brw, name, offset, 0,
372 "stencil %sable, func %d, write %sable\n",
373 ds->ds0.stencil_enable ? "en" : "dis",
374 ds->ds0.stencil_func,
375 ds->ds0.stencil_write_enable ? "en" : "dis");
376 batch_out(brw, name, offset, 1,
377 "stencil test mask 0x%x, write mask 0x%x\n",
378 ds->ds1.stencil_test_mask, ds->ds1.stencil_write_mask);
379 batch_out(brw, name, offset, 2,
380 "depth test %sable, func %d, write %sable\n",
381 ds->ds2.depth_test_enable ? "en" : "dis",
382 ds->ds2.depth_test_func,
383 ds->ds2.depth_write_enable ? "en" : "dis");
384 }
385
dump_cc_state_gen4(struct brw_context * brw,uint32_t offset)386 static void dump_cc_state_gen4(struct brw_context *brw, uint32_t offset)
387 {
388 const char *name = "CC";
389
390 batch_out(brw, name, offset, 0, "cc0\n");
391 batch_out(brw, name, offset, 1, "cc1\n");
392 batch_out(brw, name, offset, 2, "cc2\n");
393 batch_out(brw, name, offset, 3, "cc3\n");
394 batch_out(brw, name, offset, 4, "cc4: viewport offset\n");
395 batch_out(brw, name, offset, 5, "cc5\n");
396 batch_out(brw, name, offset, 6, "cc6\n");
397 batch_out(brw, name, offset, 7, "cc7\n");
398 }
399
dump_cc_state_gen6(struct brw_context * brw,uint32_t offset)400 static void dump_cc_state_gen6(struct brw_context *brw, uint32_t offset)
401 {
402 const char *name = "CC";
403 struct gen6_color_calc_state *cc = brw->intel.batch.bo->virtual + offset;
404
405 batch_out(brw, name, offset, 0,
406 "alpha test format %s, round disable %d, stencil ref %d, "
407 "bf stencil ref %d\n",
408 cc->cc0.alpha_test_format ? "FLOAT32" : "UNORM8",
409 cc->cc0.round_disable,
410 cc->cc0.stencil_ref,
411 cc->cc0.bf_stencil_ref);
412 batch_out(brw, name, offset, 1, "\n");
413 batch_out(brw, name, offset, 2, "constant red %f\n", cc->constant_r);
414 batch_out(brw, name, offset, 3, "constant green %f\n", cc->constant_g);
415 batch_out(brw, name, offset, 4, "constant blue %f\n", cc->constant_b);
416 batch_out(brw, name, offset, 5, "constant alpha %f\n", cc->constant_a);
417 }
418
dump_blend_state(struct brw_context * brw,uint32_t offset)419 static void dump_blend_state(struct brw_context *brw, uint32_t offset)
420 {
421 const char *name = "BLEND";
422
423 batch_out(brw, name, offset, 0, "\n");
424 batch_out(brw, name, offset, 1, "\n");
425 }
426
427 static void
dump_scissor(struct brw_context * brw,uint32_t offset)428 dump_scissor(struct brw_context *brw, uint32_t offset)
429 {
430 const char *name = "SCISSOR";
431 struct intel_context *intel = &brw->intel;
432 struct gen6_scissor_rect *scissor = intel->batch.bo->virtual + offset;
433
434 batch_out(brw, name, offset, 0, "xmin %d, ymin %d\n",
435 scissor->xmin, scissor->ymin);
436 batch_out(brw, name, offset, 1, "xmax %d, ymax %d\n",
437 scissor->xmax, scissor->ymax);
438 }
439
440 static void
dump_vs_constants(struct brw_context * brw,uint32_t offset,uint32_t size)441 dump_vs_constants(struct brw_context *brw, uint32_t offset, uint32_t size)
442 {
443 const char *name = "VS_CONST";
444 struct intel_context *intel = &brw->intel;
445 uint32_t *as_uint = intel->batch.bo->virtual + offset;
446 float *as_float = intel->batch.bo->virtual + offset;
447 int i;
448
449 for (i = 0; i < size / 4; i += 4) {
450 batch_out(brw, name, offset, i, "%3d: (% f % f % f % f) (0x%08x 0x%08x 0x%08x 0x%08x)\n",
451 i / 4,
452 as_float[i], as_float[i + 1], as_float[i + 2], as_float[i + 3],
453 as_uint[i], as_uint[i + 1], as_uint[i + 2], as_uint[i + 3]);
454 }
455 }
456
457 static void
dump_wm_constants(struct brw_context * brw,uint32_t offset,uint32_t size)458 dump_wm_constants(struct brw_context *brw, uint32_t offset, uint32_t size)
459 {
460 const char *name = "WM_CONST";
461 struct intel_context *intel = &brw->intel;
462 uint32_t *as_uint = intel->batch.bo->virtual + offset;
463 float *as_float = intel->batch.bo->virtual + offset;
464 int i;
465
466 for (i = 0; i < size / 4; i += 4) {
467 batch_out(brw, name, offset, i, "%3d: (% f % f % f % f) (0x%08x 0x%08x 0x%08x 0x%08x)\n",
468 i / 4,
469 as_float[i], as_float[i + 1], as_float[i + 2], as_float[i + 3],
470 as_uint[i], as_uint[i + 1], as_uint[i + 2], as_uint[i + 3]);
471 }
472 }
473
dump_binding_table(struct brw_context * brw,uint32_t offset,uint32_t size)474 static void dump_binding_table(struct brw_context *brw, uint32_t offset,
475 uint32_t size)
476 {
477 char name[20];
478 int i;
479 uint32_t *data = brw->intel.batch.bo->virtual + offset;
480
481 for (i = 0; i < size / 4; i++) {
482 if (data[i] == 0)
483 continue;
484
485 sprintf(name, "BIND%d", i);
486 batch_out(brw, name, offset, i, "surface state address\n");
487 }
488 }
489
490 static void
dump_prog_cache(struct brw_context * brw)491 dump_prog_cache(struct brw_context *brw)
492 {
493 struct intel_context *intel = &brw->intel;
494 struct brw_cache *cache = &brw->cache;
495 unsigned int b, i;
496 uint32_t *data;
497
498 drm_intel_bo_map(brw->cache.bo, false);
499
500 for (b = 0; b < cache->size; b++) {
501 struct brw_cache_item *item;
502
503 for (item = cache->items[b]; item; item = item->next) {
504 const char *name;
505 uint32_t offset = item->offset;
506
507 data = brw->cache.bo->virtual + item->offset;
508
509 switch (item->cache_id) {
510 case BRW_VS_PROG:
511 name = "VS kernel";
512 break;
513 case BRW_GS_PROG:
514 name = "GS kernel";
515 break;
516 case BRW_CLIP_PROG:
517 name = "CLIP kernel";
518 break;
519 case BRW_SF_PROG:
520 name = "SF kernel";
521 break;
522 case BRW_WM_PROG:
523 name = "WM kernel";
524 break;
525 default:
526 name = "unknown";
527 break;
528 }
529
530 for (i = 0; i < item->size / 4 / 4; i++) {
531 fprintf(stderr, "0x%08x: %8s: 0x%08x 0x%08x 0x%08x 0x%08x ",
532 offset + i * 4 * 4,
533 name,
534 data[i * 4], data[i * 4 + 1], data[i * 4 + 2], data[i * 4 + 3]);
535
536 brw_disasm(stderr, (void *)(data + i * 4), intel->gen);
537 }
538 }
539 }
540
541 drm_intel_bo_unmap(brw->cache.bo);
542 }
543
544 static void
dump_state_batch(struct brw_context * brw)545 dump_state_batch(struct brw_context *brw)
546 {
547 struct intel_context *intel = &brw->intel;
548 int i;
549
550 for (i = 0; i < brw->state_batch_count; i++) {
551 uint32_t offset = brw->state_batch_list[i].offset;
552 uint32_t size = brw->state_batch_list[i].size;
553
554 switch (brw->state_batch_list[i].type) {
555 case AUB_TRACE_VS_STATE:
556 dump_vs_state(brw, offset);
557 break;
558 case AUB_TRACE_GS_STATE:
559 dump_gs_state(brw, offset);
560 break;
561 case AUB_TRACE_CLIP_STATE:
562 dump_clip_state(brw, offset);
563 break;
564 case AUB_TRACE_SF_STATE:
565 dump_sf_state(brw, offset);
566 break;
567 case AUB_TRACE_WM_STATE:
568 dump_wm_state(brw, offset);
569 break;
570 case AUB_TRACE_CLIP_VP_STATE:
571 dump_clip_viewport_state(brw, offset);
572 break;
573 case AUB_TRACE_SF_VP_STATE:
574 if (intel->gen >= 7) {
575 dump_sf_clip_viewport_state(brw, offset);
576 } else {
577 dump_sf_viewport_state(brw, offset);
578 }
579 break;
580 case AUB_TRACE_CC_VP_STATE:
581 dump_cc_viewport_state(brw, offset);
582 break;
583 case AUB_TRACE_DEPTH_STENCIL_STATE:
584 dump_depth_stencil_state(brw, offset);
585 break;
586 case AUB_TRACE_CC_STATE:
587 if (intel->gen >= 6)
588 dump_cc_state_gen6(brw, offset);
589 else
590 dump_cc_state_gen4(brw, offset);
591 break;
592 case AUB_TRACE_BLEND_STATE:
593 dump_blend_state(brw, offset);
594 break;
595 case AUB_TRACE_BINDING_TABLE:
596 dump_binding_table(brw, offset, size);
597 break;
598 case AUB_TRACE_SURFACE_STATE:
599 if (intel->gen < 7) {
600 dump_surface_state(brw, offset);
601 } else {
602 dump_gen7_surface_state(brw, offset);
603 }
604 break;
605 case AUB_TRACE_SAMPLER_STATE:
606 if (intel->gen < 7) {
607 dump_sampler_state(brw, offset, size);
608 } else {
609 dump_gen7_sampler_state(brw, offset, size);
610 }
611 break;
612 case AUB_TRACE_SAMPLER_DEFAULT_COLOR:
613 dump_sdc(brw, offset);
614 break;
615 case AUB_TRACE_SCISSOR_STATE:
616 dump_scissor(brw, offset);
617 break;
618 case AUB_TRACE_VS_CONSTANTS:
619 dump_vs_constants(brw, offset, size);
620 break;
621 case AUB_TRACE_WM_CONSTANTS:
622 dump_wm_constants(brw, offset, size);
623 break;
624 default:
625 break;
626 }
627 }
628 }
629
630 /**
631 * Print additional debug information associated with the batchbuffer
632 * when DEBUG_BATCH is set.
633 *
634 * For 965, this means mapping the state buffers that would have been referenced
635 * by the batchbuffer and dumping them.
636 *
637 * The buffer offsets printed rely on the buffer containing the last offset
638 * it was validated at.
639 */
brw_debug_batch(struct intel_context * intel)640 void brw_debug_batch(struct intel_context *intel)
641 {
642 struct brw_context *brw = brw_context(&intel->ctx);
643
644 drm_intel_bo_map(intel->batch.bo, false);
645 dump_state_batch(brw);
646 drm_intel_bo_unmap(intel->batch.bo);
647
648 if (0)
649 dump_prog_cache(brw);
650 }
651