1
2 /* To compile:
3 aarch64-linux-gnu-gcc -Wall -g -O0 -o memory none/tests/arm64/memory.c
4 */
5
6 #include <stdio.h>
7 #include <malloc.h> // memalign
8 #include <string.h> // memset
9 #include "tests/malloc.h"
10 #include <assert.h>
11
12 typedef unsigned char UChar;
13 typedef unsigned short int UShort;
14 typedef unsigned int UInt;
15 typedef signed int Int;
16 typedef unsigned char UChar;
17 typedef signed long long int Long;
18 typedef unsigned long long int ULong;
19
20 typedef unsigned char Bool;
21 #define False ((Bool)0)
22 #define True ((Bool)1)
23
randUChar(void)24 static inline UChar randUChar ( void )
25 {
26 static UInt seed = 80021;
27 seed = 1103515245 * seed + 12345;
28 return (seed >> 17) & 0xFF;
29 }
30
randULong(void)31 static ULong randULong ( void )
32 {
33 Int i;
34 ULong r = 0;
35 for (i = 0; i < 8; i++) {
36 r = (r << 8) | (ULong)(0xFF & randUChar());
37 }
38 return r;
39 }
40
41
42 // Same as TESTINST2 except it doesn't print the RN value, since
43 // that may differ between runs (it's a stack address). Also,
44 // claim it trashes x28 so that can be used as scratch if needed.
45 #define TESTINST2_hide2(instruction, RNval, RD, RN, carryin) \
46 { \
47 ULong out; \
48 ULong nzcv_out; \
49 ULong nzcv_in = (carryin ? (1<<29) : 0); \
50 __asm__ __volatile__( \
51 "msr nzcv,%3;" \
52 "mov " #RN ",%2;" \
53 instruction ";" \
54 "mov %0," #RD ";" \
55 "mrs %1,nzcv;" \
56 : "=&r" (out), "=&r" (nzcv_out) \
57 : "r" (RNval), "r" (nzcv_in) \
58 : #RD, #RN, "cc", "memory", "x28" \
59 ); \
60 printf("%s :: rd %016llx rn (hidden), " \
61 "cin %d, nzcv %08llx %c%c%c%c\n", \
62 instruction, out, \
63 carryin ? 1 : 0, \
64 nzcv_out & 0xffff0000, \
65 ((1<<31) & nzcv_out) ? 'N' : ' ', \
66 ((1<<30) & nzcv_out) ? 'Z' : ' ', \
67 ((1<<29) & nzcv_out) ? 'C' : ' ', \
68 ((1<<28) & nzcv_out) ? 'V' : ' ' \
69 ); \
70 }
71
72 #define TESTINST3_hide2and3(instruction, RMval, RNval, RD, RM, RN, carryin) \
73 { \
74 ULong out; \
75 ULong nzcv_out; \
76 ULong nzcv_in = (carryin ? (1<<29) : 0); \
77 __asm__ __volatile__( \
78 "msr nzcv,%4;" \
79 "mov " #RM ",%2;" \
80 "mov " #RN ",%3;" \
81 instruction ";" \
82 "mov %0," #RD ";" \
83 "mrs %1,nzcv;" \
84 : "=&r" (out), "=&r" (nzcv_out) \
85 : "r" (RMval), "r" (RNval), "r" (nzcv_in) \
86 : #RD, #RM, #RN, "cc", "memory" \
87 ); \
88 printf("%s :: rd %016llx rm (hidden), rn (hidden), " \
89 "cin %d, nzcv %08llx %c%c%c%c\n", \
90 instruction, out, \
91 carryin ? 1 : 0, \
92 nzcv_out & 0xffff0000, \
93 ((1<<31) & nzcv_out) ? 'N' : ' ', \
94 ((1<<30) & nzcv_out) ? 'Z' : ' ', \
95 ((1<<29) & nzcv_out) ? 'C' : ' ', \
96 ((1<<28) & nzcv_out) ? 'V' : ' ' \
97 ); \
98 }
99
100
101 ////////////////////////////////////////////////////////////////
102 ////////////////////////////////////////////////////////////////
103 ////////////////////////////////////////////////////////////////
104 // //
105 // test_memory_old //
106 // //
107 ////////////////////////////////////////////////////////////////
108 ////////////////////////////////////////////////////////////////
109 ////////////////////////////////////////////////////////////////
110
test_memory_old(void)111 static __attribute((noinline)) void test_memory_old ( void )
112 {
113 printf("Integer loads\n");
114
115 unsigned char area[512];
116
117 #define RESET \
118 do { int i; for (i = 0; i < sizeof(area); i++) \
119 area[i] = i | 0x80; \
120 } while (0)
121
122 #define AREA_MID (((ULong)(&area[(sizeof(area)/2)-1])) & (~(ULong)0xF))
123
124 RESET;
125
126 ////////////////////////////////////////////////////////////////
127 printf("LDR,STR (immediate, uimm12) (STR cases are MISSING)");
128 TESTINST2_hide2("ldr x21, [x22, #24]", AREA_MID, x21,x22,0);
129 TESTINST2_hide2("ldr w21, [x22, #20]", AREA_MID, x21,x22,0);
130 TESTINST2_hide2("ldrh w21, [x22, #44]", AREA_MID, x21,x22,0);
131 TESTINST2_hide2("ldrb w21, [x22, #56]", AREA_MID, x21,x22,0);
132
133 ////////////////////////////////////////////////////////////////
134 printf("LDUR,STUR (immediate, simm9) (STR cases and wb check are MISSING)\n");
135 TESTINST2_hide2("ldr x21, [x22], #-24", AREA_MID, x21,x22,0);
136 TESTINST2_hide2("ldr x21, [x22, #-40]!", AREA_MID, x21,x22,0);
137 TESTINST2_hide2("ldr x21, [x22, #-48]", AREA_MID, x21,x22,0);
138 printf("LDUR,STUR (immediate, simm9): STR cases are MISSING");
139
140 ////////////////////////////////////////////////////////////////
141 // TESTINST2_hide2 allows use of x28 as scratch
142 printf("LDP,STP (immediate, simm7) (STR cases and wb check is MISSING)\n");
143
144 TESTINST2_hide2("ldp x21, x28, [x22], #-24 ; add x21,x21,x28", AREA_MID, x21,x22,0);
145 TESTINST2_hide2("ldp x21, x28, [x22], #-24 ; eor x21,x21,x28", AREA_MID, x21,x22,0);
146 TESTINST2_hide2("ldp x21, x28, [x22, #-40]! ; add x21,x21,x28", AREA_MID, x21,x22,0);
147 TESTINST2_hide2("ldp x21, x28, [x22, #-40]! ; eor x21,x21,x28", AREA_MID, x21,x22,0);
148 TESTINST2_hide2("ldp x21, x28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0);
149 TESTINST2_hide2("ldp x21, x28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0);
150
151 TESTINST2_hide2("ldp w21, w28, [x22], #-24 ; add x21,x21,x28", AREA_MID, x21,x22,0);
152 TESTINST2_hide2("ldp w21, w28, [x22], #-24 ; eor x21,x21,x28", AREA_MID, x21,x22,0);
153 TESTINST2_hide2("ldp w21, w28, [x22, #-40]! ; add x21,x21,x28", AREA_MID, x21,x22,0);
154 TESTINST2_hide2("ldp w21, w28, [x22, #-40]! ; eor x21,x21,x28", AREA_MID, x21,x22,0);
155 TESTINST2_hide2("ldp w21, w28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0);
156 TESTINST2_hide2("ldp w21, w28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0);
157
158 ////////////////////////////////////////////////////////////////
159 // This is a bit tricky. We load the value from just before and
160 // just after the actual instruction. Because TESTINSN2_hide2
161 // generates two fixed insns either side of the test insn, these
162 // should be constant and hence "safe" to check.
163
164 printf("LDR (literal, int reg)\n");
165 TESTINST2_hide2("xyzzy00: ldr x21, xyzzy00 - 8", AREA_MID, x21,x22,0);
166 TESTINST2_hide2("xyzzy01: ldr x21, xyzzy01 + 0", AREA_MID, x21,x22,0);
167 TESTINST2_hide2("xyzzy02: ldr x21, xyzzy02 + 8", AREA_MID, x21,x22,0);
168
169 TESTINST2_hide2("xyzzy03: ldr x21, xyzzy03 - 4", AREA_MID, x21,x22,0);
170 TESTINST2_hide2("xyzzy04: ldr x21, xyzzy04 + 0", AREA_MID, x21,x22,0);
171 TESTINST2_hide2("xyzzy05: ldr x21, xyzzy05 + 4", AREA_MID, x21,x22,0);
172
173 ////////////////////////////////////////////////////////////////
174 printf("{LD,ST}R (integer register) (entirely MISSING)\n");
175
176 ////////////////////////////////////////////////////////////////
177 printf("LDRS{B,H,W} (uimm12)\n");
178 TESTINST2_hide2("ldrsw x21, [x22, #24]", AREA_MID, x21,x22,0);
179 TESTINST2_hide2("ldrsh x21, [x22, #20]", AREA_MID, x21,x22,0);
180 TESTINST2_hide2("ldrsh w21, [x22, #44]", AREA_MID, x21,x22,0);
181 TESTINST2_hide2("ldrsb x21, [x22, #88]", AREA_MID, x21,x22,0);
182 TESTINST2_hide2("ldrsb w21, [x22, #56]", AREA_MID, x21,x22,0);
183
184 ////////////////////////////////////////////////////////////////
185 printf("LDRS{B,H,W} (simm9, upd) (upd check is MISSING)\n");
186 TESTINST2_hide2("ldrsw x21, [x22, #-24]!", AREA_MID, x21,x22,0);
187 TESTINST2_hide2("ldrsh x21, [x22, #-20]!", AREA_MID, x21,x22,0);
188 TESTINST2_hide2("ldrsh w21, [x22, #-44]!", AREA_MID, x21,x22,0);
189 TESTINST2_hide2("ldrsb x21, [x22, #-88]!", AREA_MID, x21,x22,0);
190 TESTINST2_hide2("ldrsb w21, [x22, #-56]!", AREA_MID, x21,x22,0);
191
192 TESTINST2_hide2("ldrsw x21, [x22], #-24", AREA_MID, x21,x22,0);
193 TESTINST2_hide2("ldrsh x21, [x22], #-20", AREA_MID, x21,x22,0);
194 TESTINST2_hide2("ldrsh w21, [x22], #-44", AREA_MID, x21,x22,0);
195 TESTINST2_hide2("ldrsb x21, [x22], #-88", AREA_MID, x21,x22,0);
196 TESTINST2_hide2("ldrsb w21, [x22], #-56", AREA_MID, x21,x22,0);
197
198 ////////////////////////////////////////////////////////////////
199 printf("LDRS{B,H,W} (simm9, noUpd)\n");
200 TESTINST2_hide2("ldrsw x21, [x22, #-24]", AREA_MID, x21,x22,0);
201 TESTINST2_hide2("ldrsh x21, [x22, #-20]", AREA_MID, x21,x22,0);
202 TESTINST2_hide2("ldrsh w21, [x22, #-44]", AREA_MID, x21,x22,0);
203 TESTINST2_hide2("ldrsb x21, [x22, #-88]", AREA_MID, x21,x22,0);
204 TESTINST2_hide2("ldrsb w21, [x22, #-56]", AREA_MID, x21,x22,0);
205
206 ////////////////////////////////////////////////////////////////
207 printf("LDP,STP (immediate, simm7) (FP&VEC) (entirely MISSING)\n");
208
209 ////////////////////////////////////////////////////////////////
210 printf("{LD,ST}R (vector register) (entirely MISSING)\n");
211
212 ////////////////////////////////////////////////////////////////
213 printf("LDRS{B,H,W} (integer register, SX)\n");
214
215 TESTINST3_hide2and3("ldrsw x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
216 TESTINST3_hide2and3("ldrsw x21, [x22,x23, lsl #2]", AREA_MID, 5, x21,x22,x23,0);
217 TESTINST3_hide2and3("ldrsw x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
218 TESTINST3_hide2and3("ldrsw x21, [x22,w23,uxtw #2]", AREA_MID, 5, x21,x22,x23,0);
219 TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
220 TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #2]", AREA_MID, -5ULL, x21,x22,x23,0);
221
222 TESTINST3_hide2and3("ldrsh x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
223 TESTINST3_hide2and3("ldrsh x21, [x22,x23, lsl #1]", AREA_MID, 5, x21,x22,x23,0);
224 TESTINST3_hide2and3("ldrsh x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
225 TESTINST3_hide2and3("ldrsh x21, [x22,w23,uxtw #1]", AREA_MID, 5, x21,x22,x23,0);
226 TESTINST3_hide2and3("ldrsh x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
227 TESTINST3_hide2and3("ldrsh x21, [x22,w23,sxtw #1]", AREA_MID, -5ULL, x21,x22,x23,0);
228
229 TESTINST3_hide2and3("ldrsh w21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
230 TESTINST3_hide2and3("ldrsh w21, [x22,x23, lsl #1]", AREA_MID, 5, x21,x22,x23,0);
231 TESTINST3_hide2and3("ldrsh w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
232 TESTINST3_hide2and3("ldrsh w21, [x22,w23,uxtw #1]", AREA_MID, 5, x21,x22,x23,0);
233 TESTINST3_hide2and3("ldrsh w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
234 TESTINST3_hide2and3("ldrsh w21, [x22,w23,sxtw #1]", AREA_MID, -5ULL, x21,x22,x23,0);
235
236 TESTINST3_hide2and3("ldrsb x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
237 TESTINST3_hide2and3("ldrsb x21, [x22,x23, lsl #0]", AREA_MID, 5, x21,x22,x23,0);
238 TESTINST3_hide2and3("ldrsb x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
239 TESTINST3_hide2and3("ldrsb x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
240 TESTINST3_hide2and3("ldrsb x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
241 TESTINST3_hide2and3("ldrsb x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
242
243 TESTINST3_hide2and3("ldrsb w21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
244 TESTINST3_hide2and3("ldrsb w21, [x22,x23, lsl #0]", AREA_MID, 5, x21,x22,x23,0);
245 TESTINST3_hide2and3("ldrsb w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
246 TESTINST3_hide2and3("ldrsb w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
247 TESTINST3_hide2and3("ldrsb w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
248 TESTINST3_hide2and3("ldrsb w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
249
250 ////////////////////////////////////////////////////////////////
251 printf("LDR/STR (immediate, SIMD&FP, unsigned offset) (entirely MISSING)\n");
252
253 ////////////////////////////////////////////////////////////////
254 printf("LDR/STR (immediate, SIMD&FP, pre/post index) (entirely MISSING)\n");
255
256 ////////////////////////////////////////////////////////////////
257 printf("LDUR/STUR (unscaled offset, SIMD&FP) (entirely MISSING)\n");
258
259 ////////////////////////////////////////////////////////////////
260 printf("LDR (literal, SIMD&FP) (entirely MISSING)\n");
261
262 ////////////////////////////////////////////////////////////////
263 printf("LD1/ST1 (single structure, no offset) (entirely MISSING)\n");
264
265 ////////////////////////////////////////////////////////////////
266 printf("LD1/ST1 (single structure, post index) (entirely MISSING)\n");
267
268 ////////////////////////////////////////////////////////////////
269 printf("LD{,A}X{R,RH,RB} (entirely MISSING)\n");
270
271 ////////////////////////////////////////////////////////////////
272 printf("ST{,L}X{R,RH,RB} (entirely MISSING)\n");
273
274 ////////////////////////////////////////////////////////////////
275 printf("LDA{R,RH,RB}\n");
276 TESTINST2_hide2("ldar x21, [x22]", AREA_MID, x21,x22,0);
277 TESTINST2_hide2("ldar w21, [x22]", AREA_MID, x21,x22,0);
278 TESTINST2_hide2("ldarh w21, [x22]", AREA_MID, x21,x22,0);
279 TESTINST2_hide2("ldarb w21, [x22]", AREA_MID, x21,x22,0);
280
281 ////////////////////////////////////////////////////////////////
282 printf("STL{R,RH,RB} (entirely MISSING)\n");
283 } /* end of test_memory_old() */
284
285
286 ////////////////////////////////////////////////////////////////
287 ////////////////////////////////////////////////////////////////
288 ////////////////////////////////////////////////////////////////
289 // //
290 // test_memory_new //
291 // //
292 ////////////////////////////////////////////////////////////////
293 ////////////////////////////////////////////////////////////////
294 ////////////////////////////////////////////////////////////////
295
show_block_xor(UChar * block1,UChar * block2,Int n)296 static void show_block_xor ( UChar* block1, UChar* block2, Int n )
297 {
298 Int i;
299 printf(" ");
300 for (i = 0; i < n; i++) {
301 if (i > 0 && 0 == (i & 15)) printf("\n ");
302 if (0 == (i & 15)) printf("[%3d] ", i);
303 UInt diff = 0xFF & (UInt)(block1[i] - block2[i]);
304 if (diff == 0)
305 printf(".. ");
306 else
307 printf("%02x ", diff);
308 }
309 printf("\n");
310 }
311
312
313 // In: rand:
314 // memory area, xferred vec regs, xferred int regs,
315 // caller spec:
316 // addr reg1, addr reg2
317 //
318 // Out: memory area, xferred vec regs, xferred int regs, addr reg1, addr reg2
319 //
320 // INSN may mention the following regs as containing load/store data:
321 // x13 x23 v17 v18 v19 v20
322 // and
323 // x5 as containing the base address
324 // x6 as containing an offset, if required
325 // A memory area is filled with random data, and x13, x23, v17, v18, v19, v20
326 // are loaded with random data too. INSN is then executed, with
327 // x5 set to the middle of the memory area + AREG1OFF, and x6 set to AREG2VAL.
328 //
329 // What is printed out: the XOR of the new and old versions of the
330 // following:
331 // the memory area
332 // x13 x23 v17 v18 v19 v20
333 // and the SUB of the new and old values of the following:
334 // x5 x6
335 // If the insn modifies its base register then (obviously) the x5 "new - old"
336 // value will be nonzero.
337
338 #define MEM_TEST(INSN, AREG1OFF, AREG2VAL) { \
339 int i; \
340 const int N = 256; \
341 UChar* area = memalign16(N); \
342 UChar area2[N]; \
343 for (i = 0; i < N; i++) area[i] = area2[i] = randUChar(); \
344 ULong block[12]; \
345 /* 0:x13 1:x23 2:v17.d[0] 3:v17.d[1] 4:v18.d[0] 5:v18.d[1] */ \
346 /* 6:v19.d[0] 7:v19.d[1] 8:v20.d[0] 9:v20.d[1] 10:x5 11:x6 */ \
347 for (i = 0; i < 12; i++) block[i] = randULong(); \
348 block[10] = (ULong)(&area[128]) + (Long)(Int)AREG1OFF; \
349 block[11] = (Long)AREG2VAL; \
350 ULong block2[12]; \
351 for (i = 0; i < 12; i++) block2[i] = block[i]; \
352 __asm__ __volatile__( \
353 "ldr x13, [%0, #0] ; " \
354 "ldr x23, [%0, #8] ; " \
355 "ldr q17, [%0, #16] ; " \
356 "ldr q18, [%0, #32] ; " \
357 "ldr q19, [%0, #48] ; " \
358 "ldr q20, [%0, #64] ; " \
359 "ldr x5, [%0, #80] ; " \
360 "ldr x6, [%0, #88] ; " \
361 INSN " ; " \
362 "str x13, [%0, #0] ; " \
363 "str x23, [%0, #8] ; " \
364 "str q17, [%0, #16] ; " \
365 "str q18, [%0, #32] ; " \
366 "str q19, [%0, #48] ; " \
367 "str q20, [%0, #64] ; " \
368 "str x5, [%0, #80] ; " \
369 "str x6, [%0, #88] ; " \
370 : : "r"(&block[0]) : "x5", "x6", "x13", "x23", \
371 "v17", "v18", "v19", "v20", "memory", "cc" \
372 ); \
373 printf("%s with x5 = middle_of_block+%lld, x6=%lld\n", \
374 INSN, (Long)AREG1OFF, (Long)AREG2VAL); \
375 show_block_xor(&area2[0], area, 256); \
376 printf(" %016llx x13 (xor, xfer intreg #1)\n", block[0] ^ block2[0]); \
377 printf(" %016llx x23 (xor, xfer intreg #2)\n", block[1] ^ block2[1]); \
378 printf(" %016llx v17.d[0] (xor, xfer vecreg #1)\n", block[2] ^ block2[2]); \
379 printf(" %016llx v17.d[1] (xor, xfer vecreg #1)\n", block[3] ^ block2[3]); \
380 printf(" %016llx v18.d[0] (xor, xfer vecreg #2)\n", block[4] ^ block2[4]); \
381 printf(" %016llx v18.d[1] (xor, xfer vecreg #2)\n", block[5] ^ block2[5]); \
382 printf(" %016llx v19.d[0] (xor, xfer vecreg #3)\n", block[6] ^ block2[6]); \
383 printf(" %016llx v19.d[1] (xor, xfer vecreg #3)\n", block[7] ^ block2[7]); \
384 printf(" %016llx v20.d[0] (xor, xfer vecreg #3)\n", block[8] ^ block2[8]); \
385 printf(" %016llx v20.d[1] (xor, xfer vecreg #3)\n", block[9] ^ block2[9]); \
386 printf(" %16lld x5 (sub, base reg)\n", block[10] - block2[10]); \
387 printf(" %16lld x6 (sub, index reg)\n", block[11] - block2[11]); \
388 printf("\n"); \
389 free(area); \
390 }
391
392
test_memory_new(void)393 static __attribute__((noinline)) void test_memory_new ( void )
394 {
395 ////////////////////////////////////////////////////////////////
396 printf("LDR,STR (immediate, uimm12)");
397 MEM_TEST("ldr x13, [x5, #24]", -1, 0);
398 MEM_TEST("ldr w13, [x5, #20]", 1, 0);
399 MEM_TEST("ldrh w13, [x5, #44]", 2, 0);
400 MEM_TEST("ldrb w13, [x5, #56]", 3, 0);
401 MEM_TEST("str x13, [x5, #24]", -3, 0);
402 MEM_TEST("str w13, [x5, #20]", 5, 0);
403 MEM_TEST("strh w13, [x5, #44]", 6, 0);
404 MEM_TEST("strb w13, [x5, #56]", 7, 0);
405
406 ////////////////////////////////////////////////////////////////
407 printf("LDUR,STUR (immediate, simm9)\n");
408 MEM_TEST("ldr x13, [x5], #-24", 0, 0);
409 MEM_TEST("ldr x13, [x5, #-40]!", 0, 0);
410 MEM_TEST("ldr x13, [x5, #-48]", 0, 0);
411 MEM_TEST("str x13, [x5], #-24", 0, 0);
412 MEM_TEST("str x13, [x5, #-40]!", 0, 0);
413 MEM_TEST("str x13, [x5, #-48]", 0, 0);
414
415 ////////////////////////////////////////////////////////////////
416 printf("LDP,STP (immediate, simm7)\n");
417 MEM_TEST("ldp x13, x23, [x5], #-24", 0, 0);
418 MEM_TEST("ldp x13, x23, [x5, #-40]!", 0, 0);
419 MEM_TEST("ldp x13, x23, [x5, #-40]", 0, 0);
420 MEM_TEST("stp x13, x23, [x5], #-24", 0, 0);
421 MEM_TEST("stp x13, x23, [x5, #-40]!", 0, 0);
422 MEM_TEST("stp x13, x23, [x5, #-40]", 0, 0);
423
424 MEM_TEST("ldp w13, w23, [x5], #-24", 0, 0);
425 MEM_TEST("ldp w13, w23, [x5, #-40]!", 0, 0);
426 MEM_TEST("ldp w13, w23, [x5, #-40]", 0, 0);
427 MEM_TEST("stp w13, w23, [x5], #-24", 0, 0);
428 MEM_TEST("stp w13, w23, [x5, #-40]!", 0, 0);
429 MEM_TEST("stp w13, w23, [x5, #-40]", 0, 0);
430
431 ////////////////////////////////////////////////////////////////
432 printf("LDR (literal, int reg) (done above by test_memory_old)\n");
433
434 ////////////////////////////////////////////////////////////////
435 printf("{LD,ST}R (integer register)\n");
436 MEM_TEST("str x13, [x5, x6]", 12, -4);
437 MEM_TEST("str x13, [x5, x6, lsl #3]", 12, -4);
438 MEM_TEST("str x13, [x5, w6, uxtw]", 12, 4);
439 MEM_TEST("str x13, [x5, w6, uxtw #3]", 12, 4);
440 MEM_TEST("str x13, [x5, w6, sxtw]", 12, 4);
441 MEM_TEST("str x13, [x5, w6, sxtw #3]", 12, -4);
442 MEM_TEST("ldr x13, [x5, x6]", 12, -4);
443 MEM_TEST("ldr x13, [x5, x6, lsl #3]", 12, -4);
444 MEM_TEST("ldr x13, [x5, w6, uxtw]", 12, 4);
445 MEM_TEST("ldr x13, [x5, w6, uxtw #3]", 12, 4);
446 MEM_TEST("ldr x13, [x5, w6, sxtw]", 12, 4);
447 MEM_TEST("ldr x13, [x5, w6, sxtw #3]", 12, -4);
448
449 MEM_TEST("str w13, [x5, x6]", 12, -4);
450 MEM_TEST("str w13, [x5, x6, lsl #2]", 12, -4);
451 MEM_TEST("str w13, [x5, w6, uxtw]", 12, 4);
452 MEM_TEST("str w13, [x5, w6, uxtw #2]", 12, 4);
453 MEM_TEST("str w13, [x5, w6, sxtw]", 12, 4);
454 MEM_TEST("str w13, [x5, w6, sxtw #2]", 12, -4);
455 MEM_TEST("ldr w13, [x5, x6]", 12, -4);
456 MEM_TEST("ldr w13, [x5, x6, lsl #2]", 12, -4);
457 MEM_TEST("ldr w13, [x5, w6, uxtw]", 12, 4);
458 MEM_TEST("ldr w13, [x5, w6, uxtw #2]", 12, 4);
459 MEM_TEST("ldr w13, [x5, w6, sxtw]", 12, 4);
460 MEM_TEST("ldr w13, [x5, w6, sxtw #2]", 12, -4);
461
462 MEM_TEST("strh w13, [x5, x6]", 12, -4);
463 MEM_TEST("strh w13, [x5, x6, lsl #1]", 12, -4);
464 MEM_TEST("strh w13, [x5, w6, uxtw]", 12, 4);
465 MEM_TEST("strh w13, [x5, w6, uxtw #1]", 12, 4);
466 MEM_TEST("strh w13, [x5, w6, sxtw]", 12, 4);
467 MEM_TEST("strh w13, [x5, w6, sxtw #1]", 12, -4);
468 MEM_TEST("ldrh w13, [x5, x6]", 12, -4);
469 MEM_TEST("ldrh w13, [x5, x6, lsl #1]", 12, -4);
470 MEM_TEST("ldrh w13, [x5, w6, uxtw]", 12, 4);
471 MEM_TEST("ldrh w13, [x5, w6, uxtw #1]", 12, 4);
472 MEM_TEST("ldrh w13, [x5, w6, sxtw]", 12, 4);
473 MEM_TEST("ldrh w13, [x5, w6, sxtw #1]", 12, -4);
474
475 MEM_TEST("strb w13, [x5, x6]", 12, -4);
476 MEM_TEST("strb w13, [x5, x6, lsl #0]", 12, -4);
477 MEM_TEST("strb w13, [x5, w6, uxtw]", 12, 4);
478 MEM_TEST("strb w13, [x5, w6, uxtw #0]", 12, 4);
479 MEM_TEST("strb w13, [x5, w6, sxtw]", 12, 4);
480 MEM_TEST("strb w13, [x5, w6, sxtw #0]", 12, -4);
481 MEM_TEST("ldrb w13, [x5, x6]", 12, -4);
482 MEM_TEST("ldrb w13, [x5, x6, lsl #0]", 12, -4);
483 MEM_TEST("ldrb w13, [x5, w6, uxtw]", 12, 4);
484 MEM_TEST("ldrb w13, [x5, w6, uxtw #0]", 12, 4);
485 MEM_TEST("ldrb w13, [x5, w6, sxtw]", 12, 4);
486 MEM_TEST("ldrb w13, [x5, w6, sxtw #0]", 12, -4);
487
488 ////////////////////////////////////////////////////////////////
489 printf("LDRS{B,H,W} (uimm12)\n");
490 MEM_TEST("ldrsw x13, [x5, #24]", -16, 4);
491 MEM_TEST("ldrsh x13, [x5, #20]", -16, 4);
492 MEM_TEST("ldrsh w13, [x5, #44]", -16, 4);
493 MEM_TEST("ldrsb x13, [x5, #72]", -16, 4);
494 MEM_TEST("ldrsb w13, [x5, #56]", -16, 4);
495
496 ////////////////////////////////////////////////////////////////
497 printf("LDRS{B,H,W} (simm9, upd)\n");
498 MEM_TEST("ldrsw x13, [x5, #-24]!", -16, 4);
499 MEM_TEST("ldrsh x13, [x5, #-20]!", -16, 4);
500 MEM_TEST("ldrsh w13, [x5, #-44]!", -16, 4);
501 MEM_TEST("ldrsb x13, [x5, #-72]!", -16, 4);
502 MEM_TEST("ldrsb w13, [x5, #-56]!", -16, 4);
503
504 MEM_TEST("ldrsw x13, [x5], #-24", -16, 4);
505 MEM_TEST("ldrsh x13, [x5], #-20", -16, 4);
506 MEM_TEST("ldrsh w13, [x5], #-44", -16, 4);
507 MEM_TEST("ldrsb x13, [x5], #-72", -16, 4);
508 MEM_TEST("ldrsb w13, [x5], #-56", -16, 4);
509
510 ////////////////////////////////////////////////////////////////
511 printf("LDRS{B,H,W} (simm9, noUpd)\n");
512 MEM_TEST("ldrsw x13, [x5, #-24]", -16, 4);
513 MEM_TEST("ldrsh x13, [x5, #-20]", -16, 4);
514 MEM_TEST("ldrsh w13, [x5, #-44]", -16, 4);
515 MEM_TEST("ldrsb x13, [x5, #-72]", -16, 4);
516 MEM_TEST("ldrsb w13, [x5, #-56]", -16, 4);
517
518 ////////////////////////////////////////////////////////////////
519 printf("LDP,STP (immediate, simm7) (FP&VEC)\n");
520
521 MEM_TEST("stp q17, q18, [x5, 16]", -15, 4);
522 MEM_TEST("stp q19, q18, [x5, 32]!", -11, 4);
523 MEM_TEST("stp q20, q17, [x5], -48", -7, 4);
524
525 MEM_TEST("stp d18, d17, [x5, 16]", -15, 4);
526 MEM_TEST("stp d17, d19, [x5, 32]!", -11, 4);
527 MEM_TEST("stp d20, d18, [x5], -48", -7, 4);
528
529 MEM_TEST("stp s17, s18, [x5, 16]", -15, 4);
530 MEM_TEST("stp s19, s18, [x5, 32]!", -11, 4);
531 MEM_TEST("stp s20, s17, [x5], -48", -7, 4);
532
533 MEM_TEST("ldp q17, q18, [x5, 16]", -15, 4);
534 MEM_TEST("ldp q18, q19, [x5, 32]!", -11, 4);
535 MEM_TEST("ldp q19, q20, [x5], -48", -7, 4);
536
537 MEM_TEST("ldp d20, d17, [x5, 16]", -15, 4);
538 MEM_TEST("ldp d17, d18, [x5, 32]!", -11, 4);
539 MEM_TEST("ldp d18, d19, [x5], -48", -7, 4);
540
541 MEM_TEST("ldp s19, s20, [x5, 16]", -15, 4);
542 MEM_TEST("ldp s20, s17, [x5, 32]!", -11, 4);
543 MEM_TEST("ldp s17, s18, [x5], -48", -7, 4);
544
545 ////////////////////////////////////////////////////////////////
546 printf("LDNP,STNP (immediate, simm7) (FP&VEC, w/ nontemporal hint)\n");
547
548 MEM_TEST("stnp q18, q17, [x5, 16]", -15, 4);
549 MEM_TEST("stnp d20, d19, [x5, 40]", -15, 4);
550 MEM_TEST("stnp s19, s18, [x5, 68]", -15, 4);
551
552 MEM_TEST("ldnp q18, q17, [x5, 16]", -15, 4);
553 MEM_TEST("ldnp d17, d20, [x5, 40]", -15, 4);
554 MEM_TEST("ldnp s20, s19, [x5, 68]", -15, 4);
555
556 ////////////////////////////////////////////////////////////////
557 printf("{LD,ST}R (vector register)\n");
558
559 MEM_TEST("str q17, [x5, x6]", 12, -4);
560 MEM_TEST("str q17, [x5, x6, lsl #4]", 12, -4);
561 MEM_TEST("str q17, [x5, w6, uxtw]", 12, 4);
562 MEM_TEST("str q17, [x5, w6, uxtw #4]", 12, 4);
563 MEM_TEST("str q17, [x5, w6, sxtw]", 12, 4);
564 MEM_TEST("str q17, [x5, w6, sxtw #4]", 12, -4);
565 MEM_TEST("ldr q17, [x5, x6]", 12, -4);
566 MEM_TEST("ldr q17, [x5, x6, lsl #4]", 12, -4);
567 MEM_TEST("ldr q17, [x5, w6, uxtw]", 12, 4);
568 MEM_TEST("ldr q17, [x5, w6, uxtw #4]", 12, 4);
569 MEM_TEST("ldr q17, [x5, w6, sxtw]", 12, 4);
570 MEM_TEST("ldr q17, [x5, w6, sxtw #4]", 12, -4);
571
572 MEM_TEST("str d17, [x5, x6]", 12, -4);
573 MEM_TEST("str d17, [x5, x6, lsl #3]", 12, -4);
574 MEM_TEST("str d17, [x5, w6, uxtw]", 12, 4);
575 MEM_TEST("str d17, [x5, w6, uxtw #3]", 12, 4);
576 MEM_TEST("str d17, [x5, w6, sxtw]", 12, 4);
577 MEM_TEST("str d17, [x5, w6, sxtw #3]", 12, -4);
578 MEM_TEST("ldr d17, [x5, x6]", 12, -4);
579 MEM_TEST("ldr d17, [x5, x6, lsl #3]", 12, -4);
580 MEM_TEST("ldr d17, [x5, w6, uxtw]", 12, 4);
581 MEM_TEST("ldr d17, [x5, w6, uxtw #3]", 12, 4);
582 MEM_TEST("ldr d17, [x5, w6, sxtw]", 12, 4);
583 MEM_TEST("ldr d17, [x5, w6, sxtw #3]", 12, -4);
584
585 MEM_TEST("str s17, [x5, x6]", 12, -4);
586 MEM_TEST("str s17, [x5, x6, lsl #2]", 12, -4);
587 MEM_TEST("str s17, [x5, w6, uxtw]", 12, 4);
588 MEM_TEST("str s17, [x5, w6, uxtw #2]", 12, 4);
589 MEM_TEST("str s17, [x5, w6, sxtw]", 12, 4);
590 MEM_TEST("str s17, [x5, w6, sxtw #2]", 12, -4);
591 MEM_TEST("ldr s17, [x5, x6]", 12, -4);
592 MEM_TEST("ldr s17, [x5, x6, lsl #2]", 12, -4);
593 MEM_TEST("ldr s17, [x5, w6, uxtw]", 12, 4);
594 MEM_TEST("ldr s17, [x5, w6, uxtw #2]", 12, 4);
595 MEM_TEST("ldr s17, [x5, w6, sxtw]", 12, 4);
596 MEM_TEST("ldr s17, [x5, w6, sxtw #2]", 12, -4);
597
598 MEM_TEST("str h17, [x5, x6]", 12, -4);
599 MEM_TEST("str h17, [x5, x6, lsl #1]", 12, -4);
600 MEM_TEST("str h17, [x5, w6, uxtw]", 12, 4);
601 MEM_TEST("str h17, [x5, w6, uxtw #1]", 12, 4);
602 MEM_TEST("str h17, [x5, w6, sxtw]", 12, 4);
603 MEM_TEST("str h17, [x5, w6, sxtw #1]", 12, -4);
604 MEM_TEST("ldr h17, [x5, x6]", 12, -4);
605 MEM_TEST("ldr h17, [x5, x6, lsl #1]", 12, -4);
606 MEM_TEST("ldr h17, [x5, w6, uxtw]", 12, 4);
607 MEM_TEST("ldr h17, [x5, w6, uxtw #1]", 12, 4);
608 MEM_TEST("ldr h17, [x5, w6, sxtw]", 12, 4);
609 MEM_TEST("ldr h17, [x5, w6, sxtw #1]", 12, -4);
610
611 MEM_TEST("str b17, [x5, x6]", 12, -4);
612 MEM_TEST("str b17, [x5, x6, lsl #0]", 12, -4);
613 MEM_TEST("str b17, [x5, w6, uxtw]", 12, 4);
614 MEM_TEST("str b17, [x5, w6, uxtw #0]", 12, 4);
615 MEM_TEST("str b17, [x5, w6, sxtw]", 12, 4);
616 MEM_TEST("str b17, [x5, w6, sxtw #0]", 12, -4);
617 MEM_TEST("ldr b17, [x5, x6]", 12, -4);
618 MEM_TEST("ldr b17, [x5, x6, lsl #0]", 12, -4);
619 MEM_TEST("ldr b17, [x5, w6, uxtw]", 12, 4);
620 MEM_TEST("ldr b17, [x5, w6, uxtw #0]", 12, 4);
621 MEM_TEST("ldr b17, [x5, w6, sxtw]", 12, 4);
622 MEM_TEST("ldr b17, [x5, w6, sxtw #0]", 12, -4);
623
624 ////////////////////////////////////////////////////////////////
625 printf("LDRS{B,H,W} (integer register, SX)\n");
626
627 MEM_TEST("ldrsw x13, [x5,x6]", 12, -4);
628 MEM_TEST("ldrsw x13, [x5,x6, lsl #2]", 12, -4);
629 MEM_TEST("ldrsw x13, [x5,w6,uxtw #0]", 12, 4);
630 MEM_TEST("ldrsw x13, [x5,w6,uxtw #2]", 12, 4);
631 MEM_TEST("ldrsw x13, [x5,w6,sxtw #0]", 12, 4);
632 MEM_TEST("ldrsw x13, [x5,w6,sxtw #2]", 12, -4);
633
634 MEM_TEST("ldrsh x13, [x5,x6]", 12, -4);
635 MEM_TEST("ldrsh x13, [x5,x6, lsl #1]", 12, -4);
636 MEM_TEST("ldrsh x13, [x5,w6,uxtw #0]", 12, 4);
637 MEM_TEST("ldrsh x13, [x5,w6,uxtw #1]", 12, 4);
638 MEM_TEST("ldrsh x13, [x5,w6,sxtw #0]", 12, 4);
639 MEM_TEST("ldrsh x13, [x5,w6,sxtw #1]", 12, -4);
640
641 MEM_TEST("ldrsh w13, [x5,x6]", 12, -4);
642 MEM_TEST("ldrsh w13, [x5,x6, lsl #1]", 12, -4);
643 MEM_TEST("ldrsh w13, [x5,w6,uxtw #0]", 12, 4);
644 MEM_TEST("ldrsh w13, [x5,w6,uxtw #1]", 12, 4);
645 MEM_TEST("ldrsh w13, [x5,w6,sxtw #0]", 12, 4);
646 MEM_TEST("ldrsh w13, [x5,w6,sxtw #1]", 12, -4);
647
648 MEM_TEST("ldrsb x13, [x5,x6]", 12, -4);
649 MEM_TEST("ldrsb x13, [x5,x6, lsl #0]", 12, -4);
650 MEM_TEST("ldrsb x13, [x5,w6,uxtw #0]", 12, 4);
651 MEM_TEST("ldrsb x13, [x5,w6,uxtw #0]", 12, 4);
652 MEM_TEST("ldrsb x13, [x5,w6,sxtw #0]", 12, 4);
653 MEM_TEST("ldrsb x13, [x5,w6,sxtw #0]", 12, -4);
654
655 MEM_TEST("ldrsb w13, [x5,x6]", 12, -4);
656 MEM_TEST("ldrsb w13, [x5,x6, lsl #0]", 12, -4);
657 MEM_TEST("ldrsb w13, [x5,w6,uxtw #0]", 12, 4);
658 MEM_TEST("ldrsb w13, [x5,w6,uxtw #0]", 12, 4);
659 MEM_TEST("ldrsb w13, [x5,w6,sxtw #0]", 12, 4);
660 MEM_TEST("ldrsb w13, [x5,w6,sxtw #0]", 12, -4);
661
662 ////////////////////////////////////////////////////////////////
663 printf("LDR/STR (immediate, SIMD&FP, unsigned offset)\n");
664
665 MEM_TEST("str q17, [x5, #-32]", 16, 0);
666 MEM_TEST("str d17, [x5, #-32]", 16, 0);
667 MEM_TEST("str s17, [x5, #-32]", 16, 0);
668 MEM_TEST("str h17, [x5, #-32]", 16, 0);
669 MEM_TEST("str b17, [x5, #-32]", 16, 0);
670 MEM_TEST("ldr q17, [x5, #-32]", 16, 0);
671 MEM_TEST("ldr d17, [x5, #-32]", 16, 0);
672 MEM_TEST("ldr s17, [x5, #-32]", 16, 0);
673 MEM_TEST("ldr h17, [x5, #-32]", 16, 0);
674 MEM_TEST("ldr b17, [x5, #-32]", 16, 0);
675
676 ////////////////////////////////////////////////////////////////
677 printf("LDR/STR (immediate, SIMD&FP, pre/post index)\n");
678
679 MEM_TEST("str q17, [x5], #-32", 16, 0);
680 MEM_TEST("str d17, [x5], #-32", 16, 0);
681 MEM_TEST("str s17, [x5], #-32", 16, 0);
682 MEM_TEST("str h17, [x5], #-32", 16, 0);
683 MEM_TEST("str b17, [x5], #-32", 16, 0);
684 MEM_TEST("ldr q17, [x5], #-32", 16, 0);
685 MEM_TEST("ldr d17, [x5], #-32", 16, 0);
686 MEM_TEST("ldr s17, [x5], #-32", 16, 0);
687 MEM_TEST("ldr h17, [x5], #-32", 16, 0);
688 MEM_TEST("ldr b17, [x5], #-32", 16, 0);
689
690 MEM_TEST("str q17, [x5, #-32]!", 16, 0);
691 MEM_TEST("str d17, [x5, #-32]!", 16, 0);
692 MEM_TEST("str s17, [x5, #-32]!", 16, 0);
693 MEM_TEST("str h17, [x5, #-32]!", 16, 0);
694 MEM_TEST("str b17, [x5, #-32]!", 16, 0);
695 MEM_TEST("ldr q17, [x5, #-32]!", 16, 0);
696 MEM_TEST("ldr d17, [x5, #-32]!", 16, 0);
697 MEM_TEST("ldr s17, [x5, #-32]!", 16, 0);
698 MEM_TEST("ldr h17, [x5, #-32]!", 16, 0);
699 MEM_TEST("ldr b17, [x5, #-32]!", 16, 0);
700
701 ////////////////////////////////////////////////////////////////
702 printf("LDUR/STUR (unscaled offset, SIMD&FP)\n");
703
704 MEM_TEST("str q17, [x5, #-13]", 16, 0);
705 MEM_TEST("str d17, [x5, #-13]", 16, 0);
706 MEM_TEST("str s17, [x5, #-13]", 16, 0);
707 MEM_TEST("str h17, [x5, #-13]", 16, 0);
708 MEM_TEST("str b17, [x5, #-13]", 16, 0);
709 MEM_TEST("ldr q17, [x5, #-13]", 16, 0);
710 MEM_TEST("ldr d17, [x5, #-13]", 16, 0);
711 MEM_TEST("ldr s17, [x5, #-13]", 16, 0);
712 MEM_TEST("ldr h17, [x5, #-13]", 16, 0);
713 MEM_TEST("ldr b17, [x5, #-13]", 16, 0);
714
715 ////////////////////////////////////////////////////////////////
716 printf("LDR (literal, SIMD&FP) (entirely MISSING)\n");
717
718 MEM_TEST("xyzzy10: ldr s17, xyzzy10 - 8", 0, 0)
719 MEM_TEST("xyzzy11: ldr d17, xyzzy11 + 8", 0, 0)
720 MEM_TEST("xyzzy12: ldr q17, xyzzy12 + 4", 0, 0)
721
722 ////////////////////////////////////////////////////////////////
723 printf("LD1/ST1 (multiple 1-elem structs to/from 1 reg\n");
724
725 MEM_TEST("st1 {v18.2d}, [x5]", 17, 7)
726 MEM_TEST("st1 {v18.2d}, [x5], #16", 9, 9)
727 MEM_TEST("st1 {v18.2d}, [x5], x6", -13, -5)
728
729 MEM_TEST("st1 {v18.1d}, [x5]", 17, 7)
730 MEM_TEST("st1 {v18.1d}, [x5], #8", 9, 9)
731 MEM_TEST("st1 {v18.1d}, [x5], x6", -13, -5)
732
733 MEM_TEST("st1 {v18.4s}, [x5]", 17, 7)
734 MEM_TEST("st1 {v18.4s}, [x5], #16", 9, 9)
735 MEM_TEST("st1 {v18.4s}, [x5], x6", -13, -5)
736
737 MEM_TEST("st1 {v18.2s}, [x5]", 17, 7)
738 MEM_TEST("st1 {v18.2s}, [x5], #8", 9, 9)
739 MEM_TEST("st1 {v18.2s}, [x5], x6", -13, -5)
740
741 MEM_TEST("st1 {v18.8h}, [x5]", 17, 7)
742 MEM_TEST("st1 {v18.8h}, [x5], #16", 9, 9)
743 MEM_TEST("st1 {v18.8h}, [x5], x6", -13, -5)
744
745 MEM_TEST("st1 {v18.4h}, [x5]", 17, 7)
746 MEM_TEST("st1 {v18.4h}, [x5], #8", 9, 9)
747 MEM_TEST("st1 {v18.4h}, [x5], x6", -13, -5)
748
749 MEM_TEST("st1 {v18.16b}, [x5]", 17, 7)
750 MEM_TEST("st1 {v18.16b}, [x5], #16", 9, 9)
751 MEM_TEST("st1 {v18.16b}, [x5], x6", -13, -5)
752
753 MEM_TEST("st1 {v18.8b}, [x5]", 17, 7)
754 MEM_TEST("st1 {v18.8b}, [x5], #8", 9, 9)
755 MEM_TEST("st1 {v18.8b}, [x5], x6", -13, -5)
756
757 MEM_TEST("ld1 {v18.2d}, [x5]", 17, 7)
758 MEM_TEST("ld1 {v18.2d}, [x5], #16", 9, 9)
759 MEM_TEST("ld1 {v18.2d}, [x5], x6", -13, -5)
760
761 MEM_TEST("ld1 {v18.1d}, [x5]", 17, 7)
762 MEM_TEST("ld1 {v18.1d}, [x5], #8", 9, 9)
763 MEM_TEST("ld1 {v18.1d}, [x5], x6", -13, -5)
764
765 MEM_TEST("ld1 {v18.4s}, [x5]", 17, 7)
766 MEM_TEST("ld1 {v18.4s}, [x5], #16", 9, 9)
767 MEM_TEST("ld1 {v18.4s}, [x5], x6", -13, -5)
768
769 MEM_TEST("ld1 {v18.2s}, [x5]", 17, 7)
770 MEM_TEST("ld1 {v18.2s}, [x5], #8", 9, 9)
771 MEM_TEST("ld1 {v18.2s}, [x5], x6", -13, -5)
772
773 MEM_TEST("ld1 {v18.8h}, [x5]", 17, 7)
774 MEM_TEST("ld1 {v18.8h}, [x5], #16", 9, 9)
775 MEM_TEST("ld1 {v18.8h}, [x5], x6", -13, -5)
776
777 MEM_TEST("ld1 {v18.4h}, [x5]", 17, 7)
778 MEM_TEST("ld1 {v18.4h}, [x5], #8", 9, 9)
779 MEM_TEST("ld1 {v18.4h}, [x5], x6", -13, -5)
780
781 MEM_TEST("ld1 {v18.16b}, [x5]", 17, 7)
782 MEM_TEST("ld1 {v18.16b}, [x5], #16", 9, 9)
783 MEM_TEST("ld1 {v18.16b}, [x5], x6", -13, -5)
784
785 MEM_TEST("ld1 {v18.8b}, [x5]", 17, 7)
786 MEM_TEST("ld1 {v18.8b}, [x5], #8", 9, 9)
787 MEM_TEST("ld1 {v18.8b}, [x5], x6", -13, -5)
788
789 ////////////////////////////////////////////////////////////////
790 printf("LD2/ST2 (multiple 2-elem structs to/from 2 regs\n");
791
792 MEM_TEST("st2 {v18.2d, v19.2d}, [x5]", 17, 7)
793 MEM_TEST("st2 {v18.2d, v19.2d}, [x5], #32", 9, 9)
794 MEM_TEST("st2 {v18.2d, v19.2d}, [x5], x6", -13, -5)
795
796 /* no 1d case */
797
798 MEM_TEST("st2 {v18.4s, v19.4s}, [x5]", 17, 7)
799 MEM_TEST("st2 {v18.4s, v19.4s}, [x5], #32", 9, 9)
800 MEM_TEST("st2 {v18.4s, v19.4s}, [x5], x6", -13, -5)
801
802 MEM_TEST("st2 {v18.2s, v19.2s}, [x5]", 17, 7)
803 MEM_TEST("st2 {v18.2s, v19.2s}, [x5], #16", 9, 9)
804 MEM_TEST("st2 {v18.2s, v19.2s}, [x5], x6", -13, -5)
805
806 MEM_TEST("st2 {v18.8h, v19.8h}, [x5]", 17, 7)
807 MEM_TEST("st2 {v18.8h, v19.8h}, [x5], #32", 9, 9)
808 MEM_TEST("st2 {v18.8h, v19.8h}, [x5], x6", -13, -5)
809
810 MEM_TEST("st2 {v18.4h, v19.4h}, [x5]", 17, 7)
811 MEM_TEST("st2 {v18.4h, v19.4h}, [x5], #16", 9, 9)
812 MEM_TEST("st2 {v18.4h, v19.4h}, [x5], x6", -13, -5)
813
814 MEM_TEST("st2 {v18.16b, v19.16b}, [x5]", 17, 7)
815 MEM_TEST("st2 {v18.16b, v19.16b}, [x5], #32", 9, 9)
816 MEM_TEST("st2 {v18.16b, v19.16b}, [x5], x6", -13, -5)
817
818 MEM_TEST("st2 {v18.8b, v19.8b}, [x5]", 17, 7)
819 MEM_TEST("st2 {v18.8b, v19.8b}, [x5], #16", 9, 9)
820 MEM_TEST("st2 {v18.8b, v19.8b}, [x5], x6", -13, -5)
821
822 MEM_TEST("ld2 {v18.2d, v19.2d}, [x5]", 17, 7)
823 MEM_TEST("ld2 {v18.2d, v19.2d}, [x5], #32", 9, 9)
824 MEM_TEST("ld2 {v18.2d, v19.2d}, [x5], x6", -13, -5)
825
826 /* no 1d case */
827
828 MEM_TEST("ld2 {v18.4s, v19.4s}, [x5]", 17, 7)
829 MEM_TEST("ld2 {v18.4s, v19.4s}, [x5], #32", 9, 9)
830 MEM_TEST("ld2 {v18.4s, v19.4s}, [x5], x6", -13, -5)
831
832 MEM_TEST("ld2 {v18.2s, v19.2s}, [x5]", 17, 7)
833 MEM_TEST("ld2 {v18.2s, v19.2s}, [x5], #16", 9, 9)
834 MEM_TEST("ld2 {v18.2s, v19.2s}, [x5], x6", -13, -5)
835
836 MEM_TEST("ld2 {v18.8h, v19.8h}, [x5]", 17, 7)
837 MEM_TEST("ld2 {v18.8h, v19.8h}, [x5], #32", 9, 9)
838 MEM_TEST("ld2 {v18.8h, v19.8h}, [x5], x6", -13, -5)
839
840 MEM_TEST("ld2 {v18.4h, v19.4h}, [x5]", 17, 7)
841 MEM_TEST("ld2 {v18.4h, v19.4h}, [x5], #16", 9, 9)
842 MEM_TEST("ld2 {v18.4h, v19.4h}, [x5], x6", -13, -5)
843
844 MEM_TEST("ld2 {v18.16b, v19.16b}, [x5]", 17, 7)
845 MEM_TEST("ld2 {v18.16b, v19.16b}, [x5], #32", 9, 9)
846 MEM_TEST("ld2 {v18.16b, v19.16b}, [x5], x6", -13, -5)
847
848 MEM_TEST("ld2 {v18.8b, v19.8b}, [x5]", 17, 7)
849 MEM_TEST("ld2 {v18.8b, v19.8b}, [x5], #16", 9, 9)
850 MEM_TEST("ld2 {v18.8b, v19.8b}, [x5], x6", -13, -5)
851
852 ////////////////////////////////////////////////////////////////
853 printf("LD3/ST3 (multiple 3-elem structs to/from 3 regs\n");
854
855 MEM_TEST("st3 {v17.2d, v18.2d, v19.2d}, [x5]", 17, 7)
856 MEM_TEST("st3 {v17.2d, v18.2d, v19.2d}, [x5], #48", 9, 9)
857 MEM_TEST("st3 {v17.2d, v18.2d, v19.2d}, [x5], x6", -13, -5)
858
859 /* no 1d case */
860
861 MEM_TEST("st3 {v17.4s, v18.4s, v19.4s}, [x5]", 17, 7)
862 MEM_TEST("st3 {v17.4s, v18.4s, v19.4s}, [x5], #48", 9, 9)
863 MEM_TEST("st3 {v17.4s, v18.4s, v19.4s}, [x5], x6", -13, -5)
864
865 MEM_TEST("st3 {v17.2s, v18.2s, v19.2s}, [x5]", 17, 7)
866 MEM_TEST("st3 {v17.2s, v18.2s, v19.2s}, [x5], #24", 9, 9)
867 MEM_TEST("st3 {v17.2s, v18.2s, v19.2s}, [x5], x6", -13, -5)
868
869 MEM_TEST("st3 {v17.8h, v18.8h, v19.8h}, [x5]", 17, 7)
870 MEM_TEST("st3 {v17.8h, v18.8h, v19.8h}, [x5], #48", 9, 9)
871 MEM_TEST("st3 {v17.8h, v18.8h, v19.8h}, [x5], x6", -13, -5)
872
873 MEM_TEST("st3 {v17.4h, v18.4h, v19.4h}, [x5]", 17, 7)
874 MEM_TEST("st3 {v17.4h, v18.4h, v19.4h}, [x5], #24", 9, 9)
875 MEM_TEST("st3 {v17.4h, v18.4h, v19.4h}, [x5], x6", -13, -5)
876
877 MEM_TEST("st3 {v17.16b, v18.16b, v19.16b}, [x5]", 17, 7)
878 MEM_TEST("st3 {v17.16b, v18.16b, v19.16b}, [x5], #48", 9, 9)
879 MEM_TEST("st3 {v17.16b, v18.16b, v19.16b}, [x5], x6", -13, -5)
880
881 MEM_TEST("st3 {v17.8b, v18.8b, v19.8b}, [x5]", 17, 7)
882 MEM_TEST("st3 {v17.8b, v18.8b, v19.8b}, [x5], #24", 9, 9)
883 MEM_TEST("st3 {v17.8b, v18.8b, v19.8b}, [x5], x6", -13, -5)
884
885 MEM_TEST("ld3 {v17.2d, v18.2d, v19.2d}, [x5]", 17, 7)
886 MEM_TEST("ld3 {v17.2d, v18.2d, v19.2d}, [x5], #48", 9, 9)
887 MEM_TEST("ld3 {v17.2d, v18.2d, v19.2d}, [x5], x6", -13, -5)
888
889 /* no 1d case */
890
891 MEM_TEST("ld3 {v17.4s, v18.4s, v19.4s}, [x5]", 17, 7)
892 MEM_TEST("ld3 {v17.4s, v18.4s, v19.4s}, [x5], #48", 9, 9)
893 MEM_TEST("ld3 {v17.4s, v18.4s, v19.4s}, [x5], x6", -13, -5)
894
895 MEM_TEST("ld3 {v17.2s, v18.2s, v19.2s}, [x5]", 17, 7)
896 MEM_TEST("ld3 {v17.2s, v18.2s, v19.2s}, [x5], #24", 9, 9)
897 MEM_TEST("ld3 {v17.2s, v18.2s, v19.2s}, [x5], x6", -13, -5)
898
899 MEM_TEST("ld3 {v17.8h, v18.8h, v19.8h}, [x5]", 17, 7)
900 MEM_TEST("ld3 {v17.8h, v18.8h, v19.8h}, [x5], #48", 9, 9)
901 MEM_TEST("ld3 {v17.8h, v18.8h, v19.8h}, [x5], x6", -13, -5)
902
903 MEM_TEST("ld3 {v17.4h, v18.4h, v19.4h}, [x5]", 17, 7)
904 MEM_TEST("ld3 {v17.4h, v18.4h, v19.4h}, [x5], #24", 9, 9)
905 MEM_TEST("ld3 {v17.4h, v18.4h, v19.4h}, [x5], x6", -13, -5)
906
907 MEM_TEST("ld3 {v17.16b, v18.16b, v19.16b}, [x5]", 17, 7)
908 MEM_TEST("ld3 {v17.16b, v18.16b, v19.16b}, [x5], #48", 9, 9)
909 MEM_TEST("ld3 {v17.16b, v18.16b, v19.16b}, [x5], x6", -13, -5)
910
911 MEM_TEST("ld3 {v17.8b, v18.8b, v19.8b}, [x5]", 17, 7)
912 MEM_TEST("ld3 {v17.8b, v18.8b, v19.8b}, [x5], #24", 9, 9)
913 MEM_TEST("ld3 {v17.8b, v18.8b, v19.8b}, [x5], x6", -13, -5)
914
915 ////////////////////////////////////////////////////////////////
916 printf("LD4/ST4 (multiple 4-elem structs to/from 4 regs\n");
917
918 MEM_TEST("st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]", 17, 7)
919 MEM_TEST("st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64", 9, 9)
920 MEM_TEST("st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6", -13, -5)
921
922 /* no 1d case */
923
924 MEM_TEST("st4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]", 17, 7)
925 MEM_TEST("st4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64", 9, 9)
926 MEM_TEST("st4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6", -13, -5)
927
928 MEM_TEST("st4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]", 17, 7)
929 MEM_TEST("st4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32", 9, 9)
930 MEM_TEST("st4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6", -13, -5)
931
932 MEM_TEST("st4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]", 17, 7)
933 MEM_TEST("st4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64", 9, 9)
934 MEM_TEST("st4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6", -13, -5)
935
936 MEM_TEST("st4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]", 17, 7)
937 MEM_TEST("st4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32", 9, 9)
938 MEM_TEST("st4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6", -13, -5)
939
940 MEM_TEST("st4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
941 MEM_TEST("st4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
942 MEM_TEST("st4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
943
944 MEM_TEST("st4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]", 17, 7)
945 MEM_TEST("st4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32", 9, 9)
946 MEM_TEST("st4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6", -13, -5)
947
948 MEM_TEST("ld4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]", 17, 7)
949 MEM_TEST("ld4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64", 9, 9)
950 MEM_TEST("ld4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6", -13, -5)
951
952 /* no 1d case */
953
954 MEM_TEST("ld4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]", 17, 7)
955 MEM_TEST("ld4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64", 9, 9)
956 MEM_TEST("ld4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6", -13, -5)
957
958 MEM_TEST("ld4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]", 17, 7)
959 MEM_TEST("ld4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32", 9, 9)
960 MEM_TEST("ld4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6", -13, -5)
961
962 MEM_TEST("ld4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]", 17, 7)
963 MEM_TEST("ld4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64", 9, 9)
964 MEM_TEST("ld4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6", -13, -5)
965
966 MEM_TEST("ld4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]", 17, 7)
967 MEM_TEST("ld4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32", 9, 9)
968 MEM_TEST("ld4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6", -13, -5)
969
970 MEM_TEST("ld4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
971 MEM_TEST("ld4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
972 MEM_TEST("ld4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
973
974 MEM_TEST("ld4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]", 17, 7)
975 MEM_TEST("ld4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32", 9, 9)
976 MEM_TEST("ld4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6", -13, -5)
977
978 ////////////////////////////////////////////////////////////////
979 printf("LD1/ST1 (multiple 1-elem structs to/from 2/3/4 regs\n");
980
981 MEM_TEST("st1 {v19.2d, v20.2d}, [x5]", 17, 7)
982 MEM_TEST("st1 {v19.2d, v20.2d}, [x5], #32", 9, 9)
983 MEM_TEST("st1 {v19.2d, v20.2d}, [x5], x6", -13, -5)
984
985 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d}, [x5]", 17, 7)
986 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d}, [x5], #48", 9, 9)
987 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d}, [x5], x6", -13, -5)
988
989 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]", 17, 7)
990 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64", 9, 9)
991 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6", -13, -5)
992
993
994 MEM_TEST("st1 {v19.1d, v20.1d}, [x5]", 17, 7)
995 MEM_TEST("st1 {v19.1d, v20.1d}, [x5], #16", 9, 9)
996 MEM_TEST("st1 {v19.1d, v20.1d}, [x5], x6", -13, -5)
997
998 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d}, [x5]", 17, 7)
999 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d}, [x5], #24", 9, 9)
1000 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d}, [x5], x6", -13, -5)
1001
1002 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5]", 17, 7)
1003 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], #32", 9, 9)
1004 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], x6", -13, -5)
1005
1006
1007 MEM_TEST("st1 {v19.4s, v20.4s}, [x5]", 17, 7)
1008 MEM_TEST("st1 {v19.4s, v20.4s}, [x5], #32", 9, 9)
1009 MEM_TEST("st1 {v19.4s, v20.4s}, [x5], x6", -13, -5)
1010
1011 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s}, [x5]", 17, 7)
1012 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s}, [x5], #48", 9, 9)
1013 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s}, [x5], x6", -13, -5)
1014
1015 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]", 17, 7)
1016 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64", 9, 9)
1017 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6", -13, -5)
1018
1019
1020 MEM_TEST("st1 {v19.2s, v20.2s}, [x5]", 17, 7)
1021 MEM_TEST("st1 {v19.2s, v20.2s}, [x5], #16", 9, 9)
1022 MEM_TEST("st1 {v19.2s, v20.2s}, [x5], x6", -13, -5)
1023
1024 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s}, [x5]", 17, 7)
1025 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s}, [x5], #24", 9, 9)
1026 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s}, [x5], x6", -13, -5)
1027
1028 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]", 17, 7)
1029 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32", 9, 9)
1030 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6", -13, -5)
1031
1032
1033 MEM_TEST("st1 {v19.8h, v20.8h}, [x5]", 17, 7)
1034 MEM_TEST("st1 {v19.8h, v20.8h}, [x5], #32", 9, 9)
1035 MEM_TEST("st1 {v19.8h, v20.8h}, [x5], x6", -13, -5)
1036
1037 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h}, [x5]", 17, 7)
1038 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h}, [x5], #48", 9, 9)
1039 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h}, [x5], x6", -13, -5)
1040
1041 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]", 17, 7)
1042 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64", 9, 9)
1043 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6", -13, -5)
1044
1045
1046 MEM_TEST("st1 {v19.4h, v20.4h}, [x5]", 17, 7)
1047 MEM_TEST("st1 {v19.4h, v20.4h}, [x5], #16", 9, 9)
1048 MEM_TEST("st1 {v19.4h, v20.4h}, [x5], x6", -13, -5)
1049
1050 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h}, [x5]", 17, 7)
1051 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h}, [x5], #24", 9, 9)
1052 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h}, [x5], x6", -13, -5)
1053
1054 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]", 17, 7)
1055 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32", 9, 9)
1056 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6", -13, -5)
1057
1058
1059 MEM_TEST("st1 {v19.16b, v20.16b}, [x5]", 17, 7)
1060 MEM_TEST("st1 {v19.16b, v20.16b}, [x5], #32", 9, 9)
1061 MEM_TEST("st1 {v19.16b, v20.16b}, [x5], x6", -13, -5)
1062
1063 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b}, [x5]", 17, 7)
1064 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b}, [x5], #48", 9, 9)
1065 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b}, [x5], x6", -13, -5)
1066
1067 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
1068 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
1069 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
1070
1071
1072 MEM_TEST("st1 {v19.8b, v20.8b}, [x5]", 17, 7)
1073 MEM_TEST("st1 {v19.8b, v20.8b}, [x5], #16", 9, 9)
1074 MEM_TEST("st1 {v19.8b, v20.8b}, [x5], x6", -13, -5)
1075
1076 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b}, [x5]", 17, 7)
1077 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b}, [x5], #24", 9, 9)
1078 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b}, [x5], x6", -13, -5)
1079
1080 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]", 17, 7)
1081 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32", 9, 9)
1082 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6", -13, -5)
1083
1084
1085 MEM_TEST("ld1 {v19.2d, v20.2d}, [x5]", 17, 7)
1086 MEM_TEST("ld1 {v19.2d, v20.2d}, [x5], #32", 9, 9)
1087 MEM_TEST("ld1 {v19.2d, v20.2d}, [x5], x6", -13, -5)
1088
1089 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d}, [x5]", 17, 7)
1090 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d}, [x5], #48", 9, 9)
1091 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d}, [x5], x6", -13, -5)
1092
1093 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]", 17, 7)
1094 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64", 9, 9)
1095 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6", -13, -5)
1096
1097
1098 MEM_TEST("ld1 {v19.1d, v20.1d}, [x5]", 17, 7)
1099 MEM_TEST("ld1 {v19.1d, v20.1d}, [x5], #16", 9, 9)
1100 MEM_TEST("ld1 {v19.1d, v20.1d}, [x5], x6", -13, -5)
1101
1102 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d}, [x5]", 17, 7)
1103 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d}, [x5], #24", 9, 9)
1104 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d}, [x5], x6", -13, -5)
1105
1106 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5]", 17, 7)
1107 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], #32", 9, 9)
1108 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], x6", -13, -5)
1109
1110
1111 MEM_TEST("ld1 {v19.4s, v20.4s}, [x5]", 17, 7)
1112 MEM_TEST("ld1 {v19.4s, v20.4s}, [x5], #32", 9, 9)
1113 MEM_TEST("ld1 {v19.4s, v20.4s}, [x5], x6", -13, -5)
1114
1115 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s}, [x5]", 17, 7)
1116 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s}, [x5], #48", 9, 9)
1117 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s}, [x5], x6", -13, -5)
1118
1119 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]", 17, 7)
1120 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64", 9, 9)
1121 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6", -13, -5)
1122
1123
1124 MEM_TEST("ld1 {v19.2s, v20.2s}, [x5]", 17, 7)
1125 MEM_TEST("ld1 {v19.2s, v20.2s}, [x5], #16", 9, 9)
1126 MEM_TEST("ld1 {v19.2s, v20.2s}, [x5], x6", -13, -5)
1127
1128 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s}, [x5]", 17, 7)
1129 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s}, [x5], #24", 9, 9)
1130 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s}, [x5], x6", -13, -5)
1131
1132 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]", 17, 7)
1133 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32", 9, 9)
1134 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6", -13, -5)
1135
1136
1137 MEM_TEST("ld1 {v19.8h, v20.8h}, [x5]", 17, 7)
1138 MEM_TEST("ld1 {v19.8h, v20.8h}, [x5], #32", 9, 9)
1139 MEM_TEST("ld1 {v19.8h, v20.8h}, [x5], x6", -13, -5)
1140
1141 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h}, [x5]", 17, 7)
1142 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h}, [x5], #48", 9, 9)
1143 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h}, [x5], x6", -13, -5)
1144
1145 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]", 17, 7)
1146 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64", 9, 9)
1147 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6", -13, -5)
1148
1149
1150 MEM_TEST("ld1 {v19.4h, v20.4h}, [x5]", 17, 7)
1151 MEM_TEST("ld1 {v19.4h, v20.4h}, [x5], #16", 9, 9)
1152 MEM_TEST("ld1 {v19.4h, v20.4h}, [x5], x6", -13, -5)
1153
1154 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h}, [x5]", 17, 7)
1155 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h}, [x5], #24", 9, 9)
1156 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h}, [x5], x6", -13, -5)
1157
1158 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]", 17, 7)
1159 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32", 9, 9)
1160 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6", -13, -5)
1161
1162
1163 MEM_TEST("ld1 {v19.16b, v20.16b}, [x5]", 17, 7)
1164 MEM_TEST("ld1 {v19.16b, v20.16b}, [x5], #32", 9, 9)
1165 MEM_TEST("ld1 {v19.16b, v20.16b}, [x5], x6", -13, -5)
1166
1167 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b}, [x5]", 17, 7)
1168 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b}, [x5], #48", 9, 9)
1169 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b}, [x5], x6", -13, -5)
1170
1171 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
1172 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
1173 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
1174
1175
1176 MEM_TEST("ld1 {v19.8b, v20.8b}, [x5]", 17, 7)
1177 MEM_TEST("ld1 {v19.8b, v20.8b}, [x5], #16", 9, 9)
1178 MEM_TEST("ld1 {v19.8b, v20.8b}, [x5], x6", -13, -5)
1179
1180 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b}, [x5]", 17, 7)
1181 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b}, [x5], #24", 9, 9)
1182 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b}, [x5], x6", -13, -5)
1183
1184 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]", 17, 7)
1185 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32", 9, 9)
1186 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6", -13, -5)
1187
1188
1189 ////////////////////////////////////////////////////////////////
1190 printf("LD1R (single structure, replicate)\n");
1191
1192 MEM_TEST("ld1r {v17.2d}, [x5]", 3, -5)
1193 MEM_TEST("ld1r {v17.1d}, [x5]", 3, -4)
1194 MEM_TEST("ld1r {v17.4s}, [x5]", 3, -3)
1195 MEM_TEST("ld1r {v17.2s}, [x5]", 3, -2)
1196 MEM_TEST("ld1r {v17.8h}, [x5]", 3, -1)
1197 MEM_TEST("ld1r {v17.4h}, [x5]", 3, 1)
1198 MEM_TEST("ld1r {v17.16b}, [x5]", 3, 2)
1199 MEM_TEST("ld1r {v17.8b}, [x5]", 3, 3)
1200
1201 MEM_TEST("ld1r {v17.2d}, [x5], #8", 3, -5)
1202 MEM_TEST("ld1r {v17.1d}, [x5], #8", 3, -4)
1203 MEM_TEST("ld1r {v17.4s}, [x5], #4", 3, -3)
1204 MEM_TEST("ld1r {v17.2s}, [x5], #4", 3, -2)
1205 MEM_TEST("ld1r {v17.8h}, [x5], #2", 3, -1)
1206 MEM_TEST("ld1r {v17.4h}, [x5], #2", 3, 1)
1207 MEM_TEST("ld1r {v17.16b}, [x5], #1", 3, 2)
1208 MEM_TEST("ld1r {v17.8b}, [x5], #1", 3, 3)
1209
1210 MEM_TEST("ld1r {v17.2d}, [x5], x6", 3, -5)
1211 MEM_TEST("ld1r {v17.1d}, [x5], x6", 3, -4)
1212 MEM_TEST("ld1r {v17.4s}, [x5], x6", 3, -3)
1213 MEM_TEST("ld1r {v17.2s}, [x5], x6", 3, -2)
1214 MEM_TEST("ld1r {v17.8h}, [x5], x6", 3, -1)
1215 MEM_TEST("ld1r {v17.4h}, [x5], x6", 3, 1)
1216 MEM_TEST("ld1r {v17.16b}, [x5], x6", 3, 2)
1217 MEM_TEST("ld1r {v17.8b}, [x5], x6", 3, 3)
1218
1219
1220 ////////////////////////////////////////////////////////////////
1221 printf("LD2R (single structure, replicate)\n");
1222
1223 MEM_TEST("ld2r {v17.2d , v18.2d }, [x5]", 3, -5)
1224 MEM_TEST("ld2r {v18.1d , v19.1d }, [x5]", 3, -4)
1225 MEM_TEST("ld2r {v19.4s , v20.4s }, [x5]", 3, -3)
1226 MEM_TEST("ld2r {v17.2s , v18.2s }, [x5]", 3, -2)
1227 MEM_TEST("ld2r {v18.8h , v19.8h }, [x5]", 3, -1)
1228 MEM_TEST("ld2r {v19.4h , v20.4h }, [x5]", 3, 1)
1229 MEM_TEST("ld2r {v17.16b, v18.16b}, [x5]", 3, 2)
1230 MEM_TEST("ld2r {v18.8b , v19.8b }, [x5]", 3, 3)
1231
1232 MEM_TEST("ld2r {v19.2d , v20.2d }, [x5], #16", 3, -5)
1233 MEM_TEST("ld2r {v17.1d , v18.1d }, [x5], #16", 3, -4)
1234 MEM_TEST("ld2r {v18.4s , v19.4s }, [x5], #8", 3, -3)
1235 MEM_TEST("ld2r {v19.2s , v20.2s }, [x5], #8", 3, -2)
1236 MEM_TEST("ld2r {v17.8h , v18.8h }, [x5], #4", 3, -1)
1237 MEM_TEST("ld2r {v18.4h , v19.4h }, [x5], #4", 3, 1)
1238 MEM_TEST("ld2r {v19.16b, v20.16b}, [x5], #2", 3, 2)
1239 MEM_TEST("ld2r {v17.8b , v18.8b }, [x5], #2", 3, 3)
1240
1241 MEM_TEST("ld2r {v18.2d , v19.2d }, [x5], x6", 3, -5)
1242 MEM_TEST("ld2r {v19.1d , v20.1d }, [x5], x6", 3, -4)
1243 MEM_TEST("ld2r {v17.4s , v18.4s }, [x5], x6", 3, -3)
1244 MEM_TEST("ld2r {v18.2s , v19.2s }, [x5], x6", 3, -2)
1245 MEM_TEST("ld2r {v19.8h , v20.8h }, [x5], x6", 3, -1)
1246 MEM_TEST("ld2r {v17.4h , v18.4h }, [x5], x6", 3, 1)
1247 MEM_TEST("ld2r {v18.16b, v19.16b}, [x5], x6", 3, 2)
1248 MEM_TEST("ld2r {v19.8b , v20.8b }, [x5], x6", 3, 3)
1249
1250
1251 //////////////////////////////////////////////////////////////////
1252 printf("LD3R (single structure, replicate)\n");
1253
1254 MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d }, [x5]", 3, -5)
1255 MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d }, [x5]", 3, -4)
1256 MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s }, [x5]", 3, -3)
1257 MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s }, [x5]", 3, -2)
1258 MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h }, [x5]", 3, -5)
1259 MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h }, [x5]", 3, -4)
1260 MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b}, [x5]", 3, -3)
1261 MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b }, [x5]", 3, -2)
1262
1263 MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d }, [x5], #24", 3, -5)
1264 MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d }, [x5], #24", 3, -4)
1265 MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s }, [x5], #12", 3, -3)
1266 MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s }, [x5], #12", 3, -2)
1267 MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h }, [x5], #6", 3, -5)
1268 MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h }, [x5], #6", 3, -4)
1269 MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b}, [x5], #3", 3, -3)
1270 MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b }, [x5], #3", 3, -2)
1271
1272 MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d }, [x5], x6", 3, -5)
1273 MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d }, [x5], x6", 3, -4)
1274 MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s }, [x5], x6", 3, -3)
1275 MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s }, [x5], x6", 3, -2)
1276 MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h }, [x5], x6", 3, -5)
1277 MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h }, [x5], x6", 3, -4)
1278 MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b}, [x5], x6", 3, -3)
1279 MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b }, [x5], x6", 3, -2)
1280
1281
1282 ////////////////////////////////////////////////////////////////
1283 printf("LD4R (single structure, replicate)\n");
1284
1285 MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5]", 3, -5)
1286 MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5]", 3, -4)
1287 MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5]", 3, -3)
1288 MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5]", 3, -2)
1289 MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5]", 3, -5)
1290 MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5]", 3, -4)
1291 MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 3, -3)
1292 MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5]", 3, -2)
1293
1294 MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5], #32", 3, -5)
1295 MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5], #32", 3, -4)
1296 MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5], #16", 3, -3)
1297 MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5], #16", 3, -2)
1298 MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5], #8", 3, -5)
1299 MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5], #8", 3, -4)
1300 MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #4", 3, -3)
1301 MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5], #4", 3, -2)
1302
1303 MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5], x6", 3, -5)
1304 MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5], x6", 3, -4)
1305 MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5], x6", 3, -3)
1306 MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5], x6", 3, -2)
1307 MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5], x6", 3, -5)
1308 MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5], x6", 3, -4)
1309 MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", 3, -3)
1310 MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5], x6", 3, -2)
1311
1312
1313 ////////////////////////////////////////////////////////////////
1314 printf("LD1/ST1 (single 1-elem struct to/from one lane of 1 reg\n");
1315
1316 MEM_TEST("st1 {v19.d}[0], [x5]", 17, 7)
1317 MEM_TEST("st1 {v19.d}[0], [x5], #8", -9, 12)
1318 MEM_TEST("st1 {v19.d}[0], [x5], x6", 9, 13)
1319
1320 MEM_TEST("st1 {v19.d}[1], [x5]", 17, 7)
1321 MEM_TEST("st1 {v19.d}[1], [x5], #8", -9, 12)
1322 MEM_TEST("st1 {v19.d}[1], [x5], x6", 9, 13)
1323
1324 MEM_TEST("st1 {v19.s}[0], [x5]", 17, 7)
1325 MEM_TEST("st1 {v19.s}[0], [x5], #4", -9, 12)
1326 MEM_TEST("st1 {v19.s}[0], [x5], x6", 9, 13)
1327
1328 MEM_TEST("st1 {v19.s}[3], [x5]", 17, 7)
1329 MEM_TEST("st1 {v19.s}[3], [x5], #4", -9, 12)
1330 MEM_TEST("st1 {v19.s}[3], [x5], x6", 9, 13)
1331
1332 MEM_TEST("st1 {v19.h}[0], [x5]", 17, 7)
1333 MEM_TEST("st1 {v19.h}[0], [x5], #2", -9, 12)
1334 MEM_TEST("st1 {v19.h}[0], [x5], x6", 9, 13)
1335
1336 MEM_TEST("st1 {v19.h}[6], [x5]", 17, 7)
1337 MEM_TEST("st1 {v19.h}[6], [x5], #2", -9, 12)
1338 MEM_TEST("st1 {v19.h}[6], [x5], x6", 9, 13)
1339
1340 MEM_TEST("st1 {v19.b}[0], [x5]", 17, 7)
1341 MEM_TEST("st1 {v19.b}[0], [x5], #1", -9, 12)
1342 MEM_TEST("st1 {v19.b}[0], [x5], x6", 9, 13)
1343
1344 MEM_TEST("st1 {v19.b}[13], [x5]", 17, 7)
1345 MEM_TEST("st1 {v19.b}[13], [x5], #1", -9, 12)
1346 MEM_TEST("st1 {v19.b}[13], [x5], x6", 9, 13)
1347
1348
1349 MEM_TEST("ld1 {v19.d}[0], [x5]", 17, 7)
1350 MEM_TEST("ld1 {v19.d}[0], [x5], #8", -9, 12)
1351 MEM_TEST("ld1 {v19.d}[0], [x5], x6", 9, 13)
1352
1353 MEM_TEST("ld1 {v19.d}[1], [x5]", 17, 7)
1354 MEM_TEST("ld1 {v19.d}[1], [x5], #8", -9, 12)
1355 MEM_TEST("ld1 {v19.d}[1], [x5], x6", 9, 13)
1356
1357 MEM_TEST("ld1 {v19.s}[0], [x5]", 17, 7)
1358 MEM_TEST("ld1 {v19.s}[0], [x5], #4", -9, 12)
1359 MEM_TEST("ld1 {v19.s}[0], [x5], x6", 9, 13)
1360
1361 MEM_TEST("ld1 {v19.s}[3], [x5]", 17, 7)
1362 MEM_TEST("ld1 {v19.s}[3], [x5], #4", -9, 12)
1363 MEM_TEST("ld1 {v19.s}[3], [x5], x6", 9, 13)
1364
1365 MEM_TEST("ld1 {v19.h}[0], [x5]", 17, 7)
1366 MEM_TEST("ld1 {v19.h}[0], [x5], #2", -9, 12)
1367 MEM_TEST("ld1 {v19.h}[0], [x5], x6", 9, 13)
1368
1369 MEM_TEST("ld1 {v19.h}[6], [x5]", 17, 7)
1370 MEM_TEST("ld1 {v19.h}[6], [x5], #2", -9, 12)
1371 MEM_TEST("ld1 {v19.h}[6], [x5], x6", 9, 13)
1372
1373 MEM_TEST("ld1 {v19.b}[0], [x5]", 17, 7)
1374 MEM_TEST("ld1 {v19.b}[0], [x5], #1", -9, 12)
1375 MEM_TEST("ld1 {v19.b}[0], [x5], x6", 9, 13)
1376
1377 MEM_TEST("ld1 {v19.b}[13], [x5]", 17, 7)
1378 MEM_TEST("ld1 {v19.b}[13], [x5], #1", -9, 12)
1379 MEM_TEST("ld1 {v19.b}[13], [x5], x6", 9, 13)
1380
1381
1382 ////////////////////////////////////////////////////////////////
1383 printf("LD2/ST2 (single 2-elem struct to/from one lane of 2 regs\n");
1384
1385 MEM_TEST("st2 {v18.d, v19.d}[0], [x5]", 17, 7)
1386 MEM_TEST("st2 {v18.d, v19.d}[0], [x5], #16", -9, 12)
1387 MEM_TEST("st2 {v18.d, v19.d}[0], [x5], x6", 9, 13)
1388
1389 MEM_TEST("st2 {v18.d, v19.d}[1], [x5]", 17, 7)
1390 MEM_TEST("st2 {v18.d, v19.d}[1], [x5], #16", -9, 12)
1391 MEM_TEST("st2 {v18.d, v19.d}[1], [x5], x6", 9, 13)
1392
1393 MEM_TEST("st2 {v18.s, v19.s}[0], [x5]", 17, 7)
1394 MEM_TEST("st2 {v18.s, v19.s}[0], [x5], #8", -9, 12)
1395 MEM_TEST("st2 {v18.s, v19.s}[0], [x5], x6", 9, 13)
1396
1397 MEM_TEST("st2 {v18.s, v19.s}[3], [x5]", 17, 7)
1398 MEM_TEST("st2 {v18.s, v19.s}[3], [x5], #8", -9, 12)
1399 MEM_TEST("st2 {v18.s, v19.s}[3], [x5], x6", 9, 13)
1400
1401 MEM_TEST("st2 {v18.h, v19.h}[0], [x5]", 17, 7)
1402 MEM_TEST("st2 {v18.h, v19.h}[0], [x5], #4", -9, 12)
1403 MEM_TEST("st2 {v18.h, v19.h}[0], [x5], x6", 9, 13)
1404
1405 MEM_TEST("st2 {v18.h, v19.h}[6], [x5]", 17, 7)
1406 MEM_TEST("st2 {v18.h, v19.h}[6], [x5], #4", -9, 12)
1407 MEM_TEST("st2 {v18.h, v19.h}[6], [x5], x6", 9, 13)
1408
1409 MEM_TEST("st2 {v18.b, v19.b}[0], [x5]", 17, 7)
1410 MEM_TEST("st2 {v18.b, v19.b}[0], [x5], #2", -9, 12)
1411 MEM_TEST("st2 {v18.b, v19.b}[0], [x5], x6", 9, 13)
1412
1413 MEM_TEST("st2 {v18.b, v19.b}[13], [x5]", 17, 7)
1414 MEM_TEST("st2 {v18.b, v19.b}[13], [x5], #2", -9, 12)
1415 MEM_TEST("st2 {v18.b, v19.b}[13], [x5], x6", 9, 13)
1416
1417
1418 MEM_TEST("ld2 {v18.d, v19.d}[0], [x5]", 17, 7)
1419 MEM_TEST("ld2 {v18.d, v19.d}[0], [x5], #16", -9, 12)
1420 MEM_TEST("ld2 {v18.d, v19.d}[0], [x5], x6", 9, 13)
1421
1422 MEM_TEST("ld2 {v18.d, v19.d}[1], [x5]", 17, 7)
1423 MEM_TEST("ld2 {v18.d, v19.d}[1], [x5], #16", -9, 12)
1424 MEM_TEST("ld2 {v18.d, v19.d}[1], [x5], x6", 9, 13)
1425
1426 MEM_TEST("ld2 {v18.s, v19.s}[0], [x5]", 17, 7)
1427 MEM_TEST("ld2 {v18.s, v19.s}[0], [x5], #8", -9, 12)
1428 MEM_TEST("ld2 {v18.s, v19.s}[0], [x5], x6", 9, 13)
1429
1430 MEM_TEST("ld2 {v18.s, v19.s}[3], [x5]", 17, 7)
1431 MEM_TEST("ld2 {v18.s, v19.s}[3], [x5], #8", -9, 12)
1432 MEM_TEST("ld2 {v18.s, v19.s}[3], [x5], x6", 9, 13)
1433
1434 MEM_TEST("ld2 {v18.h, v19.h}[0], [x5]", 17, 7)
1435 MEM_TEST("ld2 {v18.h, v19.h}[0], [x5], #4", -9, 12)
1436 MEM_TEST("ld2 {v18.h, v19.h}[0], [x5], x6", 9, 13)
1437
1438 MEM_TEST("ld2 {v18.h, v19.h}[6], [x5]", 17, 7)
1439 MEM_TEST("ld2 {v18.h, v19.h}[6], [x5], #4", -9, 12)
1440 MEM_TEST("ld2 {v18.h, v19.h}[6], [x5], x6", 9, 13)
1441
1442 MEM_TEST("ld2 {v18.b, v19.b}[0], [x5]", 17, 7)
1443 MEM_TEST("ld2 {v18.b, v19.b}[0], [x5], #2", -9, 12)
1444 MEM_TEST("ld2 {v18.b, v19.b}[0], [x5], x6", 9, 13)
1445
1446 MEM_TEST("ld2 {v18.b, v19.b}[13], [x5]", 17, 7)
1447 MEM_TEST("ld2 {v18.b, v19.b}[13], [x5], #2", -9, 12)
1448 MEM_TEST("ld2 {v18.b, v19.b}[13], [x5], x6", 9, 13)
1449
1450
1451 ////////////////////////////////////////////////////////////////
1452 printf("LD3/ST3 (single 3-elem struct to/from one lane of 3 regs\n");
1453
1454 MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5]", 17, 7)
1455 MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5], #24", -9, 12)
1456 MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5], x6", 9, 13)
1457
1458 MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5]", 17, 7)
1459 MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5], #24", -9, 12)
1460 MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5], x6", 9, 13)
1461
1462 MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5]", 17, 7)
1463 MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5], #12", -9, 12)
1464 MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5], x6", 9, 13)
1465
1466 MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5]", 17, 7)
1467 MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5], #12", -9, 12)
1468 MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5], x6", 9, 13)
1469
1470 MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5]", 17, 7)
1471 MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5], #6", -9, 12)
1472 MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5], x6", 9, 13)
1473
1474 MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5]", 17, 7)
1475 MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5], #6", -9, 12)
1476 MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5], x6", 9, 13)
1477
1478 MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5]", 17, 7)
1479 MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5], #3", -9, 12)
1480 MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5], x6", 9, 13)
1481
1482 MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5]", 17, 7)
1483 MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5], #3", -9, 12)
1484 MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5], x6", 9, 13)
1485
1486
1487 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5]", 17, 7)
1488 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5], #24", -9, 12)
1489 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5], x6", 9, 13)
1490
1491 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5]", 17, 7)
1492 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5], #24", -9, 12)
1493 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5], x6", 9, 13)
1494
1495 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5]", 17, 7)
1496 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5], #12", -9, 12)
1497 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5], x6", 9, 13)
1498
1499 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5]", 17, 7)
1500 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5], #12", -9, 12)
1501 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5], x6", 9, 13)
1502
1503 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5]", 17, 7)
1504 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5], #6", -9, 12)
1505 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5], x6", 9, 13)
1506
1507 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5]", 17, 7)
1508 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5], #6", -9, 12)
1509 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5], x6", 9, 13)
1510
1511 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5]", 17, 7)
1512 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5], #3", -9, 12)
1513 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5], x6", 9, 13)
1514
1515 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5]", 17, 7)
1516 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5], #3", -9, 12)
1517 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5], x6", 9, 13)
1518
1519
1520 ////////////////////////////////////////////////////////////////
1521 printf("LD4/ST4 (single 4-elem struct to/from one lane of 4 regs\n");
1522
1523 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5]", 17, 7)
1524 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], #32", -9, 12)
1525 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], x6", 9, 13)
1526
1527 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5]", 17, 7)
1528 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], #32", -9, 12)
1529 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], x6", 9, 13)
1530
1531 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5]", 17, 7)
1532 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], #16", -9, 12)
1533 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], x6", 9, 13)
1534
1535 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5]", 17, 7)
1536 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], #16", -9, 12)
1537 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], x6", 9, 13)
1538
1539 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5]", 17, 7)
1540 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], #8", -9, 12)
1541 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], x6", 9, 13)
1542
1543 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5]", 17, 7)
1544 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], #8", -9, 12)
1545 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], x6", 9, 13)
1546
1547 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5]", 17, 7)
1548 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], #4", -9, 12)
1549 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], x6", 9, 13)
1550
1551 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5]", 17, 7)
1552 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], #4", -9, 12)
1553 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], x6", 9, 13)
1554
1555
1556 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5]", 17, 7)
1557 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], #32", -9, 12)
1558 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], x6", 9, 13)
1559
1560 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5]", 17, 7)
1561 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], #32", -9, 12)
1562 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], x6", 9, 13)
1563
1564 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5]", 17, 7)
1565 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], #16", -9, 12)
1566 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], x6", 9, 13)
1567
1568 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5]", 17, 7)
1569 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], #16", -9, 12)
1570 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], x6", 9, 13)
1571
1572 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5]", 17, 7)
1573 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], #8", -9, 12)
1574 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], x6", 9, 13)
1575
1576 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5]", 17, 7)
1577 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], #8", -9, 12)
1578 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], x6", 9, 13)
1579
1580 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5]", 17, 7)
1581 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], #4", -9, 12)
1582 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], x6", 9, 13)
1583
1584 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5]", 17, 7)
1585 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], #4", -9, 12)
1586 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], x6", 9, 13)
1587
1588 ////////////////////////////////////////////////////////////////
1589 printf("PRFM (immediate)\n");
1590
1591 MEM_TEST("prfm pldl1keep, [x5, #40]", 12, -4);
1592 MEM_TEST("prfm pstl3strm, [x5, #56]", 12, -4);
1593
1594 ////////////////////////////////////////////////////////////////
1595 printf("PRFM (register)\n");
1596
1597 MEM_TEST("prfm pldl1keep, [x5,x6]", 12, -4);
1598 MEM_TEST("prfm pldl1strm, [x5,x6, lsl #3]", 12, -4);
1599 MEM_TEST("prfm pldl2keep, [x5,w6,uxtw #0]", 12, 4);
1600 MEM_TEST("prfm pldl2strm, [x5,w6,uxtw #3]", 12, 4);
1601 MEM_TEST("prfm pldl3keep, [x5,w6,sxtw #0]", 12, 4);
1602 MEM_TEST("prfm pldl3strm, [x5,w6,sxtw #3]", 12, -4);
1603
1604 MEM_TEST("prfm pstl1keep, [x5,x6]", 12, -4);
1605 MEM_TEST("prfm pstl1strm, [x5,x6, lsl #3]", 12, -4);
1606 MEM_TEST("prfm pstl2keep, [x5,w6,uxtw #0]", 12, 4);
1607 MEM_TEST("prfm pstl2strm, [x5,w6,uxtw #3]", 12, 4);
1608 MEM_TEST("prfm pstl3keep, [x5,w6,sxtw #0]", 12, 4);
1609 MEM_TEST("prfm pstl3strm, [x5,w6,sxtw #3]", 12, -4);
1610
1611 } /* end of test_memory2() */
1612
1613 ////////////////////////////////////////////////////////////////
1614 ////////////////////////////////////////////////////////////////
1615 ////////////////////////////////////////////////////////////////
1616 ////////////////////////////////////////////////////////////////
1617 ////////////////////////////////////////////////////////////////
1618 ////////////////////////////////////////////////////////////////
1619
main(void)1620 int main ( void )
1621 {
1622 if (1) test_memory_old();
1623 if (1) test_memory_new();
1624 return 0;
1625 }
1626