1 #ifndef _UAPI_MSM_MDP_H_
2 #define _UAPI_MSM_MDP_H_
3 
4 #include <linux/types.h>
5 #include <linux/fb.h>
6 
7 #define MSMFB_IOCTL_MAGIC 'm'
8 #define MSMFB_GRP_DISP          _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int)
9 #define MSMFB_BLIT              _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int)
10 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int)
11 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int)
12 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor)
13 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap)
14 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data)
15 /* new ioctls's for set/get ccs matrix */
16 #define MSMFB_GET_CCS_MATRIX  _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs)
17 #define MSMFB_SET_CCS_MATRIX  _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs)
18 #define MSMFB_OVERLAY_SET       _IOWR(MSMFB_IOCTL_MAGIC, 135, \
19 						struct mdp_overlay)
20 #define MSMFB_OVERLAY_UNSET     _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int)
21 
22 #define MSMFB_OVERLAY_PLAY      _IOW(MSMFB_IOCTL_MAGIC, 137, \
23 						struct msmfb_overlay_data)
24 #define MSMFB_OVERLAY_QUEUE	MSMFB_OVERLAY_PLAY
25 
26 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \
27 					struct mdp_page_protection)
28 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \
29 					struct mdp_page_protection)
30 #define MSMFB_OVERLAY_GET      _IOR(MSMFB_IOCTL_MAGIC, 140, \
31 						struct mdp_overlay)
32 #define MSMFB_OVERLAY_PLAY_ENABLE     _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int)
33 #define MSMFB_OVERLAY_BLT       _IOWR(MSMFB_IOCTL_MAGIC, 142, \
34 						struct msmfb_overlay_blt)
35 #define MSMFB_OVERLAY_BLT_OFFSET     _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int)
36 #define MSMFB_HISTOGRAM_START	_IOR(MSMFB_IOCTL_MAGIC, 144, \
37 						struct mdp_histogram_start_req)
38 #define MSMFB_HISTOGRAM_STOP	_IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int)
39 #define MSMFB_NOTIFY_UPDATE	_IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int)
40 
41 #define MSMFB_OVERLAY_3D       _IOWR(MSMFB_IOCTL_MAGIC, 147, \
42 						struct msmfb_overlay_3d)
43 
44 #define MSMFB_MIXER_INFO       _IOWR(MSMFB_IOCTL_MAGIC, 148, \
45 						struct msmfb_mixer_info_req)
46 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \
47 						struct msmfb_overlay_data)
48 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150)
49 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151)
50 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152)
51 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \
52 						struct msmfb_data)
53 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \
54 						struct msmfb_data)
55 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155)
56 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp)
57 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int)
58 #define MSMFB_VSYNC_CTRL  _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int)
59 #define MSMFB_BUFFER_SYNC  _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync)
60 #define MSMFB_OVERLAY_COMMIT      _IO(MSMFB_IOCTL_MAGIC, 163)
61 #define MSMFB_DISPLAY_COMMIT      _IOW(MSMFB_IOCTL_MAGIC, 164, \
62 						struct mdp_display_commit)
63 #define MSMFB_METADATA_SET  _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata)
64 #define MSMFB_METADATA_GET  _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata)
65 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \
66 						unsigned int)
67 #define MSMFB_ASYNC_BLIT              _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int)
68 #define MSMFB_OVERLAY_PREPARE		_IOWR(MSMFB_IOCTL_MAGIC, 169, \
69 						struct mdp_overlay_list)
70 #define MSMFB_LPM_ENABLE	_IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int)
71 #define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, \
72 					      struct mdp_pp_feature_version)
73 #define MSMFB_SET_PERSISTENCE_MODE	_IOWR(MSMFB_IOCTL_MAGIC, 171, unsigned int)
74 
75 #define FB_TYPE_3D_PANEL 0x10101010
76 #define MDP_IMGTYPE2_START 0x10000
77 #define MSMFB_DRIVER_VERSION	0xF9E8D701
78 /* Maximum number of formats supported by MDP*/
79 #define MDP_IMGTYPE_END 0x100
80 
81 /* HW Revisions for different MDSS targets */
82 #define MDSS_GET_MAJOR(rev)		((rev) >> 28)
83 #define MDSS_GET_MINOR(rev)		(((rev) >> 16) & 0xFFF)
84 #define MDSS_GET_STEP(rev)		((rev) & 0xFFFF)
85 #define MDSS_GET_MAJOR_MINOR(rev)	((rev) >> 16)
86 
87 #define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2)	\
88 	(MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2)))
89 
90 #define MDSS_MDP_REV(major, minor, step)	\
91 	((((major) & 0x000F) << 28) |		\
92 	 (((minor) & 0x0FFF) << 16) |		\
93 	 ((step)   & 0xFFFF))
94 
95 #define MDSS_MDP_HW_REV_100	MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */
96 #define MDSS_MDP_HW_REV_101	MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */
97 #define MDSS_MDP_HW_REV_101_1	MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */
98 #define MDSS_MDP_HW_REV_101_2	MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */
99 #define MDSS_MDP_HW_REV_102	MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */
100 #define MDSS_MDP_HW_REV_102_1	MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */
101 #define MDSS_MDP_HW_REV_103	MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */
102 #define MDSS_MDP_HW_REV_103_1	MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */
103 #define MDSS_MDP_HW_REV_105	MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */
104 #define MDSS_MDP_HW_REV_106	MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */
105 #define MDSS_MDP_HW_REV_107	MDSS_MDP_REV(1, 7, 0) /* 8996 v1 */
106 #define MDSS_MDP_HW_REV_107_1	MDSS_MDP_REV(1, 7, 1) /* 8996 v2 */
107 #define MDSS_MDP_HW_REV_107_2	MDSS_MDP_REV(1, 7, 2) /* 8996 v3 */
108 #define MDSS_MDP_HW_REV_108	MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */
109 #define MDSS_MDP_HW_REV_109	MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */
110 #define MDSS_MDP_HW_REV_110	MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */
111 #define MDSS_MDP_HW_REV_200	MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */
112 #define MDSS_MDP_HW_REV_112	MDSS_MDP_REV(1, 12, 0) /* 8952 v1.0 */
113 #define MDSS_MDP_HW_REV_114	MDSS_MDP_REV(1, 14, 0) /* 8937 v1.0 */
114 #define MDSS_MDP_HW_REV_115	MDSS_MDP_REV(1, 15, 0) /* msm8917 */
115 #define MDSS_MDP_HW_REV_116	MDSS_MDP_REV(1, 16, 0) /* msm8953 */
116 #define MDSS_MDP_HW_REV_300	MDSS_MDP_REV(3, 0, 0)  /* msmcobalt */
117 #define MDSS_MDP_HW_REV_301	MDSS_MDP_REV(3, 0, 1)  /* msmcobalt v1.0 */
118 
119 enum {
120 	NOTIFY_UPDATE_INIT,
121 	NOTIFY_UPDATE_DEINIT,
122 	NOTIFY_UPDATE_START,
123 	NOTIFY_UPDATE_STOP,
124 	NOTIFY_UPDATE_POWER_OFF,
125 };
126 
127 enum {
128 	NOTIFY_TYPE_NO_UPDATE,
129 	NOTIFY_TYPE_SUSPEND,
130 	NOTIFY_TYPE_UPDATE,
131 	NOTIFY_TYPE_BL_UPDATE,
132 	NOTIFY_TYPE_BL_AD_ATTEN_UPDATE,
133 };
134 
135 enum {
136 	MDP_RGB_565,      /* RGB 565 planer */
137 	MDP_XRGB_8888,    /* RGB 888 padded */
138 	MDP_Y_CBCR_H2V2,  /* Y and CbCr, pseudo planer w/ Cb is in MSB */
139 	MDP_Y_CBCR_H2V2_ADRENO,
140 	MDP_ARGB_8888,    /* ARGB 888 */
141 	MDP_RGB_888,      /* RGB 888 planer */
142 	MDP_Y_CRCB_H2V2,  /* Y and CrCb, pseudo planer w/ Cr is in MSB */
143 	MDP_YCRYCB_H2V1,  /* YCrYCb interleave */
144 	MDP_CBYCRY_H2V1,  /* CbYCrY interleave */
145 	MDP_Y_CRCB_H2V1,  /* Y and CrCb, pseduo planer w/ Cr is in MSB */
146 	MDP_Y_CBCR_H2V1,   /* Y and CrCb, pseduo planer w/ Cr is in MSB */
147 	MDP_Y_CRCB_H1V2,
148 	MDP_Y_CBCR_H1V2,
149 	MDP_RGBA_8888,    /* ARGB 888 */
150 	MDP_BGRA_8888,	  /* ABGR 888 */
151 	MDP_RGBX_8888,	  /* RGBX 888 */
152 	MDP_Y_CRCB_H2V2_TILE,  /* Y and CrCb, pseudo planer tile */
153 	MDP_Y_CBCR_H2V2_TILE,  /* Y and CbCr, pseudo planer tile */
154 	MDP_Y_CR_CB_H2V2,  /* Y, Cr and Cb, planar */
155 	MDP_Y_CR_CB_GH2V2,  /* Y, Cr and Cb, planar aligned to Android YV12 */
156 	MDP_Y_CB_CR_H2V2,  /* Y, Cb and Cr, planar */
157 	MDP_Y_CRCB_H1V1,  /* Y and CrCb, pseduo planer w/ Cr is in MSB */
158 	MDP_Y_CBCR_H1V1,  /* Y and CbCr, pseduo planer w/ Cb is in MSB */
159 	MDP_YCRCB_H1V1,   /* YCrCb interleave */
160 	MDP_YCBCR_H1V1,   /* YCbCr interleave */
161 	MDP_BGR_565,      /* BGR 565 planer */
162 	MDP_BGR_888,      /* BGR 888 */
163 	MDP_Y_CBCR_H2V2_VENUS,
164 	MDP_BGRX_8888,   /* BGRX 8888 */
165 	MDP_RGBA_8888_TILE,	  /* RGBA 8888 in tile format */
166 	MDP_ARGB_8888_TILE,	  /* ARGB 8888 in tile format */
167 	MDP_ABGR_8888_TILE,	  /* ABGR 8888 in tile format */
168 	MDP_BGRA_8888_TILE,	  /* BGRA 8888 in tile format */
169 	MDP_RGBX_8888_TILE,	  /* RGBX 8888 in tile format */
170 	MDP_XRGB_8888_TILE,	  /* XRGB 8888 in tile format */
171 	MDP_XBGR_8888_TILE,	  /* XBGR 8888 in tile format */
172 	MDP_BGRX_8888_TILE,	  /* BGRX 8888 in tile format */
173 	MDP_YCBYCR_H2V1,  /* YCbYCr interleave */
174 	MDP_RGB_565_TILE,	  /* RGB 565 in tile format */
175 	MDP_BGR_565_TILE,	  /* BGR 565 in tile format */
176 	MDP_ARGB_1555,	/*ARGB 1555*/
177 	MDP_RGBA_5551,	/*RGBA 5551*/
178 	MDP_ARGB_4444,	/*ARGB 4444*/
179 	MDP_RGBA_4444,	/*RGBA 4444*/
180 	MDP_RGB_565_UBWC,
181 	MDP_RGBA_8888_UBWC,
182 	MDP_Y_CBCR_H2V2_UBWC,
183 	MDP_RGBX_8888_UBWC,
184 	MDP_Y_CRCB_H2V2_VENUS,
185 	MDP_IMGTYPE_LIMIT,
186 	MDP_RGB_BORDERFILL,	/* border fill pipe */
187 	MDP_XRGB_1555,
188 	MDP_RGBX_5551,
189 	MDP_XRGB_4444,
190 	MDP_RGBX_4444,
191 	MDP_ABGR_1555,
192 	MDP_BGRA_5551,
193 	MDP_XBGR_1555,
194 	MDP_BGRX_5551,
195 	MDP_ABGR_4444,
196 	MDP_BGRA_4444,
197 	MDP_XBGR_4444,
198 	MDP_BGRX_4444,
199 	MDP_ABGR_8888,
200 	MDP_XBGR_8888,
201 	MDP_RGBA_1010102,
202 	MDP_ARGB_2101010,
203 	MDP_RGBX_1010102,
204 	MDP_XRGB_2101010,
205 	MDP_BGRA_1010102,
206 	MDP_ABGR_2101010,
207 	MDP_BGRX_1010102,
208 	MDP_XBGR_2101010,
209 	MDP_RGBA_1010102_UBWC,
210 	MDP_RGBX_1010102_UBWC,
211 	MDP_Y_CBCR_H2V2_P010,
212 	MDP_Y_CBCR_H2V2_TP10_UBWC,
213 	MDP_IMGTYPE_LIMIT1 = MDP_IMGTYPE_END,
214 	MDP_FB_FORMAT = MDP_IMGTYPE2_START,    /* framebuffer format */
215 	MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */
216 };
217 
218 enum {
219 	PMEM_IMG,
220 	FB_IMG,
221 };
222 
223 enum {
224 	HSIC_HUE = 0,
225 	HSIC_SAT,
226 	HSIC_INT,
227 	HSIC_CON,
228 	NUM_HSIC_PARAM,
229 };
230 
231 enum mdss_mdp_max_bw_mode {
232 	MDSS_MAX_BW_LIMIT_DEFAULT = 0x1,
233 	MDSS_MAX_BW_LIMIT_CAMERA = 0x2,
234 	MDSS_MAX_BW_LIMIT_HFLIP = 0x4,
235 	MDSS_MAX_BW_LIMIT_VFLIP = 0x8,
236 };
237 
238 #define MDSS_MDP_ROT_ONLY		0x80
239 #define MDSS_MDP_RIGHT_MIXER		0x100
240 #define MDSS_MDP_DUAL_PIPE		0x200
241 
242 /* mdp_blit_req flag values */
243 #define MDP_ROT_NOP 0
244 #define MDP_FLIP_LR 0x1
245 #define MDP_FLIP_UD 0x2
246 #define MDP_ROT_90 0x4
247 #define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR)
248 #define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR)
249 #define MDP_DITHER 0x8
250 #define MDP_BLUR 0x10
251 #define MDP_BLEND_FG_PREMULT 0x20000
252 #define MDP_IS_FG 0x40000
253 #define MDP_SOLID_FILL 0x00000020
254 #define MDP_VPU_PIPE 0x00000040
255 #define MDP_DEINTERLACE 0x80000000
256 #define MDP_SHARPENING  0x40000000
257 #define MDP_NO_DMA_BARRIER_START	0x20000000
258 #define MDP_NO_DMA_BARRIER_END		0x10000000
259 #define MDP_NO_BLIT			0x08000000
260 #define MDP_BLIT_WITH_DMA_BARRIERS	0x000
261 #define MDP_BLIT_WITH_NO_DMA_BARRIERS    \
262 	(MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END)
263 #define MDP_BLIT_SRC_GEM                0x04000000
264 #define MDP_BLIT_DST_GEM                0x02000000
265 #define MDP_BLIT_NON_CACHED		0x01000000
266 #define MDP_OV_PIPE_SHARE		0x00800000
267 #define MDP_DEINTERLACE_ODD		0x00400000
268 #define MDP_OV_PLAY_NOWAIT		0x00200000
269 #define MDP_SOURCE_ROTATED_90		0x00100000
270 #define MDP_OVERLAY_PP_CFG_EN		0x00080000
271 #define MDP_BACKEND_COMPOSITION		0x00040000
272 #define MDP_BORDERFILL_SUPPORTED	0x00010000
273 #define MDP_SECURE_OVERLAY_SESSION      0x00008000
274 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION	0x00002000
275 #define MDP_OV_PIPE_FORCE_DMA		0x00004000
276 #define MDP_MEMORY_ID_TYPE_FB		0x00001000
277 #define MDP_BWC_EN			0x00000400
278 #define MDP_DECIMATION_EN		0x00000800
279 #define MDP_SMP_FORCE_ALLOC		0x00200000
280 #define MDP_TRANSP_NOP 0xffffffff
281 #define MDP_ALPHA_NOP 0xff
282 
283 #define MDP_FB_PAGE_PROTECTION_NONCACHED         (0)
284 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE      (1)
285 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2)
286 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE    (3)
287 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE  (4)
288 /* Sentinel: Don't use! */
289 #define MDP_FB_PAGE_PROTECTION_INVALID           (5)
290 /* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */
291 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES        (5)
292 
293 struct mdp_rect {
294 	uint32_t x;
295 	uint32_t y;
296 	uint32_t w;
297 	uint32_t h;
298 };
299 
300 struct mdp_img {
301 	uint32_t width;
302 	uint32_t height;
303 	uint32_t format;
304 	uint32_t offset;
305 	int memory_id;		/* the file descriptor */
306 	uint32_t priv;
307 };
308 
309 struct mult_factor {
310 	uint32_t numer;
311 	uint32_t denom;
312 };
313 
314 /*
315  * {3x3} + {3} ccs matrix
316  */
317 
318 #define MDP_CCS_RGB2YUV 	0
319 #define MDP_CCS_YUV2RGB 	1
320 
321 #define MDP_CCS_SIZE	9
322 #define MDP_BV_SIZE	3
323 
324 struct mdp_ccs {
325 	int direction;			/* MDP_CCS_RGB2YUV or YUV2RGB */
326 	uint16_t ccs[MDP_CCS_SIZE];	/* 3x3 color coefficients */
327 	uint16_t bv[MDP_BV_SIZE];	/* 1x3 bias vector */
328 };
329 
330 struct mdp_csc {
331 	int id;
332 	uint32_t csc_mv[9];
333 	uint32_t csc_pre_bv[3];
334 	uint32_t csc_post_bv[3];
335 	uint32_t csc_pre_lv[6];
336 	uint32_t csc_post_lv[6];
337 };
338 
339 /* The version of the mdp_blit_req structure so that
340  * user applications can selectively decide which functionality
341  * to include
342  */
343 
344 #define MDP_BLIT_REQ_VERSION 3
345 
346 struct color {
347 	uint32_t r;
348 	uint32_t g;
349 	uint32_t b;
350 	uint32_t alpha;
351 };
352 
353 struct mdp_blit_req {
354 	struct mdp_img src;
355 	struct mdp_img dst;
356 	struct mdp_rect src_rect;
357 	struct mdp_rect dst_rect;
358 	struct color const_color;
359 	uint32_t alpha;
360 	uint32_t transp_mask;
361 	uint32_t flags;
362 	int sharpening_strength;  /* -127 <--> 127, default 64 */
363 	uint8_t color_space;
364 	uint32_t fps;
365 };
366 
367 struct mdp_blit_req_list {
368 	uint32_t count;
369 	struct mdp_blit_req req[];
370 };
371 
372 #define MSMFB_DATA_VERSION 2
373 
374 struct msmfb_data {
375 	uint32_t offset;
376 	int memory_id;
377 	int id;
378 	uint32_t flags;
379 	uint32_t priv;
380 	uint32_t iova;
381 };
382 
383 #define MSMFB_NEW_REQUEST -1
384 
385 struct msmfb_overlay_data {
386 	uint32_t id;
387 	struct msmfb_data data;
388 	uint32_t version_key;
389 	struct msmfb_data plane1_data;
390 	struct msmfb_data plane2_data;
391 	struct msmfb_data dst_data;
392 };
393 
394 struct msmfb_img {
395 	uint32_t width;
396 	uint32_t height;
397 	uint32_t format;
398 };
399 
400 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1
401 struct msmfb_writeback_data {
402 	struct msmfb_data buf_info;
403 	struct msmfb_img img;
404 };
405 
406 #define MDP_PP_OPS_ENABLE 0x1
407 #define MDP_PP_OPS_READ 0x2
408 #define MDP_PP_OPS_WRITE 0x4
409 #define MDP_PP_OPS_DISABLE 0x8
410 #define MDP_PP_IGC_FLAG_ROM0	0x10
411 #define MDP_PP_IGC_FLAG_ROM1	0x20
412 
413 
414 #define MDSS_PP_DSPP_CFG	0x000
415 #define MDSS_PP_SSPP_CFG	0x100
416 #define MDSS_PP_LM_CFG	0x200
417 #define MDSS_PP_WB_CFG	0x300
418 
419 #define MDSS_PP_ARG_MASK	0x3C00
420 #define MDSS_PP_ARG_NUM		4
421 #define MDSS_PP_ARG_SHIFT	10
422 #define MDSS_PP_LOCATION_MASK	0x0300
423 #define MDSS_PP_LOGICAL_MASK	0x00FF
424 
425 #define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg))))
426 #define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x))))
427 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK)
428 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK)
429 
430 
431 struct mdp_qseed_cfg {
432 	uint32_t table_num;
433 	uint32_t ops;
434 	uint32_t len;
435 	uint32_t *data;
436 };
437 
438 struct mdp_sharp_cfg {
439 	uint32_t flags;
440 	uint32_t strength;
441 	uint32_t edge_thr;
442 	uint32_t smooth_thr;
443 	uint32_t noise_thr;
444 };
445 
446 struct mdp_qseed_cfg_data {
447 	uint32_t block;
448 	struct mdp_qseed_cfg qseed_data;
449 };
450 
451 #define MDP_OVERLAY_PP_CSC_CFG         0x1
452 #define MDP_OVERLAY_PP_QSEED_CFG       0x2
453 #define MDP_OVERLAY_PP_PA_CFG          0x4
454 #define MDP_OVERLAY_PP_IGC_CFG         0x8
455 #define MDP_OVERLAY_PP_SHARP_CFG       0x10
456 #define MDP_OVERLAY_PP_HIST_CFG        0x20
457 #define MDP_OVERLAY_PP_HIST_LUT_CFG    0x40
458 #define MDP_OVERLAY_PP_PA_V2_CFG       0x80
459 #define MDP_OVERLAY_PP_PCC_CFG	       0x100
460 
461 #define MDP_CSC_FLAG_ENABLE	0x1
462 #define MDP_CSC_FLAG_YUV_IN	0x2
463 #define MDP_CSC_FLAG_YUV_OUT	0x4
464 
465 #define MDP_CSC_MATRIX_COEFF_SIZE	9
466 #define MDP_CSC_CLAMP_SIZE		6
467 #define MDP_CSC_BIAS_SIZE		3
468 
469 struct mdp_csc_cfg {
470 	/* flags for enable CSC, toggling RGB,YUV input/output */
471 	uint32_t flags;
472 	uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE];
473 	uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE];
474 	uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE];
475 	uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE];
476 	uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE];
477 };
478 
479 struct mdp_csc_cfg_data {
480 	uint32_t block;
481 	struct mdp_csc_cfg csc_data;
482 };
483 
484 struct mdp_pa_cfg {
485 	uint32_t flags;
486 	uint32_t hue_adj;
487 	uint32_t sat_adj;
488 	uint32_t val_adj;
489 	uint32_t cont_adj;
490 };
491 
492 struct mdp_pa_mem_col_cfg {
493 	uint32_t color_adjust_p0;
494 	uint32_t color_adjust_p1;
495 	uint32_t hue_region;
496 	uint32_t sat_region;
497 	uint32_t val_region;
498 };
499 
500 #define MDP_SIX_ZONE_LUT_SIZE		384
501 
502 /* PA Write/Read extension flags */
503 #define MDP_PP_PA_HUE_ENABLE		0x10
504 #define MDP_PP_PA_SAT_ENABLE		0x20
505 #define MDP_PP_PA_VAL_ENABLE		0x40
506 #define MDP_PP_PA_CONT_ENABLE		0x80
507 #define MDP_PP_PA_SIX_ZONE_ENABLE	0x100
508 #define MDP_PP_PA_SKIN_ENABLE		0x200
509 #define MDP_PP_PA_SKY_ENABLE		0x400
510 #define MDP_PP_PA_FOL_ENABLE		0x800
511 
512 /* PA masks */
513 /* Masks used in PA v1_7 only */
514 #define MDP_PP_PA_MEM_PROT_HUE_EN	0x1
515 #define MDP_PP_PA_MEM_PROT_SAT_EN	0x2
516 #define MDP_PP_PA_MEM_PROT_VAL_EN	0x4
517 #define MDP_PP_PA_MEM_PROT_CONT_EN	0x8
518 #define MDP_PP_PA_MEM_PROT_SIX_EN	0x10
519 #define MDP_PP_PA_MEM_PROT_BLEND_EN	0x20
520 /* Masks used in all PAv2 versions */
521 #define MDP_PP_PA_HUE_MASK		0x1000
522 #define MDP_PP_PA_SAT_MASK		0x2000
523 #define MDP_PP_PA_VAL_MASK		0x4000
524 #define MDP_PP_PA_CONT_MASK		0x8000
525 #define MDP_PP_PA_SIX_ZONE_HUE_MASK	0x10000
526 #define MDP_PP_PA_SIX_ZONE_SAT_MASK	0x20000
527 #define MDP_PP_PA_SIX_ZONE_VAL_MASK	0x40000
528 #define MDP_PP_PA_MEM_COL_SKIN_MASK	0x80000
529 #define MDP_PP_PA_MEM_COL_SKY_MASK	0x100000
530 #define MDP_PP_PA_MEM_COL_FOL_MASK	0x200000
531 #define MDP_PP_PA_MEM_PROTECT_EN	0x400000
532 #define MDP_PP_PA_SAT_ZERO_EXP_EN	0x800000
533 
534 /* Flags for setting PA saturation and value hold */
535 #define MDP_PP_PA_LEFT_HOLD		0x1
536 #define MDP_PP_PA_RIGHT_HOLD		0x2
537 
538 struct mdp_pa_v2_data {
539 	/* Mask bits for PA features */
540 	uint32_t flags;
541 	uint32_t global_hue_adj;
542 	uint32_t global_sat_adj;
543 	uint32_t global_val_adj;
544 	uint32_t global_cont_adj;
545 	struct mdp_pa_mem_col_cfg skin_cfg;
546 	struct mdp_pa_mem_col_cfg sky_cfg;
547 	struct mdp_pa_mem_col_cfg fol_cfg;
548 	uint32_t six_zone_len;
549 	uint32_t six_zone_thresh;
550 	uint32_t *six_zone_curve_p0;
551 	uint32_t *six_zone_curve_p1;
552 };
553 
554 struct mdp_pa_mem_col_data_v1_7 {
555 	uint32_t color_adjust_p0;
556 	uint32_t color_adjust_p1;
557 	uint32_t color_adjust_p2;
558 	uint32_t blend_gain;
559 	uint8_t sat_hold;
560 	uint8_t val_hold;
561 	uint32_t hue_region;
562 	uint32_t sat_region;
563 	uint32_t val_region;
564 };
565 
566 struct mdp_pa_data_v1_7 {
567 	uint32_t mode;
568 	uint32_t global_hue_adj;
569 	uint32_t global_sat_adj;
570 	uint32_t global_val_adj;
571 	uint32_t global_cont_adj;
572 	struct mdp_pa_mem_col_data_v1_7 skin_cfg;
573 	struct mdp_pa_mem_col_data_v1_7 sky_cfg;
574 	struct mdp_pa_mem_col_data_v1_7 fol_cfg;
575 	uint32_t six_zone_thresh;
576 	uint32_t six_zone_adj_p0;
577 	uint32_t six_zone_adj_p1;
578 	uint8_t six_zone_sat_hold;
579 	uint8_t six_zone_val_hold;
580 	uint32_t six_zone_len;
581 	uint32_t *six_zone_curve_p0;
582 	uint32_t *six_zone_curve_p1;
583 };
584 
585 
586 struct mdp_pa_v2_cfg_data {
587 	uint32_t version;
588 	uint32_t block;
589 	uint32_t flags;
590 	struct mdp_pa_v2_data pa_v2_data;
591 	void *cfg_payload;
592 };
593 
594 
595 enum {
596 	mdp_igc_rec601 = 1,
597 	mdp_igc_rec709,
598 	mdp_igc_srgb,
599 	mdp_igc_custom,
600 	mdp_igc_rec_max,
601 };
602 
603 struct mdp_igc_lut_data {
604 	uint32_t block;
605 	uint32_t version;
606 	uint32_t len, ops;
607 	uint32_t *c0_c1_data;
608 	uint32_t *c2_data;
609 	void *cfg_payload;
610 };
611 
612 struct mdp_igc_lut_data_v1_7 {
613 	uint32_t table_fmt;
614 	uint32_t len;
615 	uint32_t *c0_c1_data;
616 	uint32_t *c2_data;
617 };
618 
619 struct mdp_histogram_cfg {
620 	uint32_t ops;
621 	uint32_t block;
622 	uint8_t frame_cnt;
623 	uint8_t bit_mask;
624 	uint16_t num_bins;
625 };
626 
627 struct mdp_hist_lut_data_v1_7 {
628 	uint32_t len;
629 	uint32_t *data;
630 };
631 
632 struct mdp_hist_lut_data {
633 	uint32_t block;
634 	uint32_t version;
635 	uint32_t hist_lut_first;
636 	uint32_t ops;
637 	uint32_t len;
638 	uint32_t *data;
639 	void *cfg_payload;
640 };
641 
642 struct mdp_pcc_coeff {
643 	uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1;
644 };
645 
646 struct mdp_pcc_coeff_v1_7 {
647 	uint32_t c, r, g, b, rg, gb, rb, rgb;
648 };
649 
650 struct mdp_pcc_data_v1_7 {
651 	struct mdp_pcc_coeff_v1_7 r, g, b;
652 };
653 
654 struct mdp_pcc_cfg_data {
655 	uint32_t version;
656 	uint32_t block;
657 	uint32_t ops;
658 	struct mdp_pcc_coeff r, g, b;
659 	void *cfg_payload;
660 };
661 
662 enum {
663 	mdp_lut_igc,
664 	mdp_lut_pgc,
665 	mdp_lut_hist,
666 	mdp_lut_rgb,
667 	mdp_lut_max,
668 };
669 struct mdp_overlay_pp_params {
670 	uint32_t config_ops;
671 	struct mdp_csc_cfg csc_cfg;
672 	struct mdp_qseed_cfg qseed_cfg[2];
673 	struct mdp_pa_cfg pa_cfg;
674 	struct mdp_pa_v2_data pa_v2_cfg;
675 	struct mdp_igc_lut_data igc_cfg;
676 	struct mdp_sharp_cfg sharp_cfg;
677 	struct mdp_histogram_cfg hist_cfg;
678 	struct mdp_hist_lut_data hist_lut_cfg;
679 	/* PAv2 cfg data for PA 2.x versions */
680 	struct mdp_pa_v2_cfg_data pa_v2_cfg_data;
681 	struct mdp_pcc_cfg_data pcc_cfg_data;
682 };
683 
684 /**
685  * enum mdss_mdp_blend_op - Different blend operations set by userspace
686  *
687  * @BLEND_OP_NOT_DEFINED:    No blend operation defined for the layer.
688  * @BLEND_OP_OPAQUE:         Apply a constant blend operation. The layer
689  *                           would appear opaque in case fg plane alpha is
690  *                           0xff.
691  * @BLEND_OP_PREMULTIPLIED:  Apply source over blend rule. Layer already has
692  *                           alpha pre-multiplication done. If fg plane alpha
693  *                           is less than 0xff, apply modulation as well. This
694  *                           operation is intended on layers having alpha
695  *                           channel.
696  * @BLEND_OP_COVERAGE:       Apply source over blend rule. Layer is not alpha
697  *                           pre-multiplied. Apply pre-multiplication. If fg
698  *                           plane alpha is less than 0xff, apply modulation as
699  *                           well.
700  * @BLEND_OP_MAX:            Used to track maximum blend operation possible by
701  *                           mdp.
702  */
703 enum mdss_mdp_blend_op {
704 	BLEND_OP_NOT_DEFINED = 0,
705 	BLEND_OP_OPAQUE,
706 	BLEND_OP_PREMULTIPLIED,
707 	BLEND_OP_COVERAGE,
708 	BLEND_OP_MAX,
709 };
710 
711 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
712 #define MAX_PLANES	4
713 struct mdp_scale_data {
714 	uint8_t enable_pxl_ext;
715 
716 	int init_phase_x[MAX_PLANES];
717 	int phase_step_x[MAX_PLANES];
718 	int init_phase_y[MAX_PLANES];
719 	int phase_step_y[MAX_PLANES];
720 
721 	int num_ext_pxls_left[MAX_PLANES];
722 	int num_ext_pxls_right[MAX_PLANES];
723 	int num_ext_pxls_top[MAX_PLANES];
724 	int num_ext_pxls_btm[MAX_PLANES];
725 
726 	int left_ftch[MAX_PLANES];
727 	int left_rpt[MAX_PLANES];
728 	int right_ftch[MAX_PLANES];
729 	int right_rpt[MAX_PLANES];
730 
731 	int top_rpt[MAX_PLANES];
732 	int btm_rpt[MAX_PLANES];
733 	int top_ftch[MAX_PLANES];
734 	int btm_ftch[MAX_PLANES];
735 
736 	uint32_t roi_w[MAX_PLANES];
737 };
738 
739 /**
740  * enum mdp_overlay_pipe_type - Different pipe type set by userspace
741  *
742  * @PIPE_TYPE_AUTO:    Not specified, pipe will be selected according to flags.
743  * @PIPE_TYPE_VIG:     VIG pipe.
744  * @PIPE_TYPE_RGB:     RGB pipe.
745  * @PIPE_TYPE_DMA:     DMA pipe.
746  * @PIPE_TYPE_CURSOR:  CURSOR pipe.
747  * @PIPE_TYPE_MAX:     Used to track maximum number of pipe type.
748  */
749 enum mdp_overlay_pipe_type {
750 	PIPE_TYPE_AUTO = 0,
751 	PIPE_TYPE_VIG,
752 	PIPE_TYPE_RGB,
753 	PIPE_TYPE_DMA,
754 	PIPE_TYPE_CURSOR,
755 	PIPE_TYPE_MAX,
756 };
757 
758 /**
759  * struct mdp_overlay - overlay surface structure
760  * @src:	Source image information (width, height, format).
761  * @src_rect:	Source crop rectangle, portion of image that will be fetched.
762  *		This should always be within boundaries of source image.
763  * @dst_rect:	Destination rectangle, the position and size of image on screen.
764  *		This should always be within panel boundaries.
765  * @z_order:	Blending stage to occupy in display, if multiple layers are
766  *		present, highest z_order usually means the top most visible
767  *		layer. The range acceptable is from 0-3 to support blending
768  *		up to 4 layers.
769  * @is_fg:	This flag is used to disable blending of any layers with z_order
770  *		less than this overlay. It means that any layers with z_order
771  *		less than this layer will not be blended and will be replaced
772  *		by the background border color.
773  * @alpha:	Used to set plane opacity. The range can be from 0-255, where
774  *		0 means completely transparent and 255 means fully opaque.
775  * @transp_mask: Color used as color key for transparency. Any pixel in fetched
776  *		image matching this color will be transparent when blending.
777  *		The color should be in same format as the source image format.
778  * @flags:	This is used to customize operation of overlay. See MDP flags
779  *		for more information.
780  * @pipe_type:  Used to specify the type of overlay pipe.
781  * @user_data:	DEPRECATED* Used to store user application specific information.
782  * @bg_color:	Solid color used to fill the overlay surface when no source
783  *		buffer is provided.
784  * @horz_deci:	Horizontal decimation value, this indicates the amount of pixels
785  *		dropped for each pixel that is fetched from a line. The value
786  *		given should be power of two of decimation amount.
787  *		0: no decimation
788  *		1: decimate by 2 (drop 1 pixel for each pixel fetched)
789  *		2: decimate by 4 (drop 3 pixels for each pixel fetched)
790  *		3: decimate by 8 (drop 7 pixels for each pixel fetched)
791  *		4: decimate by 16 (drop 15 pixels for each pixel fetched)
792  * @vert_deci:	Vertical decimation value, this indicates the amount of lines
793  *		dropped for each line that is fetched from overlay. The value
794  *		given should be power of two of decimation amount.
795  *		0: no decimation
796  *		1: decimation by 2 (drop 1 line for each line fetched)
797  *		2: decimation by 4 (drop 3 lines for each line fetched)
798  *		3: decimation by 8 (drop 7 lines for each line fetched)
799  *		4: decimation by 16 (drop 15 lines for each line fetched)
800  * @overlay_pp_cfg: Overlay post processing configuration, for more information
801  *		see struct mdp_overlay_pp_params.
802  * @priority:	Priority is returned by the driver when overlay is set for the
803  *		first time. It indicates the priority of the underlying pipe
804  *		serving the overlay. This priority can be used by user-space
805  *		in source split when pipes are re-used and shuffled around to
806  *		reduce fallbacks.
807  */
808 struct mdp_overlay {
809 	struct msmfb_img src;
810 	struct mdp_rect src_rect;
811 	struct mdp_rect dst_rect;
812 	uint32_t z_order;	/* stage number */
813 	uint32_t is_fg;		/* control alpha & transp */
814 	uint32_t alpha;
815 	uint32_t blend_op;
816 	uint32_t transp_mask;
817 	uint32_t flags;
818 	uint32_t pipe_type;
819 	uint32_t id;
820 	uint8_t priority;
821 	uint32_t user_data[6];
822 	uint32_t bg_color;
823 	uint8_t horz_deci;
824 	uint8_t vert_deci;
825 	struct mdp_overlay_pp_params overlay_pp_cfg;
826 	struct mdp_scale_data scale;
827 	uint8_t color_space;
828 	uint32_t frame_rate;
829 };
830 
831 struct msmfb_overlay_3d {
832 	uint32_t is_3d;
833 	uint32_t width;
834 	uint32_t height;
835 };
836 
837 
838 struct msmfb_overlay_blt {
839 	uint32_t enable;
840 	uint32_t offset;
841 	uint32_t width;
842 	uint32_t height;
843 	uint32_t bpp;
844 };
845 
846 struct mdp_histogram {
847 	uint32_t frame_cnt;
848 	uint32_t bin_cnt;
849 	uint32_t *r;
850 	uint32_t *g;
851 	uint32_t *b;
852 };
853 
854 #define MISR_CRC_BATCH_SIZE 32
855 enum {
856 	DISPLAY_MISR_EDP,
857 	DISPLAY_MISR_DSI0,
858 	DISPLAY_MISR_DSI1,
859 	DISPLAY_MISR_HDMI,
860 	DISPLAY_MISR_LCDC,
861 	DISPLAY_MISR_MDP,
862 	DISPLAY_MISR_ATV,
863 	DISPLAY_MISR_DSI_CMD,
864 	DISPLAY_MISR_MAX
865 };
866 
867 enum {
868 	MISR_OP_NONE,
869 	MISR_OP_SFM,
870 	MISR_OP_MFM,
871 	MISR_OP_BM,
872 	MISR_OP_MAX
873 };
874 
875 struct mdp_misr {
876 	uint32_t block_id;
877 	uint32_t frame_count;
878 	uint32_t crc_op_mode;
879 	uint32_t crc_value[MISR_CRC_BATCH_SIZE];
880 };
881 
882 /*
883 
884 	mdp_block_type defines the identifiers for pipes in MDP 4.3 and up
885 
886 	MDP_BLOCK_RESERVED is provided for backward compatibility and is
887 	deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used
888 	instead.
889 
890 	MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses,
891 	same for others.
892 
893 */
894 
895 enum {
896 	MDP_BLOCK_RESERVED = 0,
897 	MDP_BLOCK_OVERLAY_0,
898 	MDP_BLOCK_OVERLAY_1,
899 	MDP_BLOCK_VG_1,
900 	MDP_BLOCK_VG_2,
901 	MDP_BLOCK_RGB_1,
902 	MDP_BLOCK_RGB_2,
903 	MDP_BLOCK_DMA_P,
904 	MDP_BLOCK_DMA_S,
905 	MDP_BLOCK_DMA_E,
906 	MDP_BLOCK_OVERLAY_2,
907 	MDP_LOGICAL_BLOCK_DISP_0 = 0x10,
908 	MDP_LOGICAL_BLOCK_DISP_1,
909 	MDP_LOGICAL_BLOCK_DISP_2,
910 	MDP_BLOCK_MAX,
911 };
912 
913 /*
914  * mdp_histogram_start_req is used to provide the parameters for
915  * histogram start request
916  */
917 
918 struct mdp_histogram_start_req {
919 	uint32_t block;
920 	uint8_t frame_cnt;
921 	uint8_t bit_mask;
922 	uint16_t num_bins;
923 };
924 
925 /*
926  * mdp_histogram_data is used to return the histogram data, once
927  * the histogram is done/stopped/cance
928  */
929 
930 struct mdp_histogram_data {
931 	uint32_t block;
932 	uint32_t bin_cnt;
933 	uint32_t *c0;
934 	uint32_t *c1;
935 	uint32_t *c2;
936 	uint32_t *extra_info;
937 };
938 
939 
940 #define GC_LUT_ENTRIES_V1_7	512
941 
942 struct mdp_ar_gc_lut_data {
943 	uint32_t x_start;
944 	uint32_t slope;
945 	uint32_t offset;
946 };
947 
948 #define MDP_PP_PGC_ROUNDING_ENABLE 0x10
949 struct mdp_pgc_lut_data {
950 	uint32_t version;
951 	uint32_t block;
952 	uint32_t flags;
953 	uint8_t num_r_stages;
954 	uint8_t num_g_stages;
955 	uint8_t num_b_stages;
956 	struct mdp_ar_gc_lut_data *r_data;
957 	struct mdp_ar_gc_lut_data *g_data;
958 	struct mdp_ar_gc_lut_data *b_data;
959 	void *cfg_payload;
960 };
961 
962 #define PGC_LUT_ENTRIES 1024
963 struct mdp_pgc_lut_data_v1_7 {
964 	uint32_t  len;
965 	uint32_t  *c0_data;
966 	uint32_t  *c1_data;
967 	uint32_t  *c2_data;
968 };
969 
970 /*
971  * mdp_rgb_lut_data is used to provide parameters for configuring the
972  * generic RGB lut in case of gamma correction or other LUT updation usecases
973  */
974 struct mdp_rgb_lut_data {
975 	uint32_t flags;
976 	uint32_t lut_type;
977 	struct fb_cmap cmap;
978 };
979 
980 enum {
981 	mdp_rgb_lut_gc,
982 	mdp_rgb_lut_hist,
983 };
984 
985 struct mdp_lut_cfg_data {
986 	uint32_t lut_type;
987 	union {
988 		struct mdp_igc_lut_data igc_lut_data;
989 		struct mdp_pgc_lut_data pgc_lut_data;
990 		struct mdp_hist_lut_data hist_lut_data;
991 		struct mdp_rgb_lut_data rgb_lut_data;
992 	} data;
993 };
994 
995 struct mdp_bl_scale_data {
996 	uint32_t min_lvl;
997 	uint32_t scale;
998 };
999 
1000 struct mdp_pa_cfg_data {
1001 	uint32_t block;
1002 	struct mdp_pa_cfg pa_data;
1003 };
1004 
1005 #define MDP_DITHER_DATA_V1_7_SZ 16
1006 
1007 struct mdp_dither_data_v1_7 {
1008 	uint32_t g_y_depth;
1009 	uint32_t r_cr_depth;
1010 	uint32_t b_cb_depth;
1011 	uint32_t len;
1012 	uint32_t data[MDP_DITHER_DATA_V1_7_SZ];
1013 	uint32_t temporal_en;
1014 };
1015 
1016 struct mdp_dither_cfg_data {
1017 	uint32_t version;
1018 	uint32_t block;
1019 	uint32_t flags;
1020 	uint32_t mode;
1021 	uint32_t g_y_depth;
1022 	uint32_t r_cr_depth;
1023 	uint32_t b_cb_depth;
1024 	void *cfg_payload;
1025 };
1026 
1027 #define MDP_GAMUT_TABLE_NUM		8
1028 #define MDP_GAMUT_TABLE_NUM_V1_7	4
1029 #define MDP_GAMUT_SCALE_OFF_TABLE_NUM	3
1030 #define MDP_GAMUT_TABLE_V1_7_SZ 1229
1031 #define MDP_GAMUT_SCALE_OFF_SZ 16
1032 #define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32
1033 
1034 struct mdp_gamut_cfg_data {
1035 	uint32_t block;
1036 	uint32_t flags;
1037 	uint32_t version;
1038 	/* v1 version specific params */
1039 	uint32_t gamut_first;
1040 	uint32_t tbl_size[MDP_GAMUT_TABLE_NUM];
1041 	uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM];
1042 	uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM];
1043 	uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM];
1044 	/* params for newer versions of gamut */
1045 	void *cfg_payload;
1046 };
1047 
1048 enum {
1049 	mdp_gamut_fine_mode = 0x1,
1050 	mdp_gamut_coarse_mode,
1051 };
1052 
1053 struct mdp_gamut_data_v1_7 {
1054 	uint32_t mode;
1055 	uint32_t map_en;
1056 	uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7];
1057 	uint32_t *c0_data[MDP_GAMUT_TABLE_NUM_V1_7];
1058 	uint32_t *c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7];
1059 	uint32_t  tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM];
1060 	uint32_t  *scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM];
1061 };
1062 
1063 struct mdp_calib_config_data {
1064 	uint32_t ops;
1065 	uint32_t addr;
1066 	uint32_t data;
1067 };
1068 
1069 struct mdp_calib_config_buffer {
1070 	uint32_t ops;
1071 	uint32_t size;
1072 	uint32_t *buffer;
1073 };
1074 
1075 struct mdp_calib_dcm_state {
1076 	uint32_t ops;
1077 	uint32_t dcm_state;
1078 };
1079 
1080 enum {
1081 	DCM_UNINIT,
1082 	DCM_UNBLANK,
1083 	DCM_ENTER,
1084 	DCM_EXIT,
1085 	DCM_BLANK,
1086 	DTM_ENTER,
1087 	DTM_EXIT,
1088 };
1089 
1090 #define MDSS_PP_SPLIT_LEFT_ONLY		0x10000000
1091 #define MDSS_PP_SPLIT_RIGHT_ONLY	0x20000000
1092 #define MDSS_PP_SPLIT_MASK		0x30000000
1093 
1094 #define MDSS_MAX_BL_BRIGHTNESS 255
1095 #define AD_BL_LIN_LEN 256
1096 #define AD_BL_ATT_LUT_LEN 33
1097 
1098 #define MDSS_AD_MODE_AUTO_BL	0x0
1099 #define MDSS_AD_MODE_AUTO_STR	0x1
1100 #define MDSS_AD_MODE_TARG_STR	0x3
1101 #define MDSS_AD_MODE_MAN_STR	0x7
1102 #define MDSS_AD_MODE_CALIB	0xF
1103 
1104 #define MDP_PP_AD_INIT	0x10
1105 #define MDP_PP_AD_CFG	0x20
1106 
1107 struct mdss_ad_init {
1108 	uint32_t asym_lut[33];
1109 	uint32_t color_corr_lut[33];
1110 	uint8_t i_control[2];
1111 	uint16_t black_lvl;
1112 	uint16_t white_lvl;
1113 	uint8_t var;
1114 	uint8_t limit_ampl;
1115 	uint8_t i_dither;
1116 	uint8_t slope_max;
1117 	uint8_t slope_min;
1118 	uint8_t dither_ctl;
1119 	uint8_t format;
1120 	uint8_t auto_size;
1121 	uint16_t frame_w;
1122 	uint16_t frame_h;
1123 	uint8_t logo_v;
1124 	uint8_t logo_h;
1125 	uint32_t alpha;
1126 	uint32_t alpha_base;
1127 	uint32_t al_thresh;
1128 	uint32_t bl_lin_len;
1129 	uint32_t bl_att_len;
1130 	uint32_t *bl_lin;
1131 	uint32_t *bl_lin_inv;
1132 	uint32_t *bl_att_lut;
1133 };
1134 
1135 #define MDSS_AD_BL_CTRL_MODE_EN 1
1136 #define MDSS_AD_BL_CTRL_MODE_DIS 0
1137 struct mdss_ad_cfg {
1138 	uint32_t mode;
1139 	uint32_t al_calib_lut[33];
1140 	uint16_t backlight_min;
1141 	uint16_t backlight_max;
1142 	uint16_t backlight_scale;
1143 	uint16_t amb_light_min;
1144 	uint16_t filter[2];
1145 	uint16_t calib[4];
1146 	uint8_t strength_limit;
1147 	uint8_t t_filter_recursion;
1148 	uint16_t stab_itr;
1149 	uint32_t bl_ctrl_mode;
1150 };
1151 
1152 /* ops uses standard MDP_PP_* flags */
1153 struct mdss_ad_init_cfg {
1154 	uint32_t ops;
1155 	union {
1156 		struct mdss_ad_init init;
1157 		struct mdss_ad_cfg cfg;
1158 	} params;
1159 };
1160 
1161 /* mode uses MDSS_AD_MODE_* flags */
1162 struct mdss_ad_input {
1163 	uint32_t mode;
1164 	union {
1165 		uint32_t amb_light;
1166 		uint32_t strength;
1167 		uint32_t calib_bl;
1168 	} in;
1169 	uint32_t output;
1170 };
1171 
1172 #define MDSS_CALIB_MODE_BL	0x1
1173 struct mdss_calib_cfg {
1174 	uint32_t ops;
1175 	uint32_t calib_mask;
1176 };
1177 
1178 enum {
1179 	mdp_op_pcc_cfg,
1180 	mdp_op_csc_cfg,
1181 	mdp_op_lut_cfg,
1182 	mdp_op_qseed_cfg,
1183 	mdp_bl_scale_cfg,
1184 	mdp_op_pa_cfg,
1185 	mdp_op_pa_v2_cfg,
1186 	mdp_op_dither_cfg,
1187 	mdp_op_gamut_cfg,
1188 	mdp_op_calib_cfg,
1189 	mdp_op_ad_cfg,
1190 	mdp_op_ad_input,
1191 	mdp_op_calib_mode,
1192 	mdp_op_calib_buffer,
1193 	mdp_op_calib_dcm_state,
1194 	mdp_op_max,
1195 };
1196 
1197 enum {
1198 	WB_FORMAT_NV12,
1199 	WB_FORMAT_RGB_565,
1200 	WB_FORMAT_RGB_888,
1201 	WB_FORMAT_xRGB_8888,
1202 	WB_FORMAT_ARGB_8888,
1203 	WB_FORMAT_BGRA_8888,
1204 	WB_FORMAT_BGRX_8888,
1205 	WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */
1206 };
1207 
1208 struct msmfb_mdp_pp {
1209 	uint32_t op;
1210 	union {
1211 		struct mdp_pcc_cfg_data pcc_cfg_data;
1212 		struct mdp_csc_cfg_data csc_cfg_data;
1213 		struct mdp_lut_cfg_data lut_cfg_data;
1214 		struct mdp_qseed_cfg_data qseed_cfg_data;
1215 		struct mdp_bl_scale_data bl_scale_data;
1216 		struct mdp_pa_cfg_data pa_cfg_data;
1217 		struct mdp_pa_v2_cfg_data pa_v2_cfg_data;
1218 		struct mdp_dither_cfg_data dither_cfg_data;
1219 		struct mdp_gamut_cfg_data gamut_cfg_data;
1220 		struct mdp_calib_config_data calib_cfg;
1221 		struct mdss_ad_init_cfg ad_init_cfg;
1222 		struct mdss_calib_cfg mdss_calib_cfg;
1223 		struct mdss_ad_input ad_input;
1224 		struct mdp_calib_config_buffer calib_buffer;
1225 		struct mdp_calib_dcm_state calib_dcm;
1226 	} data;
1227 };
1228 
1229 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1
1230 enum {
1231 	metadata_op_none,
1232 	metadata_op_base_blend,
1233 	metadata_op_frame_rate,
1234 	metadata_op_vic,
1235 	metadata_op_wb_format,
1236 	metadata_op_wb_secure,
1237 	metadata_op_get_caps,
1238 	metadata_op_crc,
1239 	metadata_op_get_ion_fd,
1240 	metadata_op_max
1241 };
1242 
1243 struct mdp_blend_cfg {
1244 	uint32_t is_premultiplied;
1245 };
1246 
1247 struct mdp_mixer_cfg {
1248 	uint32_t writeback_format;
1249 	uint32_t alpha;
1250 };
1251 
1252 struct mdss_hw_caps {
1253 	uint32_t mdp_rev;
1254 	uint8_t rgb_pipes;
1255 	uint8_t vig_pipes;
1256 	uint8_t dma_pipes;
1257 	uint8_t max_smp_cnt;
1258 	uint8_t smp_per_pipe;
1259 	uint32_t features;
1260 };
1261 
1262 struct msmfb_metadata {
1263 	uint32_t op;
1264 	uint32_t flags;
1265 	union {
1266 		struct mdp_misr misr_request;
1267 		struct mdp_blend_cfg blend_cfg;
1268 		struct mdp_mixer_cfg mixer_cfg;
1269 		uint32_t panel_frame_rate;
1270 		uint32_t video_info_code;
1271 		struct mdss_hw_caps caps;
1272 		uint8_t secure_en;
1273 		int fbmem_ionfd;
1274 	} data;
1275 };
1276 
1277 #define MDP_MAX_FENCE_FD	32
1278 #define MDP_BUF_SYNC_FLAG_WAIT	1
1279 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE	0x10
1280 
1281 struct mdp_buf_sync {
1282 	uint32_t flags;
1283 	uint32_t acq_fen_fd_cnt;
1284 	uint32_t session_id;
1285 	int *acq_fen_fd;
1286 	int *rel_fen_fd;
1287 	int *retire_fen_fd;
1288 };
1289 
1290 struct mdp_async_blit_req_list {
1291 	struct mdp_buf_sync sync;
1292 	uint32_t count;
1293 	struct mdp_blit_req req[];
1294 };
1295 
1296 #define MDP_DISPLAY_COMMIT_OVERLAY	1
1297 
1298 struct mdp_display_commit {
1299 	uint32_t flags;
1300 	uint32_t wait_for_finish;
1301 	struct fb_var_screeninfo var;
1302 	/*
1303 	 * user needs to follow guidelines as per below rules
1304 	 * 1. source split is enabled: l_roi = roi and r_roi = 0
1305 	 * 2. source split is disabled:
1306 	 *	2.1 split display: l_roi = l_roi and r_roi = r_roi
1307 	 *	2.2 non split display: l_roi = roi and r_roi = 0
1308 	 */
1309 	struct mdp_rect l_roi;
1310 	struct mdp_rect r_roi;
1311 };
1312 
1313 /**
1314  * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE
1315  * @num_overlays:	Number of overlay layers as part of the frame.
1316  * @overlay_list:	Pointer to a list of overlay structures identifying
1317  *			the layers as part of the frame
1318  * @flags:		Flags can be used to extend behavior.
1319  * @processed_overlays:	Output parameter indicating how many pipes were
1320  *			successful. If there are no errors this number should
1321  *			match num_overlays. Otherwise it will indicate the last
1322  *			successful index for overlay that couldn't be set.
1323  */
1324 struct mdp_overlay_list {
1325 	uint32_t num_overlays;
1326 	struct mdp_overlay **overlay_list;
1327 	uint32_t flags;
1328 	uint32_t processed_overlays;
1329 };
1330 
1331 struct mdp_page_protection {
1332 	uint32_t page_protection;
1333 };
1334 
1335 
1336 struct mdp_mixer_info {
1337 	int pndx;
1338 	int pnum;
1339 	int ptype;
1340 	int mixer_num;
1341 	int z_order;
1342 };
1343 
1344 #define MAX_PIPE_PER_MIXER  7
1345 
1346 struct msmfb_mixer_info_req {
1347 	int mixer_num;
1348 	int cnt;
1349 	struct mdp_mixer_info info[MAX_PIPE_PER_MIXER];
1350 };
1351 
1352 enum {
1353 	DISPLAY_SUBSYSTEM_ID,
1354 	ROTATOR_SUBSYSTEM_ID,
1355 };
1356 
1357 enum {
1358 	MDP_IOMMU_DOMAIN_CP,
1359 	MDP_IOMMU_DOMAIN_NS,
1360 };
1361 
1362 enum {
1363 	MDP_WRITEBACK_MIRROR_OFF,
1364 	MDP_WRITEBACK_MIRROR_ON,
1365 	MDP_WRITEBACK_MIRROR_PAUSE,
1366 	MDP_WRITEBACK_MIRROR_RESUME,
1367 };
1368 
1369 enum mdp_color_space {
1370 	MDP_CSC_ITU_R_601,
1371 	MDP_CSC_ITU_R_601_FR,
1372 	MDP_CSC_ITU_R_709,
1373 };
1374 
1375 enum {
1376 	mdp_igc_v1_7 = 1,
1377 	mdp_igc_vmax,
1378 	mdp_hist_lut_v1_7,
1379 	mdp_hist_lut_vmax,
1380 	mdp_pgc_v1_7,
1381 	mdp_pgc_vmax,
1382 	mdp_dither_v1_7,
1383 	mdp_dither_vmax,
1384 	mdp_gamut_v1_7,
1385 	mdp_gamut_vmax,
1386 	mdp_pa_v1_7,
1387 	mdp_pa_vmax,
1388 	mdp_pcc_v1_7,
1389 	mdp_pcc_vmax,
1390 	mdp_pp_legacy,
1391 };
1392 
1393 /* PP Features */
1394 enum {
1395 	IGC = 1,
1396 	PCC,
1397 	GC,
1398 	PA,
1399 	GAMUT,
1400 	DITHER,
1401 	QSEED,
1402 	HIST_LUT,
1403 	HIST,
1404 	PP_FEATURE_MAX,
1405 };
1406 
1407 struct mdp_pp_feature_version {
1408 	uint32_t pp_feature;
1409 	uint32_t version_info;
1410 };
1411 #endif /*_UAPI_MSM_MDP_H_*/
1412