1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
2  *
3  * This program is free software; you can redistribute it and/or modify
4  * it under the terms of the GNU General Public License version 2 and
5  * only version 2 as published by the Free Software Foundation.
6  *
7  * This program is distributed in the hope that it will be useful,
8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10  * GNU General Public License for more details.
11  */
12 #ifndef __MSMB_ISP__
13 #define __MSMB_ISP__
14 
15 #include <linux/videodev2.h>
16 
17 #define MAX_PLANES_PER_STREAM 3
18 #define MAX_NUM_STREAM 7
19 
20 #define ISP_VERSION_47        47
21 #define ISP_VERSION_46        46
22 #define ISP_VERSION_44        44
23 #define ISP_VERSION_40        40
24 #define ISP_VERSION_32        32
25 #define ISP_NATIVE_BUF_BIT    (0x10000 << 0)
26 #define ISP0_BIT              (0x10000 << 1)
27 #define ISP1_BIT              (0x10000 << 2)
28 #define ISP_META_CHANNEL_BIT  (0x10000 << 3)
29 #define ISP_SCRATCH_BUF_BIT   (0x10000 << 4)
30 #define ISP_OFFLINE_STATS_BIT (0x10000 << 5)
31 #define ISP_STATS_STREAM_BIT  0x80000000
32 
33 struct msm_vfe_cfg_cmd_list;
34 
35 enum ISP_START_PIXEL_PATTERN {
36 	ISP_BAYER_RGRGRG,
37 	ISP_BAYER_GRGRGR,
38 	ISP_BAYER_BGBGBG,
39 	ISP_BAYER_GBGBGB,
40 	ISP_YUV_YCbYCr,
41 	ISP_YUV_YCrYCb,
42 	ISP_YUV_CbYCrY,
43 	ISP_YUV_CrYCbY,
44 	ISP_PIX_PATTERN_MAX
45 };
46 
47 enum msm_vfe_plane_fmt {
48 	Y_PLANE,
49 	CB_PLANE,
50 	CR_PLANE,
51 	CRCB_PLANE,
52 	CBCR_PLANE,
53 	VFE_PLANE_FMT_MAX
54 };
55 
56 enum msm_vfe_input_src {
57 	VFE_PIX_0,
58 	VFE_RAW_0,
59 	VFE_RAW_1,
60 	VFE_RAW_2,
61 	VFE_SRC_MAX,
62 };
63 
64 enum msm_vfe_axi_stream_src {
65 	PIX_ENCODER,
66 	PIX_VIEWFINDER,
67 	PIX_VIDEO,
68 	CAMIF_RAW,
69 	IDEAL_RAW,
70 	RDI_INTF_0,
71 	RDI_INTF_1,
72 	RDI_INTF_2,
73 	VFE_AXI_SRC_MAX
74 };
75 
76 enum msm_vfe_frame_skip_pattern {
77 	NO_SKIP,
78 	EVERY_2FRAME,
79 	EVERY_3FRAME,
80 	EVERY_4FRAME,
81 	EVERY_5FRAME,
82 	EVERY_6FRAME,
83 	EVERY_7FRAME,
84 	EVERY_8FRAME,
85 	EVERY_16FRAME,
86 	EVERY_32FRAME,
87 	SKIP_ALL,
88 	SKIP_RANGE,
89 	MAX_SKIP,
90 };
91 
92 /*
93  * Define an unused period. When this period is set it means that the stream is
94  * stopped(i.e the pattern is 0). We don't track the current pattern, just the
95  * period defines what the pattern is, if period is this then pattern is 0 else
96  * pattern is 1
97  */
98 #define MSM_VFE_STREAM_STOP_PERIOD 15
99 
100 enum msm_isp_stats_type {
101 	MSM_ISP_STATS_AEC,   /* legacy based AEC */
102 	MSM_ISP_STATS_AF,    /* legacy based AF */
103 	MSM_ISP_STATS_AWB,   /* legacy based AWB */
104 	MSM_ISP_STATS_RS,    /* legacy based RS */
105 	MSM_ISP_STATS_CS,    /* legacy based CS */
106 	MSM_ISP_STATS_IHIST, /* legacy based HIST */
107 	MSM_ISP_STATS_SKIN,  /* legacy based SKIN */
108 	MSM_ISP_STATS_BG,    /* Bayer Grids */
109 	MSM_ISP_STATS_BF,    /* Bayer Focus */
110 	MSM_ISP_STATS_BE,    /* Bayer Exposure*/
111 	MSM_ISP_STATS_BHIST, /* Bayer Hist */
112 	MSM_ISP_STATS_BF_SCALE,  /* Bayer Focus scale */
113 	MSM_ISP_STATS_HDR_BE,    /* HDR Bayer Exposure */
114 	MSM_ISP_STATS_HDR_BHIST, /* HDR Bayer Hist */
115 	MSM_ISP_STATS_AEC_BG,   /* AEC BG */
116 	MSM_ISP_STATS_MAX    /* MAX */
117 };
118 
119 /*
120  * @stats_type_mask: Stats type mask (enum msm_isp_stats_type).
121  * @stream_src_mask: Stream src mask (enum msm_vfe_axi_stream_src)
122  * @skip_mode: skip pattern, if skip mode is range only then min/max is used
123  * @min_frame_id: minimum frame id (valid only if skip_mode = RANGE)
124  * @max_frame_id: maximum frame id (valid only if skip_mode = RANGE)
125 */
126 struct msm_isp_sw_framskip {
127 	uint32_t stats_type_mask;
128 	uint32_t stream_src_mask;
129 	enum msm_vfe_frame_skip_pattern skip_mode;
130 	uint32_t min_frame_id;
131 	uint32_t max_frame_id;
132 };
133 
134 enum msm_vfe_testgen_color_pattern {
135 	COLOR_BAR_8_COLOR,
136 	UNICOLOR_WHITE,
137 	UNICOLOR_YELLOW,
138 	UNICOLOR_CYAN,
139 	UNICOLOR_GREEN,
140 	UNICOLOR_MAGENTA,
141 	UNICOLOR_RED,
142 	UNICOLOR_BLUE,
143 	UNICOLOR_BLACK,
144 	MAX_COLOR,
145 };
146 
147 enum msm_vfe_camif_input {
148 	CAMIF_DISABLED,
149 	CAMIF_PAD_REG_INPUT,
150 	CAMIF_MIDDI_INPUT,
151 	CAMIF_MIPI_INPUT,
152 };
153 
154 struct msm_vfe_fetch_engine_cfg {
155 	uint32_t input_format;
156 	uint32_t buf_width;
157 	uint32_t buf_height;
158 	uint32_t fetch_width;
159 	uint32_t fetch_height;
160 	uint32_t x_offset;
161 	uint32_t y_offset;
162 	uint32_t buf_stride;
163 };
164 
165 enum msm_vfe_camif_output_format {
166 	CAMIF_QCOM_RAW,
167 	CAMIF_MIPI_RAW,
168 	CAMIF_PLAIN_8,
169 	CAMIF_PLAIN_16,
170 	CAMIF_MAX_FORMAT,
171 };
172 
173 /*
174  * Camif output general configuration
175  */
176 struct msm_vfe_camif_subsample_cfg {
177 	uint32_t irq_subsample_period;
178 	uint32_t irq_subsample_pattern;
179 	uint32_t sof_counter_step;
180 	uint32_t pixel_skip;
181 	uint32_t line_skip;
182 	uint32_t first_line;
183 	uint32_t last_line;
184 	uint32_t first_pixel;
185 	uint32_t last_pixel;
186 	enum msm_vfe_camif_output_format output_format;
187 };
188 
189 /*
190  * Camif frame and window configuration
191  */
192 struct msm_vfe_camif_cfg {
193 	uint32_t lines_per_frame;
194 	uint32_t pixels_per_line;
195 	uint32_t first_pixel;
196 	uint32_t last_pixel;
197 	uint32_t first_line;
198 	uint32_t last_line;
199 	uint32_t epoch_line0;
200 	uint32_t epoch_line1;
201 	uint32_t is_split;
202 	enum msm_vfe_camif_input camif_input;
203 	struct msm_vfe_camif_subsample_cfg subsample_cfg;
204 };
205 
206 struct msm_vfe_testgen_cfg {
207 	uint32_t lines_per_frame;
208 	uint32_t pixels_per_line;
209 	uint32_t v_blank;
210 	uint32_t h_blank;
211 	enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern;
212 	uint32_t rotate_period;
213 	enum msm_vfe_testgen_color_pattern color_bar_pattern;
214 	uint32_t burst_num_frame;
215 };
216 
217 enum msm_vfe_inputmux {
218 	CAMIF,
219 	TESTGEN,
220 	EXTERNAL_READ,
221 };
222 
223 enum msm_vfe_stats_composite_group {
224 	STATS_COMPOSITE_GRP_NONE,
225 	STATS_COMPOSITE_GRP_1,
226 	STATS_COMPOSITE_GRP_2,
227 	STATS_COMPOSITE_GRP_MAX,
228 };
229 
230 enum msm_vfe_hvx_streaming_cmd {
231 	HVX_DISABLE,
232 	HVX_ONE_WAY,
233 	HVX_ROUND_TRIP
234 };
235 
236 struct msm_vfe_pix_cfg {
237 	struct msm_vfe_camif_cfg camif_cfg;
238 	struct msm_vfe_testgen_cfg testgen_cfg;
239 	struct msm_vfe_fetch_engine_cfg fetch_engine_cfg;
240 	enum msm_vfe_inputmux input_mux;
241 	enum ISP_START_PIXEL_PATTERN pixel_pattern;
242 	uint32_t input_format;
243 	enum msm_vfe_hvx_streaming_cmd hvx_cmd;
244 	uint32_t is_split;
245 };
246 
247 struct msm_vfe_rdi_cfg {
248 	uint8_t cid;
249 	uint8_t frame_based;
250 };
251 
252 struct msm_vfe_input_cfg {
253 	union {
254 		struct msm_vfe_pix_cfg pix_cfg;
255 		struct msm_vfe_rdi_cfg rdi_cfg;
256 	} d;
257 	enum msm_vfe_input_src input_src;
258 	uint32_t input_pix_clk;
259 };
260 
261 struct msm_vfe_fetch_eng_start {
262 	uint32_t session_id;
263 	uint32_t stream_id;
264 	uint32_t buf_idx;
265 	uint8_t  offline_mode;
266 	uint32_t fd;
267 	uint32_t buf_addr;
268 	uint32_t frame_id;
269 };
270 
271 struct msm_vfe_axi_plane_cfg {
272 	uint32_t output_width; /*Include padding*/
273 	uint32_t output_height;
274 	uint32_t output_stride;
275 	uint32_t output_scan_lines;
276 	uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/
277 	uint32_t plane_addr_offset;
278 	uint8_t csid_src; /*RDI 0-2*/
279 	uint8_t rdi_cid;/*CID 1-16*/
280 };
281 
282 enum msm_stream_memory_input_t {
283 	MEMORY_INPUT_DISABLED,
284 	MEMORY_INPUT_ENABLED
285 };
286 
287 struct msm_vfe_axi_stream_request_cmd {
288 	uint32_t session_id;
289 	uint32_t stream_id;
290 	uint32_t vt_enable;
291 	uint32_t output_format;/*Planar/RAW/Misc*/
292 	enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/
293 	struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
294 
295 	uint32_t burst_count;
296 	uint32_t hfr_mode;
297 	uint8_t frame_base;
298 
299 	uint32_t init_frame_drop; /*MAX 31 Frames*/
300 	enum msm_vfe_frame_skip_pattern frame_skip_pattern;
301 	uint8_t buf_divert; /* if TRUE no vb2 buf done. */
302 	/*Return values*/
303 	uint32_t axi_stream_handle;
304 	uint32_t controllable_output;
305 	uint32_t burst_len;
306 	/* Flag indicating memory input stream */
307 	enum msm_stream_memory_input_t memory_input;
308 };
309 
310 struct msm_vfe_axi_stream_release_cmd {
311 	uint32_t stream_handle;
312 };
313 
314 enum msm_vfe_axi_stream_cmd {
315 	STOP_STREAM,
316 	START_STREAM,
317 	STOP_IMMEDIATELY,
318 };
319 
320 struct msm_vfe_axi_stream_cfg_cmd {
321 	uint8_t num_streams;
322 	uint32_t stream_handle[VFE_AXI_SRC_MAX];
323 	enum msm_vfe_axi_stream_cmd cmd;
324 	uint8_t sync_frame_id_src;
325 };
326 
327 enum msm_vfe_axi_stream_update_type {
328 	ENABLE_STREAM_BUF_DIVERT,
329 	DISABLE_STREAM_BUF_DIVERT,
330 	UPDATE_STREAM_FRAMEDROP_PATTERN,
331 	UPDATE_STREAM_STATS_FRAMEDROP_PATTERN,
332 	UPDATE_STREAM_AXI_CONFIG,
333 	UPDATE_STREAM_REQUEST_FRAMES,
334 	UPDATE_STREAM_ADD_BUFQ,
335 	UPDATE_STREAM_REMOVE_BUFQ,
336 	UPDATE_STREAM_SW_FRAME_DROP,
337 };
338 
339 enum msm_vfe_iommu_type {
340 	IOMMU_ATTACH,
341 	IOMMU_DETACH,
342 };
343 
344 enum msm_vfe_buff_queue_id {
345 	VFE_BUF_QUEUE_DEFAULT,
346 	VFE_BUF_QUEUE_SHARED,
347 	VFE_BUF_QUEUE_MAX,
348 };
349 
350 struct msm_vfe_axi_stream_cfg_update_info {
351 	uint32_t stream_handle;
352 	uint32_t output_format;
353 	uint32_t user_stream_id;
354 	uint32_t frame_id;
355 	enum msm_vfe_frame_skip_pattern skip_pattern;
356 	struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
357 	struct msm_isp_sw_framskip sw_skip_info;
358 };
359 
360 struct msm_vfe_axi_halt_cmd {
361 	uint32_t stop_camif;
362 	uint32_t overflow_detected;
363 	uint32_t blocking_halt;
364 };
365 
366 struct msm_vfe_axi_reset_cmd {
367 	uint32_t blocking;
368 	uint32_t frame_id;
369 };
370 
371 struct msm_vfe_axi_restart_cmd {
372 	uint32_t enable_camif;
373 };
374 
375 struct msm_vfe_axi_stream_update_cmd {
376 	uint32_t num_streams;
377 	enum msm_vfe_axi_stream_update_type update_type;
378 	struct msm_vfe_axi_stream_cfg_update_info
379 					update_info[MSM_ISP_STATS_MAX];
380 };
381 
382 struct msm_vfe_smmu_attach_cmd {
383 	uint32_t security_mode;
384 	uint32_t iommu_attach_mode;
385 };
386 
387 struct msm_vfe_stats_stream_request_cmd {
388 	uint32_t session_id;
389 	uint32_t stream_id;
390 	enum msm_isp_stats_type stats_type;
391 	uint32_t composite_flag;
392 	uint32_t framedrop_pattern;
393 	uint32_t init_frame_drop; /*MAX 31 Frames*/
394 	uint32_t irq_subsample_pattern;
395 	uint32_t buffer_offset;
396 	uint32_t stream_handle;
397 };
398 
399 struct msm_vfe_stats_stream_release_cmd {
400 	uint32_t stream_handle;
401 };
402 struct msm_vfe_stats_stream_cfg_cmd {
403 	uint8_t num_streams;
404 	uint32_t stream_handle[MSM_ISP_STATS_MAX];
405 	uint8_t enable;
406 	uint32_t stats_burst_len;
407 };
408 
409 enum msm_vfe_reg_cfg_type {
410 	VFE_WRITE,
411 	VFE_WRITE_MB,
412 	VFE_READ,
413 	VFE_CFG_MASK,
414 	VFE_WRITE_DMI_16BIT,
415 	VFE_WRITE_DMI_32BIT,
416 	VFE_WRITE_DMI_64BIT,
417 	VFE_READ_DMI_16BIT,
418 	VFE_READ_DMI_32BIT,
419 	VFE_READ_DMI_64BIT,
420 	GET_MAX_CLK_RATE,
421 	GET_CLK_RATES,
422 	GET_ISP_ID,
423 	VFE_HW_UPDATE_LOCK,
424 	VFE_HW_UPDATE_UNLOCK,
425 	SET_WM_UB_SIZE,
426 	SET_UB_POLICY,
427 };
428 
429 struct msm_vfe_cfg_cmd2 {
430 	uint16_t num_cfg;
431 	uint16_t cmd_len;
432 	void __user *cfg_data;
433 	void __user *cfg_cmd;
434 };
435 
436 struct msm_vfe_cfg_cmd_list {
437 	struct msm_vfe_cfg_cmd2      cfg_cmd;
438 	struct msm_vfe_cfg_cmd_list *next;
439 	uint32_t                     next_size;
440 };
441 
442 struct msm_vfe_reg_rw_info {
443 	uint32_t reg_offset;
444 	uint32_t cmd_data_offset;
445 	uint32_t len;
446 };
447 
448 struct msm_vfe_reg_mask_info {
449 	uint32_t reg_offset;
450 	uint32_t mask;
451 	uint32_t val;
452 };
453 
454 struct msm_vfe_reg_dmi_info {
455 	uint32_t hi_tbl_offset; /*Optional*/
456 	uint32_t lo_tbl_offset; /*Required*/
457 	uint32_t len;
458 };
459 
460 struct msm_vfe_reg_cfg_cmd {
461 	union {
462 		struct msm_vfe_reg_rw_info rw_info;
463 		struct msm_vfe_reg_mask_info mask_info;
464 		struct msm_vfe_reg_dmi_info dmi_info;
465 	} u;
466 
467 	enum msm_vfe_reg_cfg_type cmd_type;
468 };
469 
470 enum vfe_sd_type {
471 	VFE_SD_0 = 0,
472 	VFE_SD_1,
473 	VFE_SD_COMMON,
474 	VFE_SD_MAX,
475 };
476 
477 /* When you change the value below, check for the sof event_data size.
478  * V4l2 limits payload to 64 bytes */
479 #define MS_NUM_SLAVE_MAX 1
480 
481 /* Usecases when 2 HW need to be related or synced */
482 enum msm_vfe_dual_hw_type {
483 	DUAL_NONE = 0,
484 	DUAL_HW_VFE_SPLIT = 1,
485 	DUAL_HW_MASTER_SLAVE = 2,
486 };
487 
488 /* Type for 2 INTF when used in Master-Slave mode */
489 enum msm_vfe_dual_hw_ms_type {
490 	MS_TYPE_NONE,
491 	MS_TYPE_MASTER,
492 	MS_TYPE_SLAVE,
493 };
494 
495 struct msm_isp_set_dual_hw_ms_cmd {
496 	uint8_t num_src;
497 	/* Each session can be only one type but multiple intf if YUV cam */
498 	enum msm_vfe_dual_hw_ms_type dual_hw_ms_type;
499 	/* Primary intf is mostly associated with preview.
500 	 * This primary intf SOF frame_id and timestamp is tracked
501 	 * and used to calculate delta */
502 	enum msm_vfe_input_src primary_intf;
503 	/* input_src array indicates other input INTF that may be Master/Slave.
504 	 * For these additional intf, frame_id and timestamp are not saved.
505 	 * However, if these are slaves then they will still get their
506 	 * frame_id from Master */
507 	enum msm_vfe_input_src input_src[VFE_SRC_MAX];
508 	uint32_t sof_delta_threshold; /* In milliseconds. Sent for Master */
509 };
510 
511 enum msm_isp_buf_type {
512 	ISP_PRIVATE_BUF,
513 	ISP_SHARE_BUF,
514 	MAX_ISP_BUF_TYPE,
515 };
516 
517 struct msm_isp_unmap_buf_req {
518 	uint32_t fd;
519 };
520 
521 struct msm_isp_buf_request {
522 	uint32_t session_id;
523 	uint32_t stream_id;
524 	uint8_t num_buf;
525 	uint32_t handle;
526 	enum msm_isp_buf_type buf_type;
527 };
528 
529 struct msm_isp_qbuf_plane {
530 	uint32_t addr;
531 	uint32_t offset;
532 	uint32_t length;
533 };
534 
535 struct msm_isp_qbuf_buffer {
536 	struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM];
537 	uint32_t num_planes;
538 };
539 
540 struct msm_isp_qbuf_info {
541 	uint32_t handle;
542 	int32_t buf_idx;
543 	/*Only used for prepare buffer*/
544 	struct msm_isp_qbuf_buffer buffer;
545 	/*Only used for diverted buffer*/
546 	uint32_t dirty_buf;
547 };
548 
549 struct msm_isp_clk_rates {
550 	uint32_t svs_rate;
551 	uint32_t nominal_rate;
552 	uint32_t high_rate;
553 };
554 
555 struct msm_vfe_axi_src_state {
556 	enum msm_vfe_input_src input_src;
557 	uint32_t src_active;
558 	uint32_t src_frame_id;
559 };
560 
561 enum msm_isp_event_mask_index {
562 	ISP_EVENT_MASK_INDEX_STATS_NOTIFY		= 0,
563 	ISP_EVENT_MASK_INDEX_ERROR			= 1,
564 	ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT		= 2,
565 	ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE		= 3,
566 	ISP_EVENT_MASK_INDEX_REG_UPDATE			= 4,
567 	ISP_EVENT_MASK_INDEX_SOF			= 5,
568 	ISP_EVENT_MASK_INDEX_BUF_DIVERT			= 6,
569 	ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY		= 7,
570 	ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE		= 8,
571 	ISP_EVENT_MASK_INDEX_BUF_DONE			= 9,
572 	ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING		= 10,
573 	ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH		= 11,
574 	ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR		= 12,
575 };
576 
577 
578 #define ISP_EVENT_SUBS_MASK_NONE			0
579 
580 #define ISP_EVENT_SUBS_MASK_STATS_NOTIFY \
581 			(1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY)
582 
583 #define ISP_EVENT_SUBS_MASK_ERROR \
584 			(1 << ISP_EVENT_MASK_INDEX_ERROR)
585 
586 #define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT \
587 			(1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT)
588 
589 #define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE \
590 			(1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE)
591 
592 #define ISP_EVENT_SUBS_MASK_REG_UPDATE \
593 			(1 << ISP_EVENT_MASK_INDEX_REG_UPDATE)
594 
595 #define ISP_EVENT_SUBS_MASK_SOF \
596 			(1 << ISP_EVENT_MASK_INDEX_SOF)
597 
598 #define ISP_EVENT_SUBS_MASK_BUF_DIVERT \
599 			(1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT)
600 
601 #define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY \
602 			(1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY)
603 
604 #define ISP_EVENT_SUBS_MASK_FE_READ_DONE \
605 			(1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE)
606 
607 #define ISP_EVENT_SUBS_MASK_BUF_DONE \
608 			(1 << ISP_EVENT_MASK_INDEX_BUF_DONE)
609 
610 #define ISP_EVENT_SUBS_MASK_REG_UPDATE_MISSING \
611 			(1 << ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING)
612 
613 #define ISP_EVENT_SUBS_MASK_PING_PONG_MISMATCH \
614 			(1 << ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH)
615 
616 #define ISP_EVENT_SUBS_MASK_BUF_FATAL_ERROR \
617 			(1 << ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR)
618 
619 enum msm_isp_event_idx {
620 	ISP_REG_UPDATE        = 0,
621 	ISP_EPOCH_0           = 1,
622 	ISP_EPOCH_1           = 2,
623 	ISP_START_ACK         = 3,
624 	ISP_STOP_ACK          = 4,
625 	ISP_IRQ_VIOLATION     = 5,
626 	ISP_STATS_OVERFLOW    = 6,
627 	ISP_BUF_DONE          = 7,
628 	ISP_FE_RD_DONE        = 8,
629 	ISP_IOMMU_P_FAULT     = 9,
630 	ISP_ERROR             = 10,
631 	ISP_HW_FATAL_ERROR      = 11,
632 	ISP_PING_PONG_MISMATCH = 12,
633 	ISP_REG_UPDATE_MISSING = 13,
634 	ISP_BUF_FATAL_ERROR = 14,
635 	ISP_EVENT_MAX         = 15
636 };
637 
638 #define ISP_EVENT_OFFSET          8
639 #define ISP_EVENT_BASE            (V4L2_EVENT_PRIVATE_START)
640 #define ISP_BUF_EVENT_BASE        (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET))
641 #define ISP_STATS_EVENT_BASE      (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET))
642 #define ISP_CAMIF_EVENT_BASE      (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET))
643 #define ISP_STREAM_EVENT_BASE     (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET))
644 #define ISP_EVENT_REG_UPDATE      (ISP_EVENT_BASE + ISP_REG_UPDATE)
645 #define ISP_EVENT_EPOCH_0         (ISP_EVENT_BASE + ISP_EPOCH_0)
646 #define ISP_EVENT_EPOCH_1         (ISP_EVENT_BASE + ISP_EPOCH_1)
647 #define ISP_EVENT_START_ACK       (ISP_EVENT_BASE + ISP_START_ACK)
648 #define ISP_EVENT_STOP_ACK        (ISP_EVENT_BASE + ISP_STOP_ACK)
649 #define ISP_EVENT_IRQ_VIOLATION   (ISP_EVENT_BASE + ISP_IRQ_VIOLATION)
650 #define ISP_EVENT_STATS_OVERFLOW  (ISP_EVENT_BASE + ISP_STATS_OVERFLOW)
651 #define ISP_EVENT_ERROR           (ISP_EVENT_BASE + ISP_ERROR)
652 #define ISP_EVENT_SOF             (ISP_CAMIF_EVENT_BASE)
653 #define ISP_EVENT_EOF             (ISP_CAMIF_EVENT_BASE + 1)
654 #define ISP_EVENT_BUF_DONE        (ISP_EVENT_BASE + ISP_BUF_DONE)
655 #define ISP_EVENT_BUF_DIVERT      (ISP_BUF_EVENT_BASE)
656 #define ISP_EVENT_STATS_NOTIFY    (ISP_STATS_EVENT_BASE)
657 #define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX)
658 #define ISP_EVENT_FE_READ_DONE    (ISP_EVENT_BASE + ISP_FE_RD_DONE)
659 #define ISP_EVENT_IOMMU_P_FAULT   (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT)
660 #define ISP_EVENT_HW_FATAL_ERROR  (ISP_EVENT_BASE + ISP_HW_FATAL_ERROR)
661 #define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH)
662 #define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING)
663 #define ISP_EVENT_BUF_FATAL_ERROR (ISP_EVENT_BASE + ISP_BUF_FATAL_ERROR)
664 #define ISP_EVENT_STREAM_UPDATE_DONE   (ISP_STREAM_EVENT_BASE)
665 
666 /* The msm_v4l2_event_data structure should match the
667  * v4l2_event.u.data field.
668  * should not exceed 64 bytes */
669 
670 struct msm_isp_buf_event {
671 	uint32_t session_id;
672 	uint32_t stream_id;
673 	uint32_t handle;
674 	uint32_t output_format;
675 	int8_t buf_idx;
676 };
677 struct msm_isp_fetch_eng_event {
678 	uint32_t session_id;
679 	uint32_t stream_id;
680 	uint32_t handle;
681 	uint32_t fd;
682 	int8_t buf_idx;
683 	int8_t offline_mode;
684 };
685 struct msm_isp_stats_event {
686 	uint32_t stats_mask;                        /* 4 bytes */
687 	uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX];  /* 11 bytes */
688 };
689 
690 struct msm_isp_stream_ack {
691 	uint32_t session_id;
692 	uint32_t stream_id;
693 	uint32_t handle;
694 };
695 
696 enum msm_vfe_error_type {
697 	ISP_ERROR_NONE,
698 	ISP_ERROR_CAMIF,
699 	ISP_ERROR_BUS_OVERFLOW,
700 	ISP_ERROR_RETURN_EMPTY_BUFFER,
701 	ISP_ERROR_FRAME_ID_MISMATCH,
702 	ISP_ERROR_MAX,
703 };
704 
705 struct msm_isp_error_info {
706 	enum msm_vfe_error_type err_type;
707 	uint32_t session_id;
708 	uint32_t stream_id;
709 	uint32_t stream_id_mask;
710 };
711 
712 /* This structure reports delta between master and slave */
713 struct msm_isp_ms_delta_info {
714 	uint8_t num_delta_info;
715 	uint32_t delta[MS_NUM_SLAVE_MAX];
716 };
717 
718 /* This is sent in EPOCH irq */
719 struct msm_isp_output_info {
720 	uint8_t regs_not_updated;
721 	/* mask with bufq_handle for regs not updated or return empty */
722 	uint16_t output_err_mask;
723 	/* mask with stream_idx for get_buf failed */
724 	uint8_t stream_framedrop_mask;
725 	/* mask with stats stream_idx for get_buf failed */
726 	uint16_t stats_framedrop_mask;
727 	/* delta between master and slave */
728 };
729 
730 /* This structure is piggybacked with SOF event */
731 struct msm_isp_sof_info {
732 	uint8_t regs_not_updated;
733 	/* mask with AXI_SRC for regs not updated */
734 	uint16_t reg_update_fail_mask;
735 	/* mask with bufq_handle for get_buf failed */
736 	uint32_t stream_get_buf_fail_mask;
737 	/* mask with stats stream_idx for get_buf failed */
738 	uint16_t stats_get_buf_fail_mask;
739 	/* delta between master and slave */
740 	struct msm_isp_ms_delta_info ms_delta_info;
741 };
742 
743 struct msm_isp_event_data {
744 	/*Wall clock except for buffer divert events
745 	 *which use monotonic clock
746 	 */
747 	struct timeval timestamp;
748 	/* Monotonic timestamp since bootup */
749 	struct timeval mono_timestamp;
750 	uint32_t frame_id;
751 	union {
752 		/* Sent for Stats_Done event */
753 		struct msm_isp_stats_event stats;
754 		/* Sent for Buf_Divert event */
755 		struct msm_isp_buf_event buf_done;
756 		/* Sent for offline fetch done event */
757 		struct msm_isp_fetch_eng_event fetch_done;
758 		/* Sent for Error_Event */
759 		struct msm_isp_error_info error_info;
760 		/*
761 		 * This struct needs to be removed once
762 		 * userspace switches to sof_info
763 		 */
764 		struct msm_isp_output_info output_info;
765 		/* Sent for SOF event */
766 		struct msm_isp_sof_info sof_info;
767 	} u; /* union can have max 52 bytes */
768 };
769 
770 #ifdef CONFIG_COMPAT
771 struct msm_isp_event_data32 {
772 	struct compat_timeval timestamp;
773 	struct compat_timeval mono_timestamp;
774 	uint32_t frame_id;
775 	union {
776 		struct msm_isp_stats_event stats;
777 		struct msm_isp_buf_event buf_done;
778 		struct msm_isp_fetch_eng_event fetch_done;
779 		struct msm_isp_error_info error_info;
780 		struct msm_isp_output_info output_info;
781 		struct msm_isp_sof_info sof_info;
782 	} u;
783 };
784 #endif
785 
786 #define V4L2_PIX_FMT_QBGGR8  v4l2_fourcc('Q', 'B', 'G', '8')
787 #define V4L2_PIX_FMT_QGBRG8  v4l2_fourcc('Q', 'G', 'B', '8')
788 #define V4L2_PIX_FMT_QGRBG8  v4l2_fourcc('Q', 'G', 'R', '8')
789 #define V4L2_PIX_FMT_QRGGB8  v4l2_fourcc('Q', 'R', 'G', '8')
790 #define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0')
791 #define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0')
792 #define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0')
793 #define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0')
794 #define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2')
795 #define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2')
796 #define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2')
797 #define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2')
798 #define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4')
799 #define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4')
800 #define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4')
801 #define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4')
802 #define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0')
803 #define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0')
804 #define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0')
805 #define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0')
806 #define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4')
807 #define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1')
808 #define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T')
809 #define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') /* 14 BGBG.GRGR.*/
810 #define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') /* 14 GBGB.RGRG.*/
811 #define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') /* 14 GRGR.BGBG.*/
812 #define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') /* 14 RGRG.GBGB.*/
813 
814 #define VIDIOC_MSM_VFE_REG_CFG \
815 	_IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_vfe_cfg_cmd2)
816 
817 #define VIDIOC_MSM_ISP_REQUEST_BUF \
818 	_IOWR('V', BASE_VIDIOC_PRIVATE+1, struct msm_isp_buf_request)
819 
820 #define VIDIOC_MSM_ISP_ENQUEUE_BUF \
821 	_IOWR('V', BASE_VIDIOC_PRIVATE+2, struct msm_isp_qbuf_info)
822 
823 #define VIDIOC_MSM_ISP_RELEASE_BUF \
824 	_IOWR('V', BASE_VIDIOC_PRIVATE+3, struct msm_isp_buf_request)
825 
826 #define VIDIOC_MSM_ISP_REQUEST_STREAM \
827 	_IOWR('V', BASE_VIDIOC_PRIVATE+4, struct msm_vfe_axi_stream_request_cmd)
828 
829 #define VIDIOC_MSM_ISP_CFG_STREAM \
830 	_IOWR('V', BASE_VIDIOC_PRIVATE+5, struct msm_vfe_axi_stream_cfg_cmd)
831 
832 #define VIDIOC_MSM_ISP_RELEASE_STREAM \
833 	_IOWR('V', BASE_VIDIOC_PRIVATE+6, struct msm_vfe_axi_stream_release_cmd)
834 
835 #define VIDIOC_MSM_ISP_INPUT_CFG \
836 	_IOWR('V', BASE_VIDIOC_PRIVATE+7, struct msm_vfe_input_cfg)
837 
838 #define VIDIOC_MSM_ISP_SET_SRC_STATE \
839 	_IOWR('V', BASE_VIDIOC_PRIVATE+8, struct msm_vfe_axi_src_state)
840 
841 #define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \
842 	_IOWR('V', BASE_VIDIOC_PRIVATE+9, \
843 	struct msm_vfe_stats_stream_request_cmd)
844 
845 #define VIDIOC_MSM_ISP_CFG_STATS_STREAM \
846 	_IOWR('V', BASE_VIDIOC_PRIVATE+10, struct msm_vfe_stats_stream_cfg_cmd)
847 
848 #define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \
849 	_IOWR('V', BASE_VIDIOC_PRIVATE+11, \
850 	struct msm_vfe_stats_stream_release_cmd)
851 
852 #define VIDIOC_MSM_ISP_REG_UPDATE_CMD \
853 	_IOWR('V', BASE_VIDIOC_PRIVATE+12, enum msm_vfe_input_src)
854 
855 #define VIDIOC_MSM_ISP_UPDATE_STREAM \
856 	_IOWR('V', BASE_VIDIOC_PRIVATE+13, struct msm_vfe_axi_stream_update_cmd)
857 
858 #define VIDIOC_MSM_VFE_REG_LIST_CFG \
859 	_IOWR('V', BASE_VIDIOC_PRIVATE+14, struct msm_vfe_cfg_cmd_list)
860 
861 #define VIDIOC_MSM_ISP_SMMU_ATTACH \
862 	_IOWR('V', BASE_VIDIOC_PRIVATE+15, struct msm_vfe_smmu_attach_cmd)
863 
864 #define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM \
865 	_IOWR('V', BASE_VIDIOC_PRIVATE+16, struct msm_vfe_axi_stream_update_cmd)
866 
867 #define VIDIOC_MSM_ISP_AXI_HALT \
868 	_IOWR('V', BASE_VIDIOC_PRIVATE+17, struct msm_vfe_axi_halt_cmd)
869 
870 #define VIDIOC_MSM_ISP_AXI_RESET \
871 	_IOWR('V', BASE_VIDIOC_PRIVATE+18, struct msm_vfe_axi_reset_cmd)
872 
873 #define VIDIOC_MSM_ISP_AXI_RESTART \
874 	_IOWR('V', BASE_VIDIOC_PRIVATE+19, struct msm_vfe_axi_restart_cmd)
875 
876 #define VIDIOC_MSM_ISP_FETCH_ENG_START \
877 	_IOWR('V', BASE_VIDIOC_PRIVATE+20, struct msm_vfe_fetch_eng_start)
878 
879 #define VIDIOC_MSM_ISP_DEQUEUE_BUF \
880 	_IOWR('V', BASE_VIDIOC_PRIVATE+21, struct msm_isp_qbuf_info)
881 
882 #define VIDIOC_MSM_ISP_SET_DUAL_HW_MASTER_SLAVE \
883 	_IOWR('V', BASE_VIDIOC_PRIVATE+22, struct msm_isp_set_dual_hw_ms_cmd)
884 
885 #define VIDIOC_MSM_ISP_MAP_BUF_START_FE \
886 	_IOWR('V', BASE_VIDIOC_PRIVATE+23, struct msm_vfe_fetch_eng_start)
887 
888 #define VIDIOC_MSM_ISP_UNMAP_BUF \
889 	_IOWR('V', BASE_VIDIOC_PRIVATE+24, struct msm_isp_unmap_buf_req)
890 
891 #endif /* __MSMB_ISP__ */
892