1; Morpho Technologies MT Arch description. -*- Scheme -*- 2; Copyright 2001, 2007, 2009 Free Software Foundation, Inc. 3; 4; Contributed by Red Hat Inc; developed under contract from 5; Morpho Technologies. 6; 7; This file is part of the GNU Binutils. 8; 9; This program is free software; you can redistribute it and/or modify 10; it under the terms of the GNU General Public License as published by 11; the Free Software Foundation; either version 3 of the License, or 12; (at your option) any later version. 13; 14; This program is distributed in the hope that it will be useful, 15; but WITHOUT ANY WARRANTY; without even the implied warranty of 16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17; GNU General Public License for more details. 18; 19; You should have received a copy of the GNU General Public License 20; along with this program; if not, write to the Free Software 21; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 22; MA 02110-1301, USA. 23 24(include "simplify.inc") 25 26;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 27;; Define The Architecture, Attributes, ISA, CPU, Machine, And Model. ;; 28;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 29 30; define-arch must appear first 31(define-arch 32 (name mt) ; name of cpu family 33 (comment "Morpho Technologies mRISC family") 34 (default-alignment aligned) 35 (insn-lsb0? #t) 36 (machs ms1 ms1-003 ms2) 37 (isas mt) 38) 39 40; Instruction set parameters. 41 42(define-isa 43 (name mt) 44 (comment "Morpho Technologies MT ISA") 45 (default-insn-word-bitsize 32) 46 (default-insn-bitsize 32) 47 (base-insn-bitsize 32) 48 (parallel-insns 2) 49) 50 51; Cpu family definitions. 52 53 54(define-cpu 55 ; cpu names must be distinct from the architecture name and machine names. 56 (name ms1bf) 57 (comment "Morpho Technologies mRISC family") 58 (endian big) 59 (word-bitsize 32) 60) 61 62(define-cpu 63 ; cpu names must be distinct from the architecture name and machine names. 64 (name ms1-003bf) 65 (comment "Morpho Technologies mRISC family") 66 (endian big) 67 (word-bitsize 32) 68) 69 70(define-cpu 71 ; cpu names must be distinct from the architecture name and machine names. 72 (name ms2bf) 73 (comment "Morpho Technologies mRISC family") 74 (endian big) 75 (word-bitsize 32) 76) 77 78(define-mach 79 (name ms1) 80 (comment "Morpho Technologies mrisc") 81 (cpu ms1bf) 82 (isas mt) 83) 84 85(define-mach 86 (name ms1-003) 87 (comment "Morpho Technologies mrisc") 88 (cpu ms1-003bf) 89 (isas mt) 90) 91 92(define-mach 93 (name ms2) 94 (comment "Morpho Technologies ms2") 95 (cpu ms2bf) 96 (isas mt) 97) 98 99 100; Model descriptions. 101; Can probably take the u-exec out. We'll see. 102(define-model 103 (name ms1) 104 (comment "Morpho Technologies mrisc") 105 (mach ms1) 106 (unit u-exec "Execution Unit" () 107 1 1 ; issue done 108 () ; state 109 () ; inputs 110 () ; outputs 111 () ; profile action (default) 112 ) 113) 114 115(define-model 116 (name ms1-003) 117 (comment "Morpho Technologies mrisc") 118 (mach ms1-003) 119 (unit u-exec "Execution Unit" () 120 1 1 ; issue done 121 () ; state 122 () ; inputs 123 () ; outputs 124 () ; profile action (default) 125 ) 126) 127 128(define-model 129 (name ms2) 130 (comment "Morpho Technologies ms2") 131 (mach ms2) 132 (unit u-exec "Execution Unit" () 133 1 1 ; issue done 134 () ; state 135 () ; inputs 136 () ; outputs 137 () ; profile action (default) 138 ) 139) 140 141; FIXME: It might simplify things to separate the execute process from the 142; one that updates the PC. 143 144 145;;;;;;;;;;;;;;;;;;;;;;;; 146;; Instruction Fields ;; 147;;;;;;;;;;;;;;;;;;;;;;;; 148 149; Attributes: 150; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) 151; ABS-ADDR: absolute address (for reloc and disassembly purposes?) 152; RESERVED: bits are not used to decode insn, must be all 0 153; RELOC: there is a relocation associated with this field (experiment) 154; 155; f-msys: Identify a a morphosys insns. 1 if msys, 0 if not. 156; f-opc: 6 bit opcode for non-morphosys instructions. 157; f-msopc: 6 bit opcode for morphosys instructions. 158; f-imm: flag to indicate use of an immediate operand. 1 if yes, 0 if no. 159; f-sr1: source resgister 1. (also used for MSYS insns) 160; f-sr2: source register 2. (also used for MSYS insns) 161; f-dr: destination register when located in bits 19:16. 162; f-drrr: destination register when located in bits 15:12. (also for MSYS insns) 163; f-imm16: 16 bit immediate value when not an offset. 164; f-imm16a: 16 bit immediate value when it's a pc-rel offset. 165; f-uu4a: unused 4 bit field. 166; f-uu4b: second unsed 4 bit field. 167; f-uu1: unused 1 bit field 168; f-uu12: unused 12 bit field. 169; f-uu16: unused 16 bit field. 170; f-uu24: unused 24 bit field. 171 172(dnf f-msys "morphosys insn flag" () 31 1) 173(dnf f-opc "opcode field" () 30 6) 174(dnf f-imm "immedate flag" () 24 1) 175(dnf f-uu24 "unused 24 bits" () 23 24) 176(dnf f-sr1 "sr1 register field" (ABS-ADDR) 23 4) 177(dnf f-sr2 "sr2 register field" (ABS-ADDR) 19 4) 178(dnf f-dr "dr register field" (ABS-ADDR) 19 4) 179(dnf f-drrr "drrr register field" (ABS-ADDR) 15 4) 180(dnf f-imm16u "unsigned 16 bit immediate" () 15 16) 181(df f-imm16s "signed 16 bit immediate" () 15 16 INT ((value pc) (add HI value 0)) ((value pc) (add HI value 0))) 182(dnf f-imm16a "pc-rel offset" (PCREL-ADDR) 15 16) 183(dnf f-uu4a "unused 4 bit field" () 19 4) 184(dnf f-uu4b "unused 4 bit field" () 23 4) 185(dnf f-uu12 "unused 12 bit field" () 11 12) 186(dnf f-uu8 "unused 8 bit field" () 15 8) 187(dnf f-uu16 "unused 16 bit field" () 15 16) 188(dnf f-uu1 "unused 1 bit field" () 7 1) 189 190; The following ifields are used exclusively for the MorphoSys instructions. 191; In a few cases, a bit field is used for something in addition to what its 192; name suggests. For the most part, the names are meaningful though. 193 194(dnf f-msopc "opcode field" () 30 5) 195(dnf f-uu-26-25 "unused 26 bits" () 25 26) 196(dnf f-mask "mask" () 25 16) 197(dnf f-bankaddr "bank address" () 25 13) 198(dnf f-rda "rda" () 25 1) 199(dnf f-uu-2-25 "unused bits 25 & 24" () 25 2) 200(dnf f-rbbc "Omega network configuration" () 25 2) 201(dnf f-perm "perm" () 25 2) 202(dnf f-mode "mode" () 25 2) 203(dnf f-uu-1-24 "testing" () 24 1) 204(dnf f-wr "wr" () 24 1) 205(dnf f-fbincr "fb incr" () 23 4) 206(dnf f-uu-2-23 "unused bits 23 and 22" () 23 2) 207(dnf f-xmode "xmode" () 23 1) 208(dnf f-a23 "a23" () 23 1) 209(dnf f-mask1 "mask1" () 22 3) 210(dnf f-cr "cr" () 22 3) 211(dnf f-type "type" () 21 2) 212(dnf f-incamt "increment amount" () 19 8) 213(dnf f-cbs "cbs" () 19 2) 214(dnf f-uu-1-19 "unused bit 19" () 19 1) 215(dnf f-ball "b_all" () 19 1) 216(dnf f-colnum "column number" () 18 3) 217(dnf f-brc "b_r_c" () 18 3) 218(dnf f-incr "incr" () 17 6) 219(dnf f-fbdisp "frame buffer displacement" () 15 6) 220(dnf f-uu-4-15 "unused bits 15,14,13,12" () 15 4) 221(dnf f-length "length" () 15 3) 222(dnf f-uu-1-15 "unused bit 15" () 15 1) 223(dnf f-rc "row/column context" () 15 1) 224(dnf f-rcnum "starting cell of cntxt mem." () 14 3) 225(dnf f-rownum "row number" () 14 3) 226(dnf f-cbx "cbx" () 14 3) 227(dnf f-id "id" () 14 1) 228(dnf f-size "size" () 13 14) 229(dnf f-rownum1 "row number" () 12 3) 230(dnf f-uu-3-11 "unused 3 bits (11-9)" () 11 3) 231(dnf f-rc1 "row/column context" () 11 1) 232(dnf f-ccb "ccb" () 11 1) 233(dnf f-cbrb "data-bus orientation" () 10 1) 234(dnf f-cdb "cdb" () 10 1) 235(dnf f-rownum2 "row number" () 9 3) 236(dnf f-cell "cell" () 9 3) 237(dnf f-uu-3-9 "unused 3 bits (9-7)" () 9 3) 238(dnf f-contnum "context number" () 8 9) 239(dnf f-uu-1-6 "unused bit 6" () 6 1) 240(dnf f-dup "dup" () 6 1) 241(dnf f-rc2 "rc2" () 6 1) 242(dnf f-ctxdisp "context displacement" () 5 6) 243 244; additional fields in ms2 245(dnf f-imm16l "loop count" () 23 16) 246(df f-loopo "loop offset" () 7 8 UINT 247 ((value pc) (srl SI value 2)) 248 ((value pc) (add SI (sll value 2) 8)) 249 ) 250(dnf f-cb1sel "cb1 select" () 25 3) 251(dnf f-cb2sel "cb2 select" () 22 3) 252(dnf f-cb1incr "cb1 increment" (SIGNED) 19 6) 253(dnf f-cb2incr "cb2 increment" (SIGNED) 13 6) 254(dnf f-rc3 "row/colum context" () 7 1) 255 256; The following is just for a test 257(dnf f-msysfrsr2 "sr2 for msys" () 19 4) 258(dnf f-brc2 "b_r_c2" () 14 3) 259(dnf f-ball2 "b_all2" () 15 1) 260 261 262;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 263;; Enumerations Of Instruction Fields ;; 264;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 265 266; insn-msys: bit 31. 1 for Morphosys Insns, 0 if not. 267(define-normal-insn-enum insn-msys "msys enums" () MSYS_ f-msys 268 (NO YES) 269) 270 271; insn-opc: bits 30 through 25 . Non-MorphoSys Instructions 272; Note - the documentation is wrong for the encoding of the DBNZ 273; instruction. It is actually 011110. See Issue 67699. 274(define-normal-insn-enum insn-opc "opc enums" () OPC_ f-opc 275 (ADD ADDU SUB SUBU MUL - - - 276 AND OR XOR NAND NOR XNOR LDUI - 277 LSL LSR ASR - - - - - 278 BRLT BRLE BREQ JMP JAL BRNEQ DBNZ LOOP 279 LDW STW - - - - - - 280 - - - - - - - - 281 EI DI SI RETI BREAK IFLUSH - - 282 ) 283) 284 285; insn-msopc: bits 30 through 26 . MorphoSys Instructions 286(define-normal-insn-enum insn-msopc "msopc enums" () MSOPC_ f-msopc 287 (LDCTXT LDFB STFB FBCB MFBCB FBCCI FBRCI FBCRI 288 FBRRI MFBCCI MFBRCI MFBCRI MFBRRI FBCBDR RCFBCB MRCFBCB 289 CBCAST DUPCBCAST WFBI WFB RCRISC FBCBINC RCXMODE INTLVR 290 WFBINC MWFBINC WFBINCR MWFBINCR FBCBINCS MFBCBINCS FBCBINCRS MFBCBINCRS 291 - - - - - - - - 292 ) 293) 294 295; insn-imm: bit 24. Immediate operand indicator. 296(define-normal-insn-enum insn-imm "imm enums" () IMM_ f-imm 297 ; This bit specifies whether and immediate operand will be present. 298 ; It's 1 if there is, 0 if there is not. 299 (NO YES) 300) 301;;;;;;;;;;;;;;;; 302;; Attributes ;; 303;;;;;;;;;;;;;;;; 304 305; Might not need this. Keep if for the sim just in case. 306;(define-attr 307; (for insn) 308; (type boolean) 309; (name EXT-SKIP-INSN) 310; (comment "instruction is a PAGE, LOADL or LOADH instruction") 311;) 312 313(define-attr 314 (for insn) 315 (type boolean) 316 (name LOAD-DELAY) 317 (comment "insn has a load delay") 318) 319 320(define-attr 321 (for insn) 322 (type boolean) 323 (name MEMORY-ACCESS) 324 (comment "insn performs a memory access") 325) 326 327(define-attr 328 (for insn) 329 (type boolean) 330 (name AL-INSN) 331 (comment "insn is an arithmetic or logic insn.") 332) 333 334(define-attr 335 (for insn) 336 (type boolean) 337 (name IO-INSN) 338 (comment "insn performs an I/O operation") 339) 340 341(define-attr 342 (for insn) 343 (type boolean) 344 (name BR-INSN) 345 (comment "insn performs an I/O operation") 346) 347 348(define-attr 349 (for insn) 350 (type boolean) 351 (name JAL-HAZARD) 352 (comment "insn has jal-like hazard") 353) 354 355(define-pmacro (define-reg-use-attr regfield) 356 (define-attr 357 (for insn) 358 (type boolean) 359 (name (.sym "USES-" (.upcase regfield))) 360 (comment ("insn accesses register operand " regfield)))) 361 362(define-reg-use-attr "frdr") 363(define-reg-use-attr "frdrrr") 364(define-reg-use-attr "frsr1") 365(define-reg-use-attr "frsr2") 366 367 368; Might not need this. Keep it for the sim just in case. 369(define-attr 370 (for insn) 371 (type boolean) 372 (name SKIPA) 373 (comment "instruction is a SKIP instruction") 374) 375 376 377;;;;;;;;;;;;;;;;;;;;; 378;; Hardware Pieces ;; 379;;;;;;;;;;;;;;;;;;;;; 380 381;(define-pmacro (build-reg-name n) (.splice (.str "$" n) n)) 382 383; These are the 16 registers that the chip has. In later versions 384; where there will be more registers, this will need to be expanded. 385; Note that there are two entries for the registers with two names. 386(define-hardware 387 (name h-spr) 388 (comment "special-purpose registers") 389 (type register SI (16)) 390 (indices keyword "" (("R0" 0) ("R1" 1) ("R2" 2) ("R3" 3) ("R4" 4) ("R5" 5) 391 ("R6" 6) ("R7" 7) ("R8" 8) ("R9" 9) ("R10" 10) ("R11" 11) ("R12" 12) ("fp" 12) 392 ("R13" 13) ("sp" 13) ("R14" 14) ("ra" 14) ("R15" 15) ("ira" 15))) 393; (get (index) (and (raw-reg h-spr) #xffffffff)) 394; (set (index value) (set (raw-reg h-spr) (and value #xffffffff))) 395) 396 397; This is the program counter. 398(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) 399 400(define-keyword 401 (name msys-syms) 402 (print-name h-nil) 403 (prefix "") 404 (values (DUP 1) (XX 0)) 405) 406 407;;;;;;;;;;;;;; 408;; Operands ;; 409;;;;;;;;;;;;;; 410 411(define-operand (name frsr1) (comment "register") (attrs) 412 (type h-spr) (index f-sr1) ) 413(define-operand (name frsr2) (comment "register") (attrs) 414 (type h-spr) (index f-sr2) ) 415(define-operand (name frdr) (comment "register") (attrs) 416 (type h-spr) (index f-dr) ) 417(define-operand (name frdrrr) (comment "register") (attrs) 418 (type h-spr) (index f-drrr) ) 419(define-operand (name imm16) (comment "immediate value - sign extd") (attrs) 420 (type h-sint) (index f-imm16s) (handlers (parse "imm16") (print "dollarhex"))) 421(define-operand (name imm16z) (comment "immediate value - zero extd") (attrs) 422 (type h-uint) (index f-imm16u) (handlers (parse "imm16") (print "dollarhex"))) 423(define-operand (name imm16o) (comment "immediate value") (attrs PCREL-ADDR) 424 (type h-uint) (index f-imm16s) (handlers (parse "imm16") (print "pcrel"))) 425 426; Operands for MorphoSys Instructions 427 428(define-operand (name rc) (comment "rc") (attrs) 429 (type h-uint) (index f-rc) (handlers (parse "rc") (print "dollarhex"))) 430 431(define-operand (name rcnum) (comment "rcnum") (attrs) 432 (type h-uint) (index f-rcnum) (handlers (print "dollarhex"))) 433 434(define-operand (name contnum) (comment "context number") (attrs) 435 (type h-uint) (index f-contnum) (handlers (print "dollarhex"))) 436 437(define-operand (name rbbc) (comment "omega network configuration") (attrs) 438 (type h-uint) (index f-rbbc) (handlers (parse "rbbc") (print "dollarhex"))) 439 440(define-operand (name colnum) (comment "column number") (attrs) 441 (type h-uint) (index f-colnum) (handlers (print "dollarhex"))) 442 443(define-operand (name rownum) (comment "row number") (attrs) 444 (type h-uint) (index f-rownum) (handlers (print "dollarhex"))) 445 446(define-operand (name rownum1) (comment "row number") (attrs) 447 (type h-uint) (index f-rownum1) (handlers (print "dollarhex"))) 448 449(define-operand (name rownum2) (comment "row number") (attrs) 450 (type h-uint) (index f-rownum2) (handlers (print "dollarhex"))) 451 452(define-operand (name rc1) (comment "rc1") (attrs) 453 (type h-uint) (index f-rc1) (handlers (parse "rc") (print "dollarhex"))) 454 455(define-operand (name rc2) (comment "rc2") (attrs) 456 (type h-uint) (index f-rc2) (handlers (parse "rc") (print "dollarhex"))) 457 458(define-operand (name cbrb) (comment "data-bus orientation") (attrs) 459 (type h-uint) (index f-cbrb) (handlers (parse "cbrb") (print "dollarhex"))) 460 461(define-operand (name cell) (comment "cell") (attrs) 462 (type h-uint) (index f-cell) (handlers (print "dollarhex"))) 463 464(define-operand (name dup) (comment "dup") (attrs) 465 (type h-uint) (index f-dup) (handlers (parse "dup") (print "dollarhex"))) 466 467(define-operand (name ctxdisp) (comment "context displacement") (attrs) 468 (type h-uint) (index f-ctxdisp) (handlers (print "dollarhex"))) 469 470(define-operand (name fbdisp) (comment "frame buffer displacement") (attrs) 471 (type h-uint) (index f-fbdisp) (handlers (print "dollarhex"))) 472 473(define-operand (name type) (comment "type") (attrs) 474 (type h-uint) (index f-type) (handlers (parse "type") (print "dollarhex"))) 475 476(define-operand (name mask) (comment "mask") (attrs) 477 (type h-uint) (index f-mask) (handlers (print "dollarhex"))) 478 479(define-operand (name bankaddr) (comment "bank address") (attrs) 480 (type h-uint) (index f-bankaddr) (handlers (print "dollarhex"))) 481 482(define-operand (name incamt) (comment "increment amount") (attrs) 483 (type h-uint) (index f-incamt) (handlers (print "dollarhex"))) 484 485(define-operand (name xmode) (comment "xmode") (attrs) 486 (type h-uint) (index f-xmode) (handlers (parse "xmode") (print "dollarhex"))) 487 488(define-operand (name mask1) (comment "mask1") (attrs) 489 (type h-uint) (index f-mask1) (handlers (print "dollarhex"))) 490 491(define-operand (name ball) (comment "b_all") (attrs) 492 (type h-uint) (index f-ball) (handlers (parse "ball") (print "dollarhex"))) 493 494(define-operand (name brc) (comment "b_r_c") (attrs) 495 (type h-uint) (index f-brc) (handlers (print "dollarhex"))) 496 497(define-operand (name rda) (comment "rd") (attrs) 498 (type h-uint) (index f-rda) (handlers (print "dollarhex"))) 499 500(define-operand (name wr) (comment "wr") (attrs) 501 (type h-uint) (index f-wr) (handlers (print "dollarhex"))) 502 503(define-operand (name ball2) (comment "b_all2") (attrs) 504 (type h-uint) (index f-ball2) (handlers (parse "ball") (print "dollarhex"))) 505 506(define-operand (name brc2) (comment "b_r_c2") (attrs) 507 (type h-uint) (index f-brc2) (handlers (print "dollarhex"))) 508(define-operand (name perm) (comment "perm") (attrs) 509 (type h-uint) (index f-perm) (handlers (print "dollarhex"))) 510(define-operand (name a23) (comment "a23") (attrs) 511 (type h-uint) (index f-a23) (handlers (print "dollarhex"))) 512(define-operand (name cr) (comment "c-r") (attrs) 513 (type h-uint) (index f-cr) (handlers (print "dollarhex"))) 514(define-operand (name cbs) (comment "cbs") (attrs) 515 (type h-uint) (index f-cbs) (handlers (print "dollarhex"))) 516(define-operand (name incr) (comment "incr") (attrs) 517 (type h-uint) (index f-incr) (handlers (print "dollarhex"))) 518(define-operand (name length) (comment "length") (attrs) 519 (type h-uint) (index f-length) (handlers (print "dollarhex"))) 520(define-operand (name cbx) (comment "cbx") (attrs) 521 (type h-uint) (index f-cbx) (handlers (print "dollarhex"))) 522(define-operand (name ccb) (comment "ccb") (attrs) 523 (type h-uint) (index f-ccb) (handlers (print "dollarhex"))) 524(define-operand (name cdb) (comment "cdb") (attrs) 525 (type h-uint) (index f-cdb) (handlers (print "dollarhex"))) 526 527; For the INTLVR insn 528(define-operand (name mode) (comment "mode") (attrs) 529 (type h-uint) (index f-mode) (handlers (print "dollarhex"))) 530(define-operand (name id) (comment "i/d") (attrs) 531 (type h-uint) (index f-id) (handlers (print "dollarhex"))) 532(define-operand (name size) (comment "size") (attrs) 533 (type h-uint) (index f-size) (handlers (print "dollarhex"))) 534 535(define-operand (name fbincr) (comment "fb incr") (attrs) 536 (type h-uint) (index f-fbincr) (handlers (print "dollarhex"))) 537 538; For the ms2 insns 539(define-operand (name loopsize) (comment "immediate value") 540 (attrs (MACH ms2) PCREL-ADDR) 541 (type h-uint) (index f-loopo) (handlers (parse "loopsize") (print "pcrel"))) 542(define-operand (name imm16l) (comment "immediate value") 543 (attrs (MACH ms2)) 544 (type h-uint) (index f-imm16l) (handlers (print "dollarhex"))) 545(define-operand (name rc3) (comment "rc3") (attrs (MACH ms2)) 546 (type h-uint) (index f-rc3) (handlers (parse "rc") (print "dollarhex"))) 547(define-operand (name cb1sel) (comment "cb1sel") (attrs (MACH ms2)) 548 (type h-uint) (index f-cb1sel) (handlers (print "dollarhex"))) 549(define-operand (name cb2sel) (comment "cb2sel") (attrs (MACH ms2)) 550 (type h-uint) (index f-cb2sel) (handlers (print "dollarhex"))) 551(define-operand (name cb1incr) (comment "cb1incr") (attrs (MACH ms2)) 552 (type h-sint) (index f-cb1incr) (handlers (print "dollarhex"))) 553(define-operand (name cb2incr) (comment "cb2incr") (attrs (MACH ms2)) 554 (type h-sint) (index f-cb2incr) (handlers (print "dollarhex"))) 555 556; Probaby won't need most of these. 557(define-pmacro r0 (reg h-spr #x0)) 558(define-pmacro r1 (reg h-spr #x01)) 559(define-pmacro r2 (reg h-spr #x02)) 560(define-pmacro r3 (reg h-spr #x03)) 561(define-pmacro r4 (reg h-spr #x04)) 562(define-pmacro r5 (reg h-spr #x05)) 563(define-pmacro r6 (reg h-spr #x06)) 564(define-pmacro r7 (reg h-spr #x07)) 565(define-pmacro r8 (reg h-spr #x08)) 566(define-pmacro r9 (reg h-spr #x09)) 567(define-pmacro r10 (reg h-spr #xA)) 568(define-pmacro r11 (reg h-spr #xB)) 569(define-pmacro r12 (reg h-spr #xC)) 570(define-pmacro fp (reg h-spr #xC)) 571(define-pmacro r13 (reg h-spr #xD)) 572(define-pmacro sp (reg h-spr #xD)) 573(define-pmacro r14 (reg h-spr #xE)) 574(define-pmacro ra (reg h-spr #xE)) 575(define-pmacro r15 (reg h-spr #xF)) 576(define-pmacro ira (reg h-spr #xF)) 577 578; delayed set 579(define-pmacro (dset dest src) (set (delay 1 dest) src)) 580 581 582;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 583;; Instructions As Defined In the MorphoRisc ISA Document ;; 584;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 585 586; Arithmetic Instructions 587 588(dni add "ADD DstReg, SrcReg1, SrcReg2" 589 (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) 590 "add $frdrrr,$frsr1,$frsr2" 591 (+ MSYS_NO OPC_ADD IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) 592 (set frdrrr (add SI frsr1 frsr2)) 593 () 594) 595 596(dni addu "ADDU DstReg, SrcReg1, SrcReg2" 597 (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) 598 "addu $frdrrr,$frsr1,$frsr2" 599 (+ MSYS_NO OPC_ADDU IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) 600 (set frdrrr (add USI frsr1 frsr2)) 601 () 602) 603 604(dni addi "ADDI DstReg, SrcReg1 UnsImm" 605 (AL-INSN USES-FRDR USES-FRSR1) 606 "addi $frdr,$frsr1,#$imm16" 607 (+ MSYS_NO OPC_ADD IMM_YES frsr1 frdr imm16) 608 (sequence((HI tmp)) 609 (set HI tmp (and imm16 #xffff)) 610 (set frdr (add SI frsr1 (ext SI tmp))) 611 ) 612 () 613) 614 615(dni addui "ADDUI DstReg, SrcReg1, UnsImm" 616 (AL-INSN USES-FRDR USES-FRSR1) 617 "addui $frdr,$frsr1,#$imm16z" 618 (+ MSYS_NO OPC_ADDU IMM_YES frsr1 frdr imm16z) 619 (set frdr (add USI frsr1 (ext USI imm16z))) 620 () 621) 622 623(dni sub "SUB DstReg, SrcReg1, SrcReg2" 624 (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) 625 "sub $frdrrr,$frsr1,$frsr2" 626 (+ MSYS_NO OPC_SUB IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) 627 (set frdrrr (sub SI frsr1 frsr2)) 628 () 629) 630 631(dni subu "SUBU DstReg, SrcReg1, SrcReg2" 632 (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) 633 "subu $frdrrr,$frsr1,$frsr2" 634 (+ MSYS_NO OPC_SUBU IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) 635 (set frdrrr (sub USI frsr1 frsr2)) 636 () 637) 638 639(dni subi "SUBI DstReg, SrcReg1, UnsImm" 640 (AL-INSN USES-FRDR USES-FRSR1) 641 "subi $frdr,$frsr1,#$imm16" 642 (+ MSYS_NO OPC_SUB IMM_YES frsr1 frdr imm16) 643 (sequence((HI tmp)) 644 (set HI tmp (and imm16 #xffff)) 645 (set frdr (sub SI frsr1 (ext SI tmp))) 646 ) 647 ;(set frdr (sub SI frsr1 (ext SI imm16))) 648 () 649) 650 651(dni subui "SUBUI DstReg, SrcReg1, UnsImm" 652 (AL-INSN USES-FRDR USES-FRSR1) 653 "subui $frdr,$frsr1,#$imm16z" 654 (+ MSYS_NO OPC_SUBU IMM_YES frsr1 frdr imm16z) 655 (set frdr (sub USI frsr1 (ext USI imm16z))) 656 () 657) 658 659(dni mul "MUL DstReg, SrcReg1, SrcReg2" 660 ((MACH ms1-003,ms2) AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) 661 "mul $frdrrr,$frsr1,$frsr2" 662 (+ MSYS_NO OPC_MUL IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) 663 (sequence((HI op1) (HI op2)) 664 (set op1 (and frsr1 #xffff)) 665 (if (or (lt op1 (const -32768)) (gt op1 (const 32767))) 666 (error "operand out of range") 667 ) 668 (set op2 (and frsr2 #xffff)) 669 (if (or (lt op2 (const -32768)) (gt op2 (const 32767))) 670 (error "operand out of range") 671 ) 672 (set frdrrr (mul SI (ext SI op1) (ext SI op2))) 673 ) 674 () 675) 676 677(dni muli "MULI DstReg, SrcReg1, UnsImm" 678 ((MACH ms1-003,ms2) AL-INSN USES-FRDR USES-FRSR1) 679 "muli $frdr,$frsr1,#$imm16" 680 (+ MSYS_NO OPC_MUL IMM_YES frsr1 frdr imm16) 681 (sequence((HI op1) (HI op2)) 682 (set op1 (and frsr1 #xffff)) 683 (if (or (lt op1 (const -32768)) (gt op1 (const 32767))) 684 (error "operand out of range") 685 ) 686 (set op2 (and imm16 #xffff)) 687 (if (eq op1 (const 0)) 688 (error "op1 is 0") 689 ) 690 (if (eq op2 (const 0)) 691 (error "op2 is 0") 692 ) 693 (set frdr (mul SI (ext SI op1) (ext SI op2))) 694 ) 695 () 696) 697 698; Logical Instructions 699 700(dni and "AND DstReg, SrcReg1, SrcReg2" 701 (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) 702 "and $frdrrr,$frsr1,$frsr2" 703 (+ MSYS_NO OPC_AND IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) 704 (set frdrrr (and frsr1 frsr2)) 705 () 706) 707 708(dni andi "ANDI DstReg, SrcReg1, UnsImm" 709 (AL-INSN USES-FRDR USES-FRSR1) 710 "andi $frdr,$frsr1,#$imm16z" 711 (+ MSYS_NO OPC_AND IMM_YES frsr1 frdr imm16z) 712 (set frdr (and frsr1 (ext USI imm16z))) 713 () 714) 715 716(dni or "OR DstReg, SrcReg1, SrcReg2" 717 (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) 718 "or $frdrrr,$frsr1,$frsr2" 719 (+ MSYS_NO OPC_OR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) 720 (set frdrrr (or frsr1 frsr2)) 721 () 722) 723 724(dni nop "nop" 725 () 726 "nop" 727 (+ MSYS_NO OPC_OR IMM_NO (f-uu24 0)) 728 (nop) 729 () 730) 731 732(dni ori "ORI DstReg, SrcReg1, UnsImm" 733 (AL-INSN USES-FRDR USES-FRSR1) 734 "ori $frdr,$frsr1,#$imm16z" 735 (+ MSYS_NO OPC_OR IMM_YES frsr1 frdr imm16z) 736 (set frdr (or frsr1 (ext USI imm16z))) 737 () 738) 739 740(dni xor "XOR DstReg, SrcReg1, SrcReg2" 741 (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) 742 "xor $frdrrr,$frsr1,$frsr2" 743 (+ MSYS_NO OPC_XOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) 744 (set frdrrr (xor frsr1 frsr2)) 745 () 746) 747 748(dni xori "XORI DstReg, SrcReg1, UnsImm" 749 (AL-INSN USES-FRDR USES-FRSR1) 750 "xori $frdr,$frsr1,#$imm16z" 751 (+ MSYS_NO OPC_XOR IMM_YES frsr1 frdr imm16z) 752 (set frdr (xor frsr1 (ext USI imm16z))) 753 () 754) 755 756(dni nand "NAND DstReg, SrcReg1, SrcReg2" 757 (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) 758 "nand $frdrrr,$frsr1,$frsr2" 759 (+ MSYS_NO OPC_NAND IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) 760 (set frdrrr (inv (and frsr1 frsr2))) 761 () 762) 763 764(dni nandi "NANDI DstReg, SrcReg1, UnsImm" 765 (AL-INSN USES-FRDR USES-FRSR1) 766 "nandi $frdr,$frsr1,#$imm16z" 767 (+ MSYS_NO OPC_NAND IMM_YES frsr1 frdr imm16z) 768 (set frdr (inv (and frsr1 (ext USI imm16z)))) 769 () 770) 771 772(dni nor "NOR DstReg, SrcReg1, SrcReg2" 773 (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) 774 "nor $frdrrr,$frsr1,$frsr2" 775 (+ MSYS_NO OPC_NOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) 776 (set frdrrr (inv (or frsr1 frsr2))) 777 () 778) 779 780(dni nori "NORI DstReg, SrcReg1, UnsImm" 781 (AL-INSN USES-FRDR USES-FRSR1) 782 "nori $frdr,$frsr1,#$imm16z" 783 (+ MSYS_NO OPC_NOR IMM_YES frsr1 frdr imm16z) 784 (set frdr (inv (or frsr1 (ext USI imm16z)))) 785 () 786) 787 788(dni xnor "XNOR DstReg, SrcReg1, SrcReg2" 789 (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) 790 "xnor $frdrrr,$frsr1,$frsr2" 791 (+ MSYS_NO OPC_XNOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) 792 (set frdrrr (inv (xor frsr1 frsr2))) 793 () 794) 795 796(dni xnori "XNORI DstReg, SrcReg1, UnsImm" 797 (AL-INSN USES-FRDR USES-FRSR1) 798 "xnori $frdr,$frsr1,#$imm16z" 799 (+ MSYS_NO OPC_XNOR IMM_YES frsr1 frdr imm16z) 800 (set frdr (inv (xor frsr1 (ext USI imm16z)))) 801 () 802) 803 804(dni ldui "LDUI DstReg, UnsImm" 805 (AL-INSN USES-FRDR) 806 "ldui $frdr,#$imm16z" 807 (+ MSYS_NO OPC_LDUI IMM_YES (f-uu4b 0) frdr imm16z) 808 (set frdr (and (sll imm16z 16) #xffff0000)) 809 () 810) 811 812; Shift Instructions 813 814(dni lsl "LSL DstReg, SrcReg1, SrcReg2" 815 (USES-FRDRRR USES-FRSR1 USES-FRSR2) 816 "lsl $frdrrr,$frsr1,$frsr2" 817 (+ MSYS_NO OPC_LSL IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) 818 (set frdrrr (sll frsr1 frsr2)) 819 () 820) 821 822(dni lsli "LSLI DstReg, SrcReg1, UnsImm" 823 (USES-FRDR USES-FRSR1) 824 "lsli $frdr,$frsr1,#$imm16" 825 (+ MSYS_NO OPC_LSL IMM_YES frsr1 frdr imm16) 826 (set frdr (sll frsr1 imm16)) 827 () 828) 829 830(dni lsr "LSR DstReg, SrcReg1, SrcReg2" 831 (USES-FRDRRR USES-FRSR1 USES-FRSR2) 832 "lsr $frdrrr,$frsr1,$frsr2" 833 (+ MSYS_NO OPC_LSR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) 834 (set frdrrr (srl frsr1 frsr2)) 835 () 836) 837 838(dni lsri "LSRI DstReg, SrcReg1, UnsImm" 839 (USES-FRDR USES-FRSR1) 840 "lsri $frdr,$frsr1,#$imm16" 841 (+ MSYS_NO OPC_LSR IMM_YES frsr1 frdr imm16) 842 (set frdr (srl frsr1 imm16)) 843 () 844) 845 846(dni asr "ASR DstReg, SrcReg1, SrcReg2" 847 (USES-FRDRRR USES-FRSR1 USES-FRSR2) 848 "asr $frdrrr,$frsr1,$frsr2" 849 (+ MSYS_NO OPC_ASR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) 850 (set frdrrr (sra frsr1 frsr2)) 851 () 852) 853 854(dni asri "ASRI DstReg, SrcReg1, UnsImm" 855 (USES-FRDR USES-FRSR1) 856 "asri $frdr,$frsr1,#$imm16" 857 (+ MSYS_NO OPC_ASR IMM_YES frsr1 frdr imm16) 858 (set frdr (sra frsr1 imm16)) 859 () 860) 861 862; Control Transfer Instructions 863 864(dni brlt "BRLT SrcReg1, SrcReg2, label" 865 (BR-INSN DELAY-SLOT USES-FRDRRR USES-FRSR1 USES-FRSR2) 866 "brlt $frsr1,$frsr2,$imm16o" 867 (+ MSYS_NO OPC_BRLT IMM_YES frsr1 frsr2 imm16o) 868 (sequence() 869 (if (lt USI frsr1 frsr2) 870 (dset pc (add pc (ext SI imm16o)))) 871 ) 872 () 873) 874 875(dni brle "BRLE SrcReg1, SrcReg2, label" 876 (BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2) 877 "brle $frsr1,$frsr2,$imm16o" 878 (+ MSYS_NO OPC_BRLE IMM_YES frsr1 frsr2 imm16o) 879 (sequence() 880 (if (le USI frsr1 frsr2) 881 (dset pc (add pc (ext SI imm16o)))) 882 ) 883 () 884) 885 886(dni breq "BREQ SrcReg1, SrcReg2, label" 887 (BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2) 888 "breq $frsr1,$frsr2,$imm16o" 889 (+ MSYS_NO OPC_BREQ IMM_YES frsr1 frsr2 imm16o) 890 (sequence() 891 (if (eq USI frsr1 frsr2) 892 (dset pc (add pc (ext SI imm16o)))) 893 ) 894 () 895) 896 897(dni brne "BRNE SrcReg1, SrcReg2, label" 898 (BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2) 899 "brne $frsr1,$frsr2,$imm16o" 900 (+ MSYS_NO OPC_BRNEQ IMM_YES frsr1 frsr2 imm16o) 901 (sequence() 902 (if (not (eq USI frsr1 frsr2)) 903 (dset pc (add pc (ext SI imm16o)))) 904 ) 905 () 906) 907 908(dni jmp "JMP, label" 909 (DELAY-SLOT BR-INSN) 910 "jmp $imm16o" 911 (+ MSYS_NO OPC_JMP IMM_YES (f-uu4b 0) (f-uu4a 0) imm16o) 912 (dset pc (add pc (ext SI imm16o))) 913 () 914) 915 916(dni jal "JAL DstReg, SrcReg1" 917 (BR-INSN DELAY-SLOT BR-INSN USES-FRDR USES-FRSR1 JAL-HAZARD) 918 "jal $frdrrr,$frsr1" 919 (+ MSYS_NO OPC_JAL IMM_NO frsr1 (f-uu4a 0) frdrrr (f-uu12 0)) 920 (sequence() 921 (if (eq frsr1 #x0) 922 (c-call VOID "do_syscall" pc) 923 (sequence() ; else part. Do non-syscall stuff here. 924 (dset frdrrr (add pc #x8)) 925 (dset pc frsr1) 926 ) 927 ) 928 ) 929 () 930) 931 932(dni dbnz "DBNZ SrcReg1, label" 933 ((MACH ms1-003,ms2) BR-INSN DELAY-SLOT USES-FRSR1) 934 "dbnz $frsr1,$imm16o" 935 (+ MSYS_NO OPC_DBNZ IMM_YES frsr1 (f-uu4a 0) imm16o) 936 (sequence() 937 (if (not (eq USI frsr1 0)) 938 (dset pc (add pc (ext SI imm16o)))) 939 ) 940 () 941) 942 943; Interrupt Control Instructions 944 945(dni ei "EI - Enable Interrupt Processing" 946 () 947 "ei" 948 (+ MSYS_NO OPC_EI IMM_NO (f-uu4b 0) (f-uu4a 0) (f-uu16 0)) 949 (c-call VOID "enable_interrupts") 950 () 951) 952 953(dni di "DI - Disable Interrupt Processing" 954 () 955 "di" 956 (+ MSYS_NO OPC_DI IMM_NO (f-uu4b 0) (f-uu4a 0) (f-uu16 0)) 957 (c-call VOID "disable_interrupts") 958 () 959) 960 961(dni si "SI - Send software Interrupt" 962 (DELAY-SLOT BR-INSN USES-FRDR) 963 "si $frdrrr" 964 (+ MSYS_NO OPC_SI IMM_NO (f-uu4b 0) (f-uu4a 0) frdrrr (f-uu12 0)) 965 ;(sequence() 966 ; (dset frdr (add pc #x4)) 967 ; (c-call VOID "do_syscall1" pc) 968 ; ; (dset pc frsr1) Do this later when we have the address. 969 ;) 970 (sequence() 971 (set frdrrr (add pc #x4)) 972 (c-call VOID "do_syscall" pc) 973 ; (set pc frsr1) Do this later when we have the address. 974 ) 975 () 976) 977 978(dni reti "RETI SrcReg1" 979 (DELAY-SLOT BR-INSN USES-FRSR1 JAL-HAZARD) 980 "reti $frsr1" 981 (+ MSYS_NO OPC_RETI IMM_NO frsr1 (f-uu4a 0) (f-uu16 0)) 982 (sequence() 983 (c-call VOID "enable_interrupts") 984 (dset pc frsr1) 985 ) 986 () 987) 988 989; Memory Access Instructions 990 991(dni ldw "LDW DstReg, SrcReg1, Imm" 992 (LOAD-DELAY MEMORY-ACCESS USES-FRDR USES-FRSR1) 993 "ldw $frdr,$frsr1,#$imm16" 994 (+ MSYS_NO OPC_LDW IMM_YES frsr1 frdr imm16) 995 (sequence((USI ea) (HI tmp)) 996 (set HI tmp (and imm16 #xffff)) 997 (set ea (and (add SI frsr1 (ext SI tmp)) #xfffffffc)) 998 (set frdr (mem SI ea)) 999 ) 1000 () 1001) 1002 1003(dni stw "STW SrcReg2, SrcReg1, Imm" 1004 (MEMORY-ACCESS USES-FRSR1 USES-FRSR2) 1005 "stw $frsr2,$frsr1,#$imm16" 1006 (+ MSYS_NO OPC_STW IMM_YES frsr1 frsr2 imm16) 1007 (sequence((USI ea) (HI tmp)) 1008 (set HI tmp (and imm16 #xffff)) 1009 (set ea (and (add SI frsr1 (ext SI tmp)) #xfffffffc)) 1010 (set (mem SI ea) frsr2) 1011 ) 1012 () 1013) 1014 1015; Break Instruction 1016 1017(dni break "BREAK" 1018 () 1019 "break" 1020 (+ MSYS_NO OPC_BREAK (f-imm 0) (f-uu24 0)) 1021 (c-call VOID "do_break" pc) 1022 () 1023) 1024 1025; Cache Flush Instruction 1026 1027(dni iflush "IFLUSH" 1028 ((MACH ms1-003,ms2)) 1029 "iflush" 1030 (+ MSYS_NO OPC_IFLUSH (f-imm 0) (f-uu24 0)) 1031 (nop) 1032 () 1033) 1034 1035; MorphoSys Instructions 1036 1037(dni ldctxt "LDCTXT SRC1, SRC2, r/c, r/c#, context#" 1038 ((MACH ms1)) 1039 "ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum" 1040 (+ MSYS_YES MSOPC_LDCTXT (f-uu-2-25 0) frsr1 frsr2 rc rcnum (f-uu-3-11 0) 1041 contnum ) 1042 (nop) 1043 () 1044) 1045 1046(dni ldfb "LDFB SRC1, byte#" 1047 ((MACH ms1)) 1048 "ldfb $frsr1,$frsr2,#$imm16z" 1049 (+ MSYS_YES MSOPC_LDFB (f-uu-2-25 0) frsr1 frsr2 imm16z) 1050 (nop) 1051 () 1052) 1053 1054(dni stfb "STFB SRC1, SRC2, byte " 1055 ((MACH ms1)) 1056 "stfb $frsr1,$frsr2,#$imm16z" 1057 (+ MSYS_YES MSOPC_STFB (f-uu-2-25 0) frsr1 frsr2 imm16z) 1058 (nop) 1059 () 1060) 1061 1062(dni fbcb "FBCB SRC1, RT/BR1/BR2/CS, B_all, B_r_c, r/c, CB/RB, cell, dup, ctx_disp" 1063 ((MACH ms1,ms1-003)) 1064 "fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp" 1065 (+ MSYS_YES MSOPC_FBCB rbbc frsr1 ball brc (f-uu-4-15 0) rc cbrb cell dup ctxdisp) 1066 (nop) 1067 () 1068) 1069 1070(dni mfbcb "MFBCB SRC1, RT/BR1/BR2/CS, SRC2, r/c, CB/RB, cell, dup, ctx_disp" 1071 () 1072 "mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp" 1073 (+ MSYS_YES MSOPC_MFBCB rbbc frsr1 frsr2 (f-uu-4-15 0) rc1 cbrb cell dup ctxdisp) 1074 (nop) 1075 () 1076) 1077 1078(dni fbcci "FBCCI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp" 1079 () 1080 "fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp" 1081 (+ MSYS_YES MSOPC_FBCCI rbbc frsr1 ball brc fbdisp cell dup ctxdisp) 1082 (nop) 1083 () 1084) 1085 1086(dni fbrci "FBRCI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp" 1087 () 1088 "fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp" 1089 (+ MSYS_YES MSOPC_FBRCI rbbc frsr1 ball brc fbdisp cell dup ctxdisp) 1090 (nop) 1091 () 1092) 1093 1094(dni fbcri "FBCRI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp" 1095 () 1096 "fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp" 1097 (+ MSYS_YES MSOPC_FBCRI rbbc frsr1 ball brc fbdisp cell dup ctxdisp) 1098 (nop) 1099 () 1100) 1101 1102(dni fbrri "FBRRI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp" 1103 () 1104 "fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp" 1105 (+ MSYS_YES MSOPC_FBRRI rbbc frsr1 ball brc fbdisp cell dup ctxdisp) 1106 (nop) 1107 () 1108) 1109 1110(dni mfbcci "MFBCCI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp" 1111 () 1112 "mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp" 1113 (+ MSYS_YES MSOPC_MFBCCI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp) 1114 (nop) 1115 () 1116) 1117 1118(dni mfbrci "MFBRCI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp" 1119 () 1120 "mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp" 1121 (+ MSYS_YES MSOPC_MFBRCI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp) 1122 (nop) 1123 () 1124) 1125 1126(dni mfbcri "MFBCRI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp" 1127 () 1128 "mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp" 1129 (+ MSYS_YES MSOPC_MFBCRI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp) 1130 (nop) 1131 () 1132) 1133 1134(dni mfbrri "MFBRRI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp" 1135 () 1136 "mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp" 1137 (+ MSYS_YES MSOPC_MFBRRI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp) 1138 (nop) 1139 () 1140) 1141 1142(dni fbcbdr "FBCBDR SRC1, RT/BR1/BR2/CS, SRC2, B_all, B_r_c, r/c, CB/RB, cell, dup, ctx_disp" 1143 () 1144 "fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp" 1145 (+ MSYS_YES MSOPC_FBCBDR rbbc frsr1 frsr2 ball2 brc2 rc1 cbrb cell dup ctxdisp) 1146 (nop) 1147 () 1148) 1149 1150(dni rcfbcb "RCFBCB RT/BR1/BR2/CS, type, B_all, B_r_c, row#, r/c, CB/RB, cell, dup, ctx_disp" 1151 () 1152 "rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp" 1153 (+ MSYS_YES MSOPC_RCFBCB rbbc (f-uu-2-23 0) type ball brc (f-uu-1-15 0) rownum rc1 cbrb cell dup ctxdisp) 1154 (nop) 1155 () 1156) 1157 1158(dni mrcfbcb "MRCFBCB SRC2, RT/BR1/BR2/CS, type, row#, r/c, CB/RB, cell, dup, ctx_disp" 1159 () 1160 "mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp" 1161 (+ MSYS_YES MSOPC_MRCFBCB rbbc (f-uu-2-23 0) type frsr2 (f-uu-1-15 0) rownum rc1 cbrb cell dup ctxdisp) 1162 (nop) 1163 () 1164) 1165 1166(dni cbcast "CBCAST mask, r/c, ctx_disp " 1167 () 1168 "cbcast #$mask,#$rc2,#$ctxdisp" 1169 (+ MSYS_YES MSOPC_CBCAST mask (f-uu-3-9 0) rc2 ctxdisp) 1170 (nop) 1171 () 1172) 1173 1174(dni dupcbcast "DUPCBCAST mask, cell, r/c, ctx_disp " 1175 () 1176 "dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp" 1177 (+ MSYS_YES MSOPC_DUPCBCAST mask cell rc2 ctxdisp) 1178 (nop) 1179 () 1180) 1181 1182(dni wfbi "WFBI Bank_address, row#, cell, dup, ctx_disp " 1183 () 1184 "wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp" 1185 (+ MSYS_YES MSOPC_WFBI bankaddr rownum1 cell dup ctxdisp) 1186 (nop) 1187 () 1188) 1189 1190;(dni wfb "WFB SRC1, SRC2, FB_disp, row#, ctx_disp" 1191; () 1192; "wfb $frsr1,$frsr2,#$fbdisp,#$rownum,#$ctxdisp" 1193; (+ MSYS_YES MSOPC_WFB (f-uu-2-25 0) frsr1 frsr2 fbdisp rownum (f-uu-1-6 0) ctxdisp) 1194; (nop) 1195; () 1196;) 1197 1198(dni wfb "WFB, DRC1,SRC2,FB_disp,row#,ctx_disp" 1199 () 1200 "wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp" 1201 (+ MSYS_YES MSOPC_WFB (f-uu-2-25 0) frsr1 frsr2 fbdisp rownum2 (f-uu-1-6 0) ctxdisp) 1202 (nop) 1203 () 1204) 1205 1206 1207(dni rcrisc "RCRISC DEST, RT/BR1/BR2/CS, SRC1, column#, r/c, CB/RB, cell, dup, ctx_disp" 1208 () 1209 "rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp" 1210 (+ MSYS_YES MSOPC_RCRISC rbbc frsr1 (f-uu-1-19 0) colnum frdrrr rc1 cbrb cell dup ctxdisp) 1211 (nop) 1212 () 1213) 1214 1215(dni fbcbinc "FBCBINC SRC1, RT/BR1/BR2/CS, Incr_amount, r/c, CB/RB, cell, dup, ctx_disp " 1216 () 1217 "fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp" 1218 (+ MSYS_YES MSOPC_FBCBINC rbbc frsr1 incamt rc1 cbrb cell dup ctxdisp) 1219 (nop) 1220 () 1221) 1222 1223(dni rcxmode "RCXMODE SRC2, rd, wr, xmode, mask, FB_disp, row#, r/c, ctx_disp" 1224 () 1225 "rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp" 1226 (+ MSYS_YES MSOPC_RCXMODE rda wr xmode mask1 frsr2 fbdisp rownum2 rc2 ctxdisp) 1227 (nop) 1228 () 1229) 1230 1231(dni interleaver "INTLVR ireg, mode, ireg, i/d, size" 1232 () 1233 "intlvr $frsr1,#$mode,$frsr2,#$id,#$size" 1234 (+ MSYS_YES MSOPC_INTLVR mode frsr1 frsr2 (f-uu-1-15 0) id size) 1235 (nop) 1236 () 1237) 1238 1239;; Issue 66262: The documenatation gives the wrong order for 1240;; the arguments to the WFBINC instruction. 1241(dni wfbinc "WFBINC type, ccb/rcb, incr, all, c/r, length, rca_row, word, dup, ctxt_disp" 1242 ((MACH ms1-003,ms2)) 1243 "wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp" 1244 (+ MSYS_YES MSOPC_WFBINC rda wr fbincr ball colnum length rownum1 rownum2 dup ctxdisp) 1245 (nop) 1246 () 1247) 1248 1249(dni mwfbinc "MWFBINC mreg, type, ccb/rcb, incr, length, rca_row, word, dup, ctxt_disp" 1250 ((MACH ms1-003,ms2)) 1251 "mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp" 1252 (+ MSYS_YES MSOPC_MWFBINC rda wr fbincr frsr2 length rownum1 rownum2 dup ctxdisp) 1253 (nop) 1254 () 1255) 1256 1257(dni wfbincr "WFBINCR ireg, type, ccb/rcb, all, c/r, length, rca_row, word, dup, ctxt_disp" 1258 ((MACH ms1-003,ms2)) 1259 "wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp" 1260 (+ MSYS_YES MSOPC_WFBINCR rda wr frsr1 ball colnum length rownum1 rownum2 dup ctxdisp) 1261 (nop) 1262 () 1263) 1264 1265(dni mwfbincr "MWFBINCR ireg, mreg, type, ccb/rcb, length, rca_row, word, dup, ctxt_disp" 1266 ((MACH ms1-003,ms2)) 1267 "mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp" 1268 (+ MSYS_YES MSOPC_MWFBINCR rda wr frsr1 frsr2 length rownum1 rownum2 dup ctxdisp) 1269 (nop) 1270 () 1271) 1272 1273(dni fbcbincs "FBCBINCS perm, all, c/r, cbs, incr, ccb/rcb, cdb/rdb, word, dup, ctxt_disp" 1274 ((MACH ms1-003,ms2)) 1275 "fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp" 1276 (+ MSYS_YES MSOPC_FBCBINCS perm a23 cr cbs incr ccb cdb rownum2 dup ctxdisp) 1277 (nop) 1278 () 1279) 1280 1281(dni mfbcbincs "MFBCBINCS ireg, perm, cbs, incr, ccb/rcb, cdb/rdb, word, dup, ctxt_disp" 1282 ((MACH ms1-003,ms2)) 1283 "mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp" 1284 (+ MSYS_YES MSOPC_MFBCBINCS perm frsr1 cbs incr ccb cdb rownum2 dup ctxdisp) 1285 (nop) 1286 () 1287) 1288 1289(dni fbcbincrs "FBCBINCRS ireg, perm, all, c/r, cbs, ccb/rcb, cdb/rdb, word, dup, ctxt_disp" 1290 ((MACH ms1-003,ms2)) 1291 "fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp" 1292 (+ MSYS_YES MSOPC_FBCBINCRS perm frsr1 ball colnum (f-uu-1-15 0) cbx ccb cdb rownum2 dup ctxdisp) 1293 (nop) 1294 () 1295) 1296 1297(dni mfbcbincrs "MFBCBINCRS ireg, mreg, perm, cbs, ccb/rcb, cdb/rdb, word, dup, ctxt_disp" 1298 ((MACH ms1-003,ms2)) 1299 "mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp" 1300 (+ MSYS_YES MSOPC_MFBCBINCRS perm frsr1 frsr2 (f-uu-1-15 0) cbx ccb cdb rownum2 dup ctxdisp) 1301 (nop) 1302 () 1303) 1304 1305; MS2 instructions 1306(dni loop "LOOP SrcReg1, label" 1307 ((MACH ms2) DELAY-SLOT USES-FRSR1) 1308 "loop $frsr1,$loopsize" 1309 (+ MSYS_NO OPC_LOOP IMM_NO frsr1 (f-uu4a 0) (f-uu8 0) loopsize) 1310 (nop) ;; to be filled in 1311 () 1312) 1313 1314(dni loopi "LOOPI niter, label" 1315 ((MACH ms2) DELAY-SLOT) 1316 "loopi #$imm16l,$loopsize" 1317 (+ MSYS_NO OPC_LOOP IMM_YES imm16l loopsize) 1318 (nop) ;; to be filled in 1319 () 1320) 1321 1322(dni dfbc "dfbc cb1sel,cb2sel,cb1inc,cb2inc,dr/c,cr/c,ctxdisp" 1323 ((MACH ms2)) 1324 "dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp" 1325 (+ MSYS_YES MSOPC_LDCTXT cb1sel cb2sel cb1incr cb2incr rc3 rc2 ctxdisp) 1326 (nop) 1327 () 1328) 1329 1330(dni dwfb "dwfb cb1sel,cb2sel,cb1inc,cb2inc,cr/c,ctxdisp" 1331 ((MACH ms2)) 1332 "dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp" 1333 (+ MSYS_YES MSOPC_LDFB cb1sel cb2sel cb1incr cb2incr (f-uu1 0) rc2 ctxdisp) 1334 (nop) 1335 () 1336) 1337 1338(dni fbwfb "fbwfb cb1sel,cb2sel,cb1inc,cb2inc,r0/1,cr/c,ctxdisp" 1339 ((MACH ms2)) 1340 "fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp" 1341 (+ MSYS_YES MSOPC_STFB cb1sel cb2sel cb1incr cb2incr rc3 rc2 ctxdisp) 1342 (nop) 1343 () 1344) 1345 1346(dni dfbr "dfbr cb1sel,cb2sel,reg,W/O1,W/O2,mode,cr/c,ctxdisp" 1347 ((MACH ms2) USES-FRSR2) 1348 "dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp" 1349 (+ MSYS_YES MSOPC_FBCB cb1sel cb2sel frsr2 length rownum1 rownum2 rc2 ctxdisp) 1350 (nop) 1351 () 1352) 1353