1	.text
2
3stuff:
4	.ent stuff
5	.set push
6	.set noreorder
7	.set noat
8
9	add $0, $0, $31
10	add $1, $10, $3
11	add $31, $31, $0
12
13	addi $31, $0, 0
14	addi $1, $10, 3
15	addi $0, $31, -1
16
17	addiu $31, $0, 0
18	addiu $1, $10, 3
19	addiu $31, $0, 0xFFFF
20
21	and $0, $0, $31
22	and $1, $10, $3
23	and $31, $31, $0
24
25	andi $31, $0, 0
26	andi $1, $10, 3
27	andi $0, $31, 0xFFFF
28
29	nop
30
31	# Test R5900 specific instructions:
32	adda.s $f0, $f31
33	adda.s $f31, $f0
34
35	# The c.lt.s instruction of R5900 has the same opcode as c.olt.s of MIPS I.
36	c.lt.s $f0, $f31
37	c.lt.s $f31, $f0
38
39	# The c.le.s instruction of R5900 has the same opcode as c.ole.s of MIPS I.
40	c.le.s $f0, $f31
41	c.le.s $f31, $f0
42
43	c.eq.s $f0, $f31
44	c.eq.s $f31, $f0
45
46	c.f.s $f0, $f31
47	c.f.s $f31, $f0
48
49	# The cvt.w.s instruction of the R5900 does the same as trunc.w.s in MIPS I.
50	# The cvt.w.s instruction of MIPS I doesn't exist in the R5900 CPU.
51	# For compatibilty the instruction trunc.w.s uses the opcode of cvt.w.s.
52	# cvt.w.s should not be used on R5900.
53	trunc.w.s $f0, $f31
54	trunc.w.s $f31, $f0
55
56	# Test ei/di, but the R5900 has a bug. ei/di should not be used.
57	di
58	ei
59
60	# Like div but result is written to lo1 and hi1 registers (pipeline 1).
61	div1 $0, $1, $31
62	div1 $0, $31, $1
63	divu1 $0, $1, $31
64	divu1 $0, $31, $1
65
66	# 128 bit store instruction.
67	sq $0, 0($0)
68	sq $1, 0x7fff($1)
69	sq $8, -0x8000($8)
70	sq $31, -1($31)
71	.set at
72	sq $0, 0x8000($2)
73	sq $8, -0x8001($31)
74	sq $31, 0xF1234567($4)
75	.set noat
76
77	# 128 bit load instruction.
78	lq $0, 0($0)
79	lq $1, 0x7fff($1)
80	lq $8, -0x8000($8)
81	lq $31, -1($31)
82	lq $3, 0x8000($2)
83	lq $8, -0x8001($31)
84	lq $31, 0xF1234567($4)
85
86	# Prefetch cache
87	pref 0, 0($0)
88	pref 1, 0x7fff($1)
89	pref 8, -0x8000($8)
90	pref 31, -1($31)
91
92	# Floating point multiply-ADD
93	madd.s $f0, $f31, $f0
94	madd.s $f31, $f0, $f31
95
96	# Like maddu, but pipeline 1
97	maddu1 $0, $31
98	maddu1 $31, $0
99	maddu1 $0, $0, $31
100	maddu1 $31, $31, $0
101
102	# Like madd, but pipeline 1
103	madd1 $0, $31
104	madd1 $31, $0
105	madd1 $0, $0, $31
106	madd1 $31, $31, $0
107
108	# Floating point multiply-ADD
109	madda.s $f0, $f31
110	madda.s $f31, $f0
111
112	# Floating point maximum
113	max.s $f0, $f31, $f0
114	max.s $f31, $f0, $f31
115
116	# Floating point minimum
117	min.s $f0, $f31, $f0
118	min.s $f31, $f0, $f31
119
120	# Preformance counter registers
121	mfpc $31, 0
122	mfpc $0, 1
123	mfps $0, 0
124	mfps $31, 0
125	mtpc $31, 0
126	mtpc $0, 1
127	mtps $0, 0
128	mtps $31, 0
129
130	# Brekpoint register
131	mfbpc $0
132	mfbpc $31
133	mtbpc $0
134	mtbpc $31
135	mfdab $0
136	mfdab $31
137	mtdab $0
138	mtdab $31
139	mfdabm $0
140	mfdabm $31
141	mtdabm $0
142	mtdabm $31
143	mfdvb $0
144	mfdvb $31
145	mtdvb $0
146	mtdvb $31
147	mfdvbm $0
148	mfdvbm $31
149	mtdvbm $0
150	mtdvbm $31
151	mfiab $0
152	mfiab $31
153	mtiab $0
154	mtiab $31
155	mfiabm $0
156	mfiabm $31
157	mtiabm $0
158	mtiabm $31
159
160	# Pipeline1
161	mfhi1 $0
162	mfhi1 $31
163	mthi1 $0
164	mthi1 $31
165	mflo1 $0
166	mflo1 $31
167	mtlo1 $0
168	mtlo1 $31
169
170	# Shift amount register
171	mfsa $0
172	mfsa $31
173	mtsa $0
174	mtsa $31
175	mtsab $0, -1
176	mtsab $8, 0x8000
177	mtsab $8, 0x7FFF
178	mtsab $31, 0
179	mtsah $0, -1
180	mtsah $8, 0x8000
181	mtsah $8, 0x7FFF
182	mtsah $31, 0
183
184	movn $0, $0, $31
185	movn $31, $31, $0
186	movz $0, $0, $31
187	movz $31, $31, $0
188
189	# Floating multiply and subtract
190	msub.s $f0, $f31, $f0
191	msub.s $f31, $f0, $f31
192
193	# Floating multiply and subtract from accumulator
194	msuba.s $f0, $f31
195	msuba.s $f31, $f0
196
197	# Floating point multiply to accumulator
198	mula.s $f0, $f31
199	mula.s $f31, $f0
200
201	# Like mult but pipeline 1
202	mult1 $0, $0, $31
203	mult1 $31, $31, $0
204	mult1 $0, $31
205	mult1 $31, $0
206
207	# Like multu but pipeline 1
208	multu1 $0, $0, $31
209	multu1 $31, $31, $0
210	multu1 $0, $31
211	multu1 $31, $0
212
213	# Quadword funnel shift right variable
214	qfsrv $0, $0, $31
215	qfsrv $31, $31, $0
216
217	# Floating point reciprocal squre root
218	rsqrt.s $f0, $f31, $f0
219	rsqrt.s $f31, $f0, $f31
220
221	# Floating point subtract to accumulator
222	suba.s $f0, $f31
223	suba.s $f31, $f0
224
225	# Parallel instructions operating on 128 bit registers:
226	pabsh $0, $31
227	pabsh $31, $0
228	pabsw $0, $31
229	pabsw $31, $0
230	paddb $0, $0, $31
231	paddb $31, $31, $0
232	paddh $0, $0, $31
233	paddh $31, $31, $0
234	paddsb $0, $0, $31
235	paddsb $31, $31, $0
236	paddsh $0, $0, $31
237	paddsh $31, $31, $0
238	paddsw $0, $0, $31
239	paddsw $31, $31, $0
240	paddub $0, $0, $31
241	paddub $31, $31, $0
242	padduh $0, $0, $31
243	padduh $31, $31, $0
244	padduw $0, $0, $31
245	padduw $31, $31, $0
246	paddw $0, $0, $31
247	paddw $31, $31, $0
248	padsbh $0, $0, $31
249	padsbh $31, $31, $0
250	pand $0, $0, $31
251	pand $31, $31, $0
252	pceqb $0, $0, $31
253	pceqb $31, $31, $0
254	pceqh $0, $0, $31
255	pceqh $31, $31, $0
256	pceqw $0, $0, $31
257	pcgtb $31, $31, $0
258	pceqw $0, $0, $31
259	pceqw $31, $31, $0
260	pcgtb $0, $0, $31
261	pcgtb $31, $31, $0
262	pcgth $0, $0, $31
263	pcgth $31, $31, $0
264	pcgtw $0, $0, $31
265	pcgtw $31, $31, $0
266	pcpyh $0, $31
267	pcpyh $31, $0
268	pcpyld $0, $0, $31
269	pcpyld $31, $31, $0
270	pcpyud $0, $0, $31
271	pcpyud $31, $31, $0
272	pdivbw $0, $31
273	pdivbw $31, $0
274	pdivuw $0, $31
275	pdivuw $31, $0
276	pdivw $0, $31
277	pdivw $31, $0
278	pexch $0, $31
279	pexch $31, $0
280	pexcw $0, $31
281	pexcw $31, $0
282	pexeh $0, $31
283	pexeh $31, $0
284	pexew $0, $31
285	pexew $31, $0
286	pext5 $0, $31
287	pext5 $31, $0
288	pextlb $0, $0, $31
289	pextlb $31, $31, $0
290	pextlh $0, $0, $31
291	pextlh $31, $31, $0
292	pextlw $0, $0, $31
293	pextlw $31, $31, $0
294	pextub $0, $0, $31
295	pextub $31, $31, $0
296	pextuh $0, $0, $31
297	pextuh $31, $31, $0
298	pextuw $0, $0, $31
299	pextuw $31, $31, $0
300	phmadh $0, $0, $31
301	phmadh $31, $31, $0
302	phmsbh $0, $0, $31
303	phmsbh $31, $31, $0
304	pinteh $0, $0, $31
305	pinteh $31, $31, $0
306	pinth $0, $0, $31
307	pinth $31, $31, $0
308	plzcw $0, $31
309	plzcw $31, $0
310	pmaddh $0, $0, $31
311	pmaddh $31, $31, $0
312	pmadduw $0, $0, $31
313	pmadduw $31, $31, $0
314	pmaddw $0, $0, $31
315	pmaddw $31, $31, $0
316	pmaxh $0, $0, $31
317	pmaxh $31, $31, $0
318	pmaxw $0, $0, $31
319	pmaxw $31, $31, $0
320	pmfhi $0
321	pmfhi $31
322	pmfhl.lh $0
323	pmfhl.lh $31
324	pmfhl.lw $0
325	pmfhl.lw $31
326	pmfhl.sh $0
327	pmfhl.sh $31
328	pmfhl.slw $0
329	pmfhl.slw $31
330	pmfhl.uw $0
331	pmfhl.uw $31
332	pmflo $0
333	pmflo $31
334	pminh $0, $0, $31
335	pminh $31, $31, $0
336	pminw $0, $0, $31
337	pminw $31, $31, $0
338	pmsubh $0, $0, $31
339	pmsubh $31, $31, $0
340	pmsubw $0, $0, $31
341	pmsubw $31, $31, $0
342	pmthi $0
343	pmthi $31
344	pmthl.lw $0
345	pmthl.lw $31
346	pmtlo $0
347	pmtlo $31
348	pmulth $0, $0, $31
349	pmulth $31, $31, $0
350	pmultuw $0, $0, $31
351	pmultuw $31, $31, $0
352	pmultw $0, $0, $31
353	pmultw $31, $31, $0
354	pmultw $0, $0, $31
355	pmultw $31, $31, $0
356	pnor $0, $0, $31
357	pnor $31, $31, $0
358	por $0, $0, $31
359	por $31, $31, $0
360	ppac5 $0, $31
361	ppac5 $31, $0
362	ppacb $0, $0, $31
363	ppacb $31, $31, $0
364	ppach $0, $0, $31
365	ppach $31, $31, $0
366	ppacw $0, $0, $31
367	ppacw $31, $31, $0
368	prevh $0, $31
369	prevh $31, $0
370	prot3w $0, $31
371	prot3w $31, $0
372	psllh $31, $0, 0
373	psllh $0, $31, 31
374	psllvw $0, $31, $0
375	psllvw $31, $0, $31
376	psllw $31, $0, 0
377	psllw $0, $31, 31
378	psrah $31, $0, 0
379	psrah $0, $31, 31
380	psravw $0, $31, $0
381	psravw $31, $0, $31
382	psraw $31, $0, 0
383	psraw $0, $31, 31
384	psrlh $31, $0, 0
385	psrlh $0, $31, 31
386	psrlvw $0, $31, $0
387	psrlvw $31, $0, $31
388	psrlw $31, $0, 0
389	psrlw $0, $31, 31
390	psubb $0, $0, $31
391	psubb $31, $31, $0
392	psubh $0, $0, $31
393	psubh $31, $31, $0
394	psubsb $0, $0, $31
395	psubsb $31, $31, $0
396	psubsh $0, $0, $31
397	psubsh $31, $31, $0
398	psubsw $0, $0, $31
399	psubsw $31, $31, $0
400	psubub $0, $0, $31
401	psubub $31, $31, $0
402	psubuh $0, $0, $31
403	psubuh $31, $31, $0
404	psubuw $0, $0, $31
405	psubuw $31, $31, $0
406	psubw $0, $0, $31
407	psubw $31, $31, $0
408	pxor $0, $0, $31
409	pxor $31, $31, $0
410
411	# G1 instructions
412	mult $0, $0, $31
413	mult $31, $31, $0
414	multu $0, $0, $31
415	multu $31, $31, $0
416	mul $0, $0, $31
417	mul $31, $31, $0
418	madd $0, $0, $31
419	madd $31, $31, $0
420	madd $0, $31
421	madd $31, $0
422	maddu $0, $0, $31
423	maddu $31, $31, $0
424	maddu $0, $31
425	maddu $31, $0
426	sync
427
428	# Enable sc/ll instructions by changing ISA level:
429	.set push
430	.set mips2
431	ll $5, 0($6)
432	sc $5, 0($6)
433	.set pop
434
435	# Enable scd/lld instructions by changing ISA level:
436	.set push
437	.set mips3
438	lld $5, 0($6)
439	scd $5, 0($6)
440	.set pop
441
442	.space	8
443	.end stuff
444