Lines Matching refs:r0
30 mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register
31 bic r0, r0, #0x00000002 // disable L2 cache
32 mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register
35 mrc p15, 0, r0, c1, c0, 0
36 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
37 bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */
38 orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
39 orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */
40 mcr p15, 0, r0, c1, c0, 0
43 mrc p15, 0, r0, c1, c0, 2
44 orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)
45 mcr p15, 0, r0, c1, c0, 2
46 mov r0, #0x40000000 // Set EN bit in FPEXC
47 msr FPEXC,r0
50 LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base
51 mcr p15, 0, r0, c12, c0, 0
58 str r1, [r0, r2]
81 LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) // memory start arg0