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Searched refs:AsRegister (Results 1 – 20 of 20) sorted by relevance

/art/compiler/optimizing/
Dintrinsics_mips64.cc59 GpuRegister trg_reg = trg.AsRegister<GpuRegister>(); in MoveFromReturnRegister()
151 GpuRegister out = locations->Out().AsRegister<GpuRegister>(); in MoveFPToInt()
187 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>(); in MoveIntToFP()
226 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>(); in GenReverseBytes()
227 GpuRegister out = locations->Out().AsRegister<GpuRegister>(); in GenReverseBytes()
278 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>(); in GenNumberOfLeadingZeroes()
279 GpuRegister out = locations->Out().AsRegister<GpuRegister>(); in GenNumberOfLeadingZeroes()
313 __ Dsbh(out.AsRegister<GpuRegister>(), in.AsRegister<GpuRegister>()); in GenNumberOfTrailingZeroes()
314 __ Dshd(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>()); in GenNumberOfTrailingZeroes()
315 __ Dbitswap(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>()); in GenNumberOfTrailingZeroes()
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Dcode_generator_x86_64.cc196 Address array_len(array_loc.AsRegister<CpuRegister>(), len_offset); in EmitNativeCode()
203 __ movl(length_loc.AsRegister<CpuRegister>(), array_len); in EmitNativeCode()
205 __ shrl(length_loc.AsRegister<CpuRegister>(), Immediate(1)); in EmitNativeCode()
276 locations->Out().AsRegister<CpuRegister>()); in EmitNativeCode()
323 locations->Out().AsRegister<CpuRegister>()); in EmitNativeCode()
483 CpuRegister ref_cpu_reg = ref_.AsRegister<CpuRegister>(); in EmitNativeCode()
484 Register ref_reg = ref_cpu_reg.AsRegister(); in EmitNativeCode()
576 CpuRegister ref_cpu_reg = ref_.AsRegister<CpuRegister>(); in EmitNativeCode()
577 Register ref_reg = ref_cpu_reg.AsRegister(); in EmitNativeCode()
649 bool base_equals_value = (base.AsRegister() == value.AsRegister()); in EmitNativeCode()
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Dintrinsics_x86_64.cc94 CpuRegister src_curr_addr = locations->GetTemp(0).AsRegister<CpuRegister>(); in EmitNativeCode()
95 CpuRegister dst_curr_addr = locations->GetTemp(1).AsRegister<CpuRegister>(); in EmitNativeCode()
96 CpuRegister src_stop_addr = locations->GetTemp(2).AsRegister<CpuRegister>(); in EmitNativeCode()
150 __ movd(output.AsRegister<CpuRegister>(), input.AsFpuRegister<XmmRegister>(), is64bit); in MoveFPToInt()
156 __ movd(output.AsFpuRegister<XmmRegister>(), input.AsRegister<CpuRegister>(), is64bit); in MoveIntToFP()
198 CpuRegister out = locations->Out().AsRegister<CpuRegister>(); in GenReverseBytes()
304 CpuRegister out = output.AsRegister<CpuRegister>(); in GenAbsInteger()
305 CpuRegister mask = locations->GetTemp(0).AsRegister<CpuRegister>(); in GenAbsInteger()
485 CpuRegister out = locations->Out().AsRegister<CpuRegister>(); in GenMinMax()
486 CpuRegister op2 = op2_loc.AsRegister<CpuRegister>(); in GenMinMax()
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Dcode_generator_x86.cc145 Address array_len(array_loc.AsRegister<Register>(), len_offset); in EmitNativeCode()
152 __ movl(length_loc.AsRegister<Register>(), array_len); in EmitNativeCode()
154 __ shrl(length_loc.AsRegister<Register>(), Immediate(1)); in EmitNativeCode()
239 Register method_address = locations->InAt(0).AsRegister<Register>(); in EmitNativeCode()
241 locations->Out().AsRegister<Register>()); in EmitNativeCode()
295 Register method_address = locations->InAt(0).AsRegister<Register>(); in EmitNativeCode()
297 locations->Out().AsRegister<Register>()); in EmitNativeCode()
470 Register ref_reg = ref_.AsRegister<Register>(); in EmitNativeCode()
558 Register ref_reg = ref_.AsRegister<Register>(); in EmitNativeCode()
724 Register reg_out = out_.AsRegister<Register>(); in EmitNativeCode()
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Dintrinsics_x86.cc102 Register src = locations->InAt(0).AsRegister<Register>(); in EmitNativeCode()
104 Register dest = locations->InAt(2).AsRegister<Register>(); in EmitNativeCode()
108 Register temp1 = temp1_loc.AsRegister<Register>(); in EmitNativeCode()
109 Register temp2 = locations->GetTemp(1).AsRegister<Register>(); in EmitNativeCode()
110 Register temp3 = locations->GetTemp(2).AsRegister<Register>(); in EmitNativeCode()
133 __ leal(temp2, Address(src_pos.AsRegister<Register>(), temp1, ScaleFactor::TIMES_1, 0)); in EmitNativeCode()
157 __ leal(temp3, Address(dest_pos.AsRegister<Register>(), temp1, ScaleFactor::TIMES_1, 0)); in EmitNativeCode()
212 __ movd(output.AsRegister<Register>(), input.AsFpuRegister<XmmRegister>()); in MoveFPToInt()
228 __ movd(output.AsFpuRegister<XmmRegister>(), input.AsRegister<Register>()); in MoveIntToFP()
287 Register out = locations->Out().AsRegister<Register>(); in GenReverseBytes()
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Dcode_generator_arm.cc392 Register temp = locations->GetTemp(0).AsRegister<Register>(); in EmitNativeCode()
396 entry_address = temp_is_r0 ? out.AsRegister<Register>() : temp; in EmitNativeCode()
467 Register out = locations->Out().AsRegister<Register>(); in EmitNativeCode()
479 Register temp = locations->GetTemp(0).AsRegister<Register>(); in EmitNativeCode()
661 Register ref_reg = ref_.AsRegister<Register>(); in GenerateReadBarrierMarkRuntimeCall()
690 __ blx(entrypoint_.AsRegister<Register>()); in GenerateReadBarrierMarkRuntimeCall()
739 Register ref_reg = ref_.AsRegister<Register>(); in EmitNativeCode()
800 Register ref_reg = ref_.AsRegister<Register>(); in EmitNativeCode()
943 Register ref_reg = ref_.AsRegister<Register>(); in EmitNativeCode()
1134 Register reg_out = out_.AsRegister<Register>(); in EmitNativeCode()
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Dintrinsics_arm.cc68 __ add(base, array, ShifterOperand(pos.AsRegister<Register>(), LSL, element_size_shift)); in GenSystemArrayCopyBaseAddress()
90 __ add(end, base, ShifterOperand(copy_length.AsRegister<Register>(), LSL, element_size_shift)); in GenSystemArrayCopyEndAddress()
122 Register dest = locations->InAt(2).AsRegister<Register>(); in EmitNativeCode()
124 Register src_curr_addr = locations->GetTemp(0).AsRegister<Register>(); in EmitNativeCode()
125 Register dst_curr_addr = locations->GetTemp(1).AsRegister<Register>(); in EmitNativeCode()
126 Register src_stop_addr = locations->GetTemp(2).AsRegister<Register>(); in EmitNativeCode()
127 Register tmp = locations->GetTemp(3).AsRegister<Register>(); in EmitNativeCode()
217 __ vmovrs(output.AsRegister<Register>(), input.AsFpuRegister<SRegister>()); in MoveFPToInt()
229 __ vmovsr(output.AsFpuRegister<SRegister>(), input.AsRegister<Register>()); in MoveIntToFP()
283 Register out = locations->Out().AsRegister<Register>(); in GenNumberOfLeadingZeros()
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Dcode_generator_mips64.cc206 DCHECK_NE(out.AsRegister<GpuRegister>(), AT); in EmitNativeCode()
210 __ Sw(out.AsRegister<GpuRegister>(), AT, /* placeholder */ 0x5678); in EmitNativeCode()
261 GpuRegister out = locations->Out().AsRegister<GpuRegister>(); in EmitNativeCode()
484 GpuRegister ref_reg = ref_.AsRegister<GpuRegister>(); in EmitNativeCode()
524 DCHECK_EQ(entrypoint_.AsRegister<GpuRegister>(), T9); in EmitNativeCode()
525 __ Jalr(entrypoint_.AsRegister<GpuRegister>()); in EmitNativeCode()
579 GpuRegister ref_reg = ref_.AsRegister<GpuRegister>(); in EmitNativeCode()
646 GpuRegister offset = field_offset_.AsRegister<GpuRegister>(); in EmitNativeCode()
738 GpuRegister reg_out = out_.AsRegister<GpuRegister>(); in EmitNativeCode()
761 GpuRegister index_reg = index_.AsRegister<GpuRegister>(); in EmitNativeCode()
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Dintrinsics_mips.cc71 Register trg_reg = trg.AsRegister<Register>(); in MoveFromReturnRegister()
170 Register out = locations->Out().AsRegister<Register>(); in MoveFPToInt()
212 Register in = locations->InAt(0).AsRegister<Register>(); in MoveIntToFP()
258 Register in = locations->InAt(0).AsRegister<Register>(); in GenReverse()
259 Register out = locations->Out().AsRegister<Register>(); in GenReverse()
272 Register in = locations->InAt(0).AsRegister<Register>(); in GenReverse()
273 Register out = locations->Out().AsRegister<Register>(); in GenReverse()
446 Register out = locations->Out().AsRegister<Register>(); in GenNumberOfLeadingZeroes()
462 Register in = locations->InAt(0).AsRegister<Register>(); in GenNumberOfLeadingZeroes()
494 Register out = locations->Out().AsRegister<Register>(); in GenNumberOfTrailingZeroes()
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Dcode_generator_mips.cc257 Register base = isR6 ? ZERO : locations->InAt(0).AsRegister<Register>(); in EmitNativeCode()
258 DCHECK_NE(out.AsRegister<Register>(), AT); in EmitNativeCode()
263 __ StoreToOffset(kStoreWord, out.AsRegister<Register>(), TMP, /* placeholder */ 0x5678); in EmitNativeCode()
313 Register base = isR6 ? ZERO : locations->InAt(0).AsRegister<Register>(); in EmitNativeCode()
314 Register out = locations->Out().AsRegister<Register>(); in EmitNativeCode()
538 Register ref_reg = ref_.AsRegister<Register>(); in EmitNativeCode()
578 DCHECK_EQ(entrypoint_.AsRegister<Register>(), T9); in EmitNativeCode()
579 __ Jalr(entrypoint_.AsRegister<Register>()); in EmitNativeCode()
634 Register ref_reg = ref_.AsRegister<Register>(); in EmitNativeCode()
802 Register reg_out = out_.AsRegister<Register>(); in EmitNativeCode()
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Dcode_generator_vector_x86_64.cc56 __ movd(reg, locations->InAt(0).AsRegister<CpuRegister>()); in VisitVecReplicateScalar()
64 __ movd(reg, locations->InAt(0).AsRegister<CpuRegister>()); in VisitVecReplicateScalar()
70 __ movd(reg, locations->InAt(0).AsRegister<CpuRegister>()); in VisitVecReplicateScalar()
75 __ movd(reg, locations->InAt(0).AsRegister<CpuRegister>()); // is 64-bit in VisitVecReplicateScalar()
775 return CodeGeneratorX86_64::ArrayAddress(base.AsRegister<CpuRegister>(), index, scale, offset); in CreateVecMemRegisters()
Dcode_generator_vector_x86.cc59 __ movd(reg, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
67 __ movd(reg, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
73 __ movd(reg, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
786 return CodeGeneratorX86::ArrayAddress(base.AsRegister<Register>(), index, scale, offset); in CreateVecMemRegisters()
Dlocations.h181 T AsRegister() const { in AsRegister() function
/art/compiler/utils/x86_64/
Dmanaged_register_x86_64.cc63 Register low = AsRegisterPairLow().AsRegister(); in Overlaps()
64 Register high = AsRegisterPairHigh().AsRegister(); in Overlaps()
101 os << "CPU: " << static_cast<int>(AsCpuRegister().AsRegister()); in Print()
Dconstants_x86_64.h34 constexpr Register AsRegister() const { in AsRegister() function
Dassembler_x86_64.cc28 return os << reg.AsRegister(); in operator <<()
1815 const bool src_rax = src.AsRegister() == RAX; in xchgl()
1816 const bool dst_rax = dst.AsRegister() == RAX; in xchgl()
1835 const bool src_rax = src.AsRegister() == RAX; in xchgq()
1836 const bool dst_rax = dst.AsRegister() == RAX; in xchgq()
1990 if (immediate.is_uint8() && reg.AsRegister() < 4) { in testl()
1992 if (reg.AsRegister() == RAX) { in testl()
1996 EmitUint8(0xC0 + reg.AsRegister()); in testl()
1999 } else if (reg.AsRegister() == RAX) { in testl()
2842 if (dst.NeedsRex() || dst.AsRegister() > 3) { in setcc()
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Dassembler_x86_64.h181 CHECK_EQ(base_in.AsRegister(), RSP); in Address()
212 CHECK_NE(index_in.AsRegister(), RSP); // Illegal addressing mode. in Address()
219 CHECK_NE(index_in.AsRegister(), RSP); // Illegal addressing mode. in Address()
Djni_macro_assembler_x86_64.cc52 cfi().RelOffset(DWARFReg(spill.AsCpuRegister().AsRegister()), 0); in BuildFrame()
129 cfi().Restore(DWARFReg(spill.AsCpuRegister().AsRegister())); in RemoveFrame()
Dassembler_x86_64_test.cc125 return a.AsRegister() < b.AsRegister(); in operator ()()
/art/compiler/jni/quick/x86_64/
Dcalling_convention_x86_64.cc59 result |= (1 << r.AsX86_64().AsCpuRegister().AsRegister()); in CalculateCoreCalleeSpillMask()