| /art/compiler/trampolines/ |
| D | trampoline_compiler.cc | 145 __ LoadFromOffset(kLoadWord, T9, A0, offset.Int32Value()); in CreateTrampoline()
148 __ LoadFromOffset(kLoadWord, T9, A0, JNIEnvExt::SelfOffset(4).Int32Value()); in CreateTrampoline()
149 __ LoadFromOffset(kLoadWord, T9, T9, offset.Int32Value()); in CreateTrampoline()
152 __ LoadFromOffset(kLoadWord, T9, S1, offset.Int32Value()); in CreateTrampoline()
154 __ Jr(T9); in CreateTrampoline()
177 __ LoadFromOffset(kLoadDoubleword, T9, A0, offset.Int32Value()); in CreateTrampoline()
180 __ LoadFromOffset(kLoadDoubleword, T9, A0, JNIEnvExt::SelfOffset(8).Int32Value()); in CreateTrampoline()
181 __ LoadFromOffset(kLoadDoubleword, T9, T9, offset.Int32Value()); in CreateTrampoline()
184 __ LoadFromOffset(kLoadDoubleword, T9, S1, offset.Int32Value()); in CreateTrampoline()
186 __ Jr(T9); in CreateTrampoline()
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| /art/runtime/arch/mips/ |
| D | context_mips.cc | 31 gprs_[T9] = &t9_; in Reset()
35 t9_ = MipsContext::kBadGprBase + T9; in Reset()
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| D | registers_mips.h | 55 T9 = 25, enumerator
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| D | context_mips.h | 44 SetGPR(T9, new_pc); in SetPC()
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| D | fault_handler_mips.cc | 141 sc->sc_regs[mips::T9] = sc->sc_pc; // make sure T9 points to the function in Action()
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| D | quick_method_frame_info_mips.h | 43 (1 << art::mips::S0) | (1 << art::mips::S1) | (1 << art::mips::T8) | (1 << art::mips::T9);
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| /art/runtime/arch/mips64/ |
| D | context_mips64.cc | 31 gprs_[T9] = &t9_; in Reset()
35 t9_ = Mips64Context::kBadGprBase + T9; in Reset()
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| D | context_mips64.h | 44 SetGPR(T9, new_pc); in SetPC()
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| D | registers_mips64.h | 55 T9 = 25, enumerator
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| D | fault_handler_mips64.cc | 143 sc->sc_regs[mips64::T9] = sc->sc_pc; // make sure T9 points to the function in Action()
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| D | quick_method_frame_info_mips64.h | 47 (1 << art::mips64::T9);
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| /art/compiler/jni/quick/mips64/ |
| D | calling_convention_mips64.cc | 66 return Mips64ManagedRegister::FromGpuRegister(T9); in InterproceduralScratchRegister()
70 return Mips64ManagedRegister::FromGpuRegister(T9); in InterproceduralScratchRegister()
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| /art/compiler/jni/quick/mips/ |
| D | calling_convention_mips.cc | 77 return MipsManagedRegister::FromCoreRegister(T9); in InterproceduralScratchRegister()
81 return MipsManagedRegister::FromCoreRegister(T9); in InterproceduralScratchRegister()
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| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 82 registers_.push_back(new mips::Register(mips::T9)); in SetUpHelpers()
115 secondary_register_names_.emplace(mips::Register(mips::T9), "t9"); in SetUpHelpers()
2516 __ LlR2(mips::T9, mips::T0, 0); in TEST_F()
2517 __ Jalr(mips::T9); // T9 dependency. in TEST_F()
2520 __ Jalr(mips::T9); // RA dependency. in TEST_F()
2523 __ Jalr(mips::T1, mips::T9); // T1 dependency. in TEST_F()
2525 __ ScR2(mips::T9, mips::T0, 0); in TEST_F()
2526 __ Jr(mips::T9); // T9 dependency. in TEST_F()
2538 __ Jalr(mips::T9); // No preceding instruction for the delay slot. in TEST_F()
2660 __ Jalr(mips::T9); in TEST_F()
[all …]
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| D | assembler_mips32r6_test.cc | 112 registers_.push_back(new mips::Register(mips::T9)); in SetUpHelpers()
145 secondary_register_names_.emplace(mips::Register(mips::T9), "t9"); in SetUpHelpers()
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| D | assembler_mips.cc | 3780 LoadFromOffset(kLoadWord, T9, S1, in EmitExceptionPoll()
3782 Jr(T9); in EmitExceptionPoll()
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| /art/compiler/optimizing/ |
| D | code_generator_mips64.cc | 524 DCHECK_EQ(entrypoint_.AsRegister<GpuRegister>(), T9); in EmitNativeCode()
1625 blocked_core_registers_[T9] = true; in SetupBlockedRegisters()
1684 __ LoadFromOffset(kLoadDoubleword, T9, TR, entry_point_offset); in GenerateInvokeRuntime()
1685 __ Jalr(T9); in GenerateInvokeRuntime()
4301 Location temp = Location::RegisterLocation(T9); in GenerateGcRootFieldLoad()
4828 __ LoadFromOffset(kLoadDoubleword, T9, temp, entry_point.Int32Value()); in VisitInvokeInterface()
4830 __ Jalr(T9); in VisitInvokeInterface()
5011 T9, in GenerateStaticOrDirectCall()
5016 __ Jalr(T9); in GenerateStaticOrDirectCall()
5068 __ LoadFromOffset(kLoadDoubleword, T9, temp, entry_point.Int32Value()); in GenerateVirtualCall()
[all …]
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| D | code_generator_mips.cc | 578 DCHECK_EQ(entrypoint_.AsRegister<Register>(), T9); in EmitNativeCode()
1796 blocked_core_registers_[T9] = true; in SetupBlockedRegisters()
1865 __ LoadFromOffset(kLoadWord, T9, TR, entry_point_offset); in GenerateInvokeRuntime()
1866 __ Jalr(T9); in GenerateInvokeRuntime()
6199 Location temp = Location::RegisterLocation(T9); in GenerateGcRootFieldLoad()
6718 __ LoadFromOffset(kLoadWord, T9, temp, entry_point.Int32Value()); in VisitInvokeInterface()
6720 __ Jalr(T9); in VisitInvokeInterface()
6982 T9, in GenerateStaticOrDirectCall()
6987 __ Jalr(T9); in GenerateStaticOrDirectCall()
7039 __ LoadFromOffset(kLoadWord, T9, temp, entry_point.Int32Value()); in GenerateVirtualCall()
[all …]
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 115 registers_.push_back(new mips64::GpuRegister(mips64::T9)); in SetUpHelpers()
148 secondary_register_names_.emplace(mips64::GpuRegister(mips64::T9), "t9"); in SetUpHelpers()
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| D | assembler_mips64.cc | 3246 T9, in EmitExceptionPoll()
3249 Jr(T9); in EmitExceptionPoll()
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