Searched refs:ADDIS (Results 1 – 13 of 13) sorted by relevance
/external/pcre/dist2/src/sljit/ |
D | sljitNativePPC_64.c | 58 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16))); in load_immediate() 76 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(tmp >> 48))); in load_immediate() 112 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 48))); in load_immediate() 225 return push_inst(compiler, ADDIS | D(dst) | A(src1) | compiler->imm); in emit_single_op() 235 …return push_inst(compiler, ADDIS | D(dst) | A(dst) | (((compiler->imm >> 16) & 0xffff) + ((compile… in emit_single_op() 394 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(init_value >> 48))); in emit_const()
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D | sljitNativePPC_32.c | 37 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16))); in load_immediate() 106 return push_inst(compiler, ADDIS | D(dst) | A(src1) | compiler->imm); in emit_single_op() 115 …return push_inst(compiler, ADDIS | D(dst) | A(dst) | (((compiler->imm >> 16) & 0xffff) + ((compile… in emit_single_op() 249 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(init_value >> 16))); in emit_const()
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D | sljitNativePPC_common.c | 141 #define ADDIS (HI(15)) macro 1013 FAIL_IF(push_inst(compiler, ADDIS | D(arg) | A(arg) | IMM(high_short >> 16))); in getput_arg() 1024 FAIL_IF(push_inst(compiler, ADDIS | D(tmp_r) | A(arg & REG_MASK) | IMM(high_short >> 16))); in getput_arg() 1841 FAIL_IF(push_inst(compiler, ADDIS | D(TMP_REG2) | A(0) | 0x4330)); in sljit_emit_fop1_conv_f64_from_sw() 1846 FAIL_IF(push_inst(compiler, ADDIS | D(TMP_REG1) | A(0) | 0x8000)); in sljit_emit_fop1_conv_f64_from_sw()
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/external/v8/src/ppc/ |
D | assembler-ppc-inl.h | 486 bool overflowed = (opcode == ADDIS); in IsConstantPoolLoadStart() 510 if ((opcode != ADDIS) || !GetRA(instr).is(kConstantPoolRegister)) { in IsConstantPoolLoadEnd()
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D | constants-ppc.h | 106 ADDIS = 15 << 26, // Add Immediate Shifted enumerator
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D | disasm-ppc.cc | 1146 case ADDIS: { in InstructionDecode()
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D | assembler-ppc.cc | 288 return ((instr & kOpcodeMask) == ADDIS) && GetRA(instr).is(r0); in IsLis() 948 d_form(ADDIS, dst, src, imm.imm_, true); in addis() 1106 d_form(ADDIS, dst, r0, imm.imm_, true); in lis()
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D | simulator-ppc.cc | 3420 case ADDIS: { in ExecuteGeneric()
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D | macro-assembler-ppc.cc | 3324 cmpi(r0, Operand(ADDIS >> 26)); in DecodeConstantPoolOffset()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCAsmPrinter.cpp | 827 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ADDIS) in EmitInstruction() 937 MCInstBuilder(Subtarget->isPPC64() ? PPC::ADDIS8 : PPC::ADDIS) in EmitInstruction() 1211 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ADDIS) in EmitFunctionBodyStart()
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D | PPCInstrInfo.td | 1947 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm), 2678 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 2732 (ADDIS $in, tglobaltlsaddr:$g)>; 2736 (ADDIS $in, tglobaladdr:$g)>; 2738 (ADDIS $in, tconstpool:$g)>; 2740 (ADDIS $in, tjumptable:$g)>; 2742 (ADDIS $in, tblockaddress:$g)>;
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCInstrInfo.td | 865 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm), 1362 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 1421 (ADDIS GPRC:$in, tglobaladdr:$g)>; 1423 (ADDIS GPRC:$in, tconstpool:$g)>; 1425 (ADDIS GPRC:$in, tjumptable:$g)>; 1427 (ADDIS GPRC:$in, tblockaddress:$g)>;
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/external/llvm/lib/Target/PowerPC/AsmParser/ |
D | PPCAsmParser.cpp | 897 TmpInst.setOpcode(PPC::ADDIS); in ProcessInstruction()
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