1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subset of the 32-bit PowerPC instruction set, as used 11// by the PowerPC instruction selector. 12// 13//===----------------------------------------------------------------------===// 14 15include "PPCInstrFormats.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC specific type constraints. 19// 20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22]>; 23def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 24 SDTCisVT<0, f64>, SDTCisPtrTy<1> 25]>; 26 27def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 28def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 29 SDTCisVT<1, i32> ]>; 30def SDT_PPCvperm : SDTypeProfile<1, 3, [ 31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 32]>; 33 34def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>, 35 SDTCisVec<1>, SDTCisInt<2> 36]>; 37 38def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>, 39 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 40]>; 41 42def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>, 43 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 44]>; 45 46def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 47 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 48]>; 49 50def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 51 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 52]>; 53 54def SDT_PPClbrx : SDTypeProfile<1, 2, [ 55 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 56]>; 57def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 58 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 59]>; 60 61def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 62 SDTCisPtrTy<0>, SDTCisVT<1, i32> 63]>; 64 65def tocentry32 : Operand<iPTR> { 66 let MIOperandInfo = (ops i32imm:$imm); 67} 68 69def SDT_PPCqvfperm : SDTypeProfile<1, 3, [ 70 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3> 71]>; 72def SDT_PPCqvgpci : SDTypeProfile<1, 1, [ 73 SDTCisVec<0>, SDTCisInt<1> 74]>; 75def SDT_PPCqvaligni : SDTypeProfile<1, 3, [ 76 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3> 77]>; 78def SDT_PPCqvesplati : SDTypeProfile<1, 2, [ 79 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2> 80]>; 81 82def SDT_PPCqbflt : SDTypeProfile<1, 1, [ 83 SDTCisVec<0>, SDTCisVec<1> 84]>; 85 86def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [ 87 SDTCisVec<0>, SDTCisPtrTy<1> 88]>; 89 90//===----------------------------------------------------------------------===// 91// PowerPC specific DAG Nodes. 92// 93 94def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 95def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 96 97def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 98def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 99def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 100def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 101def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 102def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 103def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 104def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 105def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 106 [SDNPHasChain, SDNPMayStore]>; 107def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 108 [SDNPHasChain, SDNPMayLoad]>; 109def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 110 [SDNPHasChain, SDNPMayLoad]>; 111 112// Extract FPSCR (not modeled at the DAG level). 113def PPCmffs : SDNode<"PPCISD::MFFS", 114 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>; 115 116// Perform FADD in round-to-zero mode. 117def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 118 119 120def PPCfsel : SDNode<"PPCISD::FSEL", 121 // Type constraint for fsel. 122 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 123 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 124 125def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 126def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 127def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, 128 [SDNPMayLoad, SDNPMemOperand]>; 129def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 130def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 131 132def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>; 133 134def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 135def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 136 [SDNPMayLoad]>; 137def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 138def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 139def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 140def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 141def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR", 142 SDTypeProfile<1, 3, [ 143 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 144 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 145def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 146def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 147def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 148def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR", 149 SDTypeProfile<1, 3, [ 150 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 151 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 152def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>; 153def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 154 155def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 156def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>; 157def PPCxxinsert : SDNode<"PPCISD::XXINSERT", SDT_PPCVecInsert, []>; 158def PPCvecshl : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>; 159 160def PPCqvfperm : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>; 161def PPCqvgpci : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>; 162def PPCqvaligni : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>; 163def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>; 164 165def PPCqbflt : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>; 166 167def PPCqvlfsb : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb, 168 [SDNPHasChain, SDNPMayLoad]>; 169 170def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>; 171 172// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 173// amounts. These nodes are generated by the multi-precision shift code. 174def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 175def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 176def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 177 178// These are target-independent nodes, but have target-specific formats. 179def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 180 [SDNPHasChain, SDNPOutGlue]>; 181def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 182 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 183 184def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 185def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 186 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 187 SDNPVariadic]>; 188def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 189 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 190 SDNPVariadic]>; 191def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 192 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 193def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 194 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 195 SDNPVariadic]>; 196def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC", 197 SDTypeProfile<0, 1, []>, 198 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 199 SDNPVariadic]>; 200 201def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 202 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 203 204def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 205 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 206 207def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 208 SDTypeProfile<1, 1, [SDTCisInt<0>, 209 SDTCisPtrTy<1>]>, 210 [SDNPHasChain, SDNPSideEffect]>; 211def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 212 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 213 [SDNPHasChain, SDNPSideEffect]>; 214 215def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 216def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, 217 [SDNPHasChain, SDNPSideEffect]>; 218 219def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone, 220 [SDNPHasChain, SDNPSideEffect]>; 221def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>; 222def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc, 223 [SDNPHasChain, SDNPSideEffect]>; 224 225def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 226def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>; 227 228def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 229 [SDNPHasChain, SDNPOptInGlue]>; 230 231def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 232 [SDNPHasChain, SDNPMayLoad]>; 233def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 234 [SDNPHasChain, SDNPMayStore]>; 235 236// Instructions to set/unset CR bit 6 for SVR4 vararg calls 237def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 238 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 239def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 240 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 241 242// Instructions to support dynamic alloca. 243def SDTDynOp : SDTypeProfile<1, 2, []>; 244def SDTDynAreaOp : SDTypeProfile<1, 1, []>; 245def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 246def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>; 247 248//===----------------------------------------------------------------------===// 249// PowerPC specific transformation functions and pattern fragments. 250// 251 252def SHL32 : SDNodeXForm<imm, [{ 253 // Transformation function: 31 - imm 254 return getI32Imm(31 - N->getZExtValue(), SDLoc(N)); 255}]>; 256 257def SRL32 : SDNodeXForm<imm, [{ 258 // Transformation function: 32 - imm 259 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N)) 260 : getI32Imm(0, SDLoc(N)); 261}]>; 262 263def LO16 : SDNodeXForm<imm, [{ 264 // Transformation function: get the low 16 bits. 265 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N)); 266}]>; 267 268def HI16 : SDNodeXForm<imm, [{ 269 // Transformation function: shift the immediate value down into the low bits. 270 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N)); 271}]>; 272 273def HA16 : SDNodeXForm<imm, [{ 274 // Transformation function: shift the immediate value down into the low bits. 275 int Val = N->getZExtValue(); 276 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); 277}]>; 278def MB : SDNodeXForm<imm, [{ 279 // Transformation function: get the start bit of a mask 280 unsigned mb = 0, me; 281 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 282 return getI32Imm(mb, SDLoc(N)); 283}]>; 284 285def ME : SDNodeXForm<imm, [{ 286 // Transformation function: get the end bit of a mask 287 unsigned mb, me = 0; 288 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 289 return getI32Imm(me, SDLoc(N)); 290}]>; 291def maskimm32 : PatLeaf<(imm), [{ 292 // maskImm predicate - True if immediate is a run of ones. 293 unsigned mb, me; 294 if (N->getValueType(0) == MVT::i32) 295 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 296 else 297 return false; 298}]>; 299 300def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ 301 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 302 // sign extended field. Used by instructions like 'addi'. 303 return (int32_t)Imm == (short)Imm; 304}]>; 305def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ 306 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 307 // sign extended field. Used by instructions like 'addi'. 308 return (int64_t)Imm == (short)Imm; 309}]>; 310def immZExt16 : PatLeaf<(imm), [{ 311 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 312 // field. Used by instructions like 'ori'. 313 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 314}], LO16>; 315 316// imm16Shifted* - These match immediates where the low 16-bits are zero. There 317// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 318// identical in 32-bit mode, but in 64-bit mode, they return true if the 319// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 320// clear). 321def imm16ShiftedZExt : PatLeaf<(imm), [{ 322 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 323 // immediate are set. Used by instructions like 'xoris'. 324 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 325}], HI16>; 326 327def imm16ShiftedSExt : PatLeaf<(imm), [{ 328 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 329 // immediate are set. Used by instructions like 'addis'. Identical to 330 // imm16ShiftedZExt in 32-bit mode. 331 if (N->getZExtValue() & 0xFFFF) return false; 332 if (N->getValueType(0) == MVT::i32) 333 return true; 334 // For 64-bit, make sure it is sext right. 335 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 336}], HI16>; 337 338def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{ 339 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit 340 // zero extended field. 341 return isUInt<32>(Imm); 342}]>; 343 344// Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 345// restricted memrix (4-aligned) constants are alignment sensitive. If these 346// offsets are hidden behind TOC entries than the values of the lower-order 347// bits cannot be checked directly. As a result, we need to also incorporate 348// an alignment check into the relevant patterns. 349 350def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 351 return cast<LoadSDNode>(N)->getAlignment() >= 4; 352}]>; 353def aligned4store : PatFrag<(ops node:$val, node:$ptr), 354 (store node:$val, node:$ptr), [{ 355 return cast<StoreSDNode>(N)->getAlignment() >= 4; 356}]>; 357def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 358 return cast<LoadSDNode>(N)->getAlignment() >= 4; 359}]>; 360def aligned4pre_store : PatFrag< 361 (ops node:$val, node:$base, node:$offset), 362 (pre_store node:$val, node:$base, node:$offset), [{ 363 return cast<StoreSDNode>(N)->getAlignment() >= 4; 364}]>; 365 366def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 367 return cast<LoadSDNode>(N)->getAlignment() < 4; 368}]>; 369def unaligned4store : PatFrag<(ops node:$val, node:$ptr), 370 (store node:$val, node:$ptr), [{ 371 return cast<StoreSDNode>(N)->getAlignment() < 4; 372}]>; 373def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 374 return cast<LoadSDNode>(N)->getAlignment() < 4; 375}]>; 376 377//===----------------------------------------------------------------------===// 378// PowerPC Flag Definitions. 379 380class isPPC64 { bit PPC64 = 1; } 381class isDOT { bit RC = 1; } 382 383class RegConstraint<string C> { 384 string Constraints = C; 385} 386class NoEncode<string E> { 387 string DisableEncoding = E; 388} 389 390 391//===----------------------------------------------------------------------===// 392// PowerPC Operand Definitions. 393 394// In the default PowerPC assembler syntax, registers are specified simply 395// by number, so they cannot be distinguished from immediate values (without 396// looking at the opcode). This means that the default operand matching logic 397// for the asm parser does not work, and we need to specify custom matchers. 398// Since those can only be specified with RegisterOperand classes and not 399// directly on the RegisterClass, all instructions patterns used by the asm 400// parser need to use a RegisterOperand (instead of a RegisterClass) for 401// all their register operands. 402// For this purpose, we define one RegisterOperand for each RegisterClass, 403// using the same name as the class, just in lower case. 404 405def PPCRegGPRCAsmOperand : AsmOperandClass { 406 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber"; 407} 408def gprc : RegisterOperand<GPRC> { 409 let ParserMatchClass = PPCRegGPRCAsmOperand; 410} 411def PPCRegG8RCAsmOperand : AsmOperandClass { 412 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber"; 413} 414def g8rc : RegisterOperand<G8RC> { 415 let ParserMatchClass = PPCRegG8RCAsmOperand; 416} 417def PPCRegGPRCNoR0AsmOperand : AsmOperandClass { 418 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber"; 419} 420def gprc_nor0 : RegisterOperand<GPRC_NOR0> { 421 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand; 422} 423def PPCRegG8RCNoX0AsmOperand : AsmOperandClass { 424 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber"; 425} 426def g8rc_nox0 : RegisterOperand<G8RC_NOX0> { 427 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand; 428} 429def PPCRegF8RCAsmOperand : AsmOperandClass { 430 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber"; 431} 432def f8rc : RegisterOperand<F8RC> { 433 let ParserMatchClass = PPCRegF8RCAsmOperand; 434} 435def PPCRegF4RCAsmOperand : AsmOperandClass { 436 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber"; 437} 438def f4rc : RegisterOperand<F4RC> { 439 let ParserMatchClass = PPCRegF4RCAsmOperand; 440} 441def PPCRegVRRCAsmOperand : AsmOperandClass { 442 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber"; 443} 444def vrrc : RegisterOperand<VRRC> { 445 let ParserMatchClass = PPCRegVRRCAsmOperand; 446} 447def PPCRegCRBITRCAsmOperand : AsmOperandClass { 448 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber"; 449} 450def crbitrc : RegisterOperand<CRBITRC> { 451 let ParserMatchClass = PPCRegCRBITRCAsmOperand; 452} 453def PPCRegCRRCAsmOperand : AsmOperandClass { 454 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber"; 455} 456def crrc : RegisterOperand<CRRC> { 457 let ParserMatchClass = PPCRegCRRCAsmOperand; 458} 459def crrc0 : RegisterOperand<CRRC0> { 460 let ParserMatchClass = PPCRegCRRCAsmOperand; 461} 462 463def PPCU1ImmAsmOperand : AsmOperandClass { 464 let Name = "U1Imm"; let PredicateMethod = "isU1Imm"; 465 let RenderMethod = "addImmOperands"; 466} 467def u1imm : Operand<i32> { 468 let PrintMethod = "printU1ImmOperand"; 469 let ParserMatchClass = PPCU1ImmAsmOperand; 470} 471 472def PPCU2ImmAsmOperand : AsmOperandClass { 473 let Name = "U2Imm"; let PredicateMethod = "isU2Imm"; 474 let RenderMethod = "addImmOperands"; 475} 476def u2imm : Operand<i32> { 477 let PrintMethod = "printU2ImmOperand"; 478 let ParserMatchClass = PPCU2ImmAsmOperand; 479} 480 481def PPCU3ImmAsmOperand : AsmOperandClass { 482 let Name = "U3Imm"; let PredicateMethod = "isU3Imm"; 483 let RenderMethod = "addImmOperands"; 484} 485def u3imm : Operand<i32> { 486 let PrintMethod = "printU3ImmOperand"; 487 let ParserMatchClass = PPCU3ImmAsmOperand; 488} 489 490def PPCU4ImmAsmOperand : AsmOperandClass { 491 let Name = "U4Imm"; let PredicateMethod = "isU4Imm"; 492 let RenderMethod = "addImmOperands"; 493} 494def u4imm : Operand<i32> { 495 let PrintMethod = "printU4ImmOperand"; 496 let ParserMatchClass = PPCU4ImmAsmOperand; 497} 498def PPCS5ImmAsmOperand : AsmOperandClass { 499 let Name = "S5Imm"; let PredicateMethod = "isS5Imm"; 500 let RenderMethod = "addImmOperands"; 501} 502def s5imm : Operand<i32> { 503 let PrintMethod = "printS5ImmOperand"; 504 let ParserMatchClass = PPCS5ImmAsmOperand; 505 let DecoderMethod = "decodeSImmOperand<5>"; 506} 507def PPCU5ImmAsmOperand : AsmOperandClass { 508 let Name = "U5Imm"; let PredicateMethod = "isU5Imm"; 509 let RenderMethod = "addImmOperands"; 510} 511def u5imm : Operand<i32> { 512 let PrintMethod = "printU5ImmOperand"; 513 let ParserMatchClass = PPCU5ImmAsmOperand; 514 let DecoderMethod = "decodeUImmOperand<5>"; 515} 516def PPCU6ImmAsmOperand : AsmOperandClass { 517 let Name = "U6Imm"; let PredicateMethod = "isU6Imm"; 518 let RenderMethod = "addImmOperands"; 519} 520def u6imm : Operand<i32> { 521 let PrintMethod = "printU6ImmOperand"; 522 let ParserMatchClass = PPCU6ImmAsmOperand; 523 let DecoderMethod = "decodeUImmOperand<6>"; 524} 525def PPCU7ImmAsmOperand : AsmOperandClass { 526 let Name = "U7Imm"; let PredicateMethod = "isU7Imm"; 527 let RenderMethod = "addImmOperands"; 528} 529def u7imm : Operand<i32> { 530 let PrintMethod = "printU7ImmOperand"; 531 let ParserMatchClass = PPCU7ImmAsmOperand; 532 let DecoderMethod = "decodeUImmOperand<7>"; 533} 534def PPCU8ImmAsmOperand : AsmOperandClass { 535 let Name = "U8Imm"; let PredicateMethod = "isU8Imm"; 536 let RenderMethod = "addImmOperands"; 537} 538def u8imm : Operand<i32> { 539 let PrintMethod = "printU8ImmOperand"; 540 let ParserMatchClass = PPCU8ImmAsmOperand; 541 let DecoderMethod = "decodeUImmOperand<8>"; 542} 543def PPCU10ImmAsmOperand : AsmOperandClass { 544 let Name = "U10Imm"; let PredicateMethod = "isU10Imm"; 545 let RenderMethod = "addImmOperands"; 546} 547def u10imm : Operand<i32> { 548 let PrintMethod = "printU10ImmOperand"; 549 let ParserMatchClass = PPCU10ImmAsmOperand; 550 let DecoderMethod = "decodeUImmOperand<10>"; 551} 552def PPCU12ImmAsmOperand : AsmOperandClass { 553 let Name = "U12Imm"; let PredicateMethod = "isU12Imm"; 554 let RenderMethod = "addImmOperands"; 555} 556def u12imm : Operand<i32> { 557 let PrintMethod = "printU12ImmOperand"; 558 let ParserMatchClass = PPCU12ImmAsmOperand; 559 let DecoderMethod = "decodeUImmOperand<12>"; 560} 561def PPCS16ImmAsmOperand : AsmOperandClass { 562 let Name = "S16Imm"; let PredicateMethod = "isS16Imm"; 563 let RenderMethod = "addS16ImmOperands"; 564} 565def s16imm : Operand<i32> { 566 let PrintMethod = "printS16ImmOperand"; 567 let EncoderMethod = "getImm16Encoding"; 568 let ParserMatchClass = PPCS16ImmAsmOperand; 569 let DecoderMethod = "decodeSImmOperand<16>"; 570} 571def PPCU16ImmAsmOperand : AsmOperandClass { 572 let Name = "U16Imm"; let PredicateMethod = "isU16Imm"; 573 let RenderMethod = "addU16ImmOperands"; 574} 575def u16imm : Operand<i32> { 576 let PrintMethod = "printU16ImmOperand"; 577 let EncoderMethod = "getImm16Encoding"; 578 let ParserMatchClass = PPCU16ImmAsmOperand; 579 let DecoderMethod = "decodeUImmOperand<16>"; 580} 581def PPCS17ImmAsmOperand : AsmOperandClass { 582 let Name = "S17Imm"; let PredicateMethod = "isS17Imm"; 583 let RenderMethod = "addS16ImmOperands"; 584} 585def s17imm : Operand<i32> { 586 // This operand type is used for addis/lis to allow the assembler parser 587 // to accept immediates in the range -65536..65535 for compatibility with 588 // the GNU assembler. The operand is treated as 16-bit otherwise. 589 let PrintMethod = "printS16ImmOperand"; 590 let EncoderMethod = "getImm16Encoding"; 591 let ParserMatchClass = PPCS17ImmAsmOperand; 592 let DecoderMethod = "decodeSImmOperand<16>"; 593} 594def PPCDirectBrAsmOperand : AsmOperandClass { 595 let Name = "DirectBr"; let PredicateMethod = "isDirectBr"; 596 let RenderMethod = "addBranchTargetOperands"; 597} 598def directbrtarget : Operand<OtherVT> { 599 let PrintMethod = "printBranchOperand"; 600 let EncoderMethod = "getDirectBrEncoding"; 601 let ParserMatchClass = PPCDirectBrAsmOperand; 602} 603def absdirectbrtarget : Operand<OtherVT> { 604 let PrintMethod = "printAbsBranchOperand"; 605 let EncoderMethod = "getAbsDirectBrEncoding"; 606 let ParserMatchClass = PPCDirectBrAsmOperand; 607} 608def PPCCondBrAsmOperand : AsmOperandClass { 609 let Name = "CondBr"; let PredicateMethod = "isCondBr"; 610 let RenderMethod = "addBranchTargetOperands"; 611} 612def condbrtarget : Operand<OtherVT> { 613 let PrintMethod = "printBranchOperand"; 614 let EncoderMethod = "getCondBrEncoding"; 615 let ParserMatchClass = PPCCondBrAsmOperand; 616} 617def abscondbrtarget : Operand<OtherVT> { 618 let PrintMethod = "printAbsBranchOperand"; 619 let EncoderMethod = "getAbsCondBrEncoding"; 620 let ParserMatchClass = PPCCondBrAsmOperand; 621} 622def calltarget : Operand<iPTR> { 623 let PrintMethod = "printBranchOperand"; 624 let EncoderMethod = "getDirectBrEncoding"; 625 let ParserMatchClass = PPCDirectBrAsmOperand; 626} 627def abscalltarget : Operand<iPTR> { 628 let PrintMethod = "printAbsBranchOperand"; 629 let EncoderMethod = "getAbsDirectBrEncoding"; 630 let ParserMatchClass = PPCDirectBrAsmOperand; 631} 632def PPCCRBitMaskOperand : AsmOperandClass { 633 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask"; 634} 635def crbitm: Operand<i8> { 636 let PrintMethod = "printcrbitm"; 637 let EncoderMethod = "get_crbitm_encoding"; 638 let DecoderMethod = "decodeCRBitMOperand"; 639 let ParserMatchClass = PPCCRBitMaskOperand; 640} 641// Address operands 642// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode). 643def PPCRegGxRCNoR0Operand : AsmOperandClass { 644 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; 645} 646def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> { 647 let ParserMatchClass = PPCRegGxRCNoR0Operand; 648} 649// A version of ptr_rc usable with the asm parser. 650def PPCRegGxRCOperand : AsmOperandClass { 651 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber"; 652} 653def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> { 654 let ParserMatchClass = PPCRegGxRCOperand; 655} 656 657def PPCDispRIOperand : AsmOperandClass { 658 let Name = "DispRI"; let PredicateMethod = "isS16Imm"; 659 let RenderMethod = "addS16ImmOperands"; 660} 661def dispRI : Operand<iPTR> { 662 let ParserMatchClass = PPCDispRIOperand; 663} 664def PPCDispRIXOperand : AsmOperandClass { 665 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4"; 666 let RenderMethod = "addImmOperands"; 667} 668def dispRIX : Operand<iPTR> { 669 let ParserMatchClass = PPCDispRIXOperand; 670} 671def PPCDispRIX16Operand : AsmOperandClass { 672 let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16"; 673 let RenderMethod = "addImmOperands"; 674} 675def dispRIX16 : Operand<iPTR> { 676 let ParserMatchClass = PPCDispRIX16Operand; 677} 678def PPCDispSPE8Operand : AsmOperandClass { 679 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8"; 680 let RenderMethod = "addImmOperands"; 681} 682def dispSPE8 : Operand<iPTR> { 683 let ParserMatchClass = PPCDispSPE8Operand; 684} 685def PPCDispSPE4Operand : AsmOperandClass { 686 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4"; 687 let RenderMethod = "addImmOperands"; 688} 689def dispSPE4 : Operand<iPTR> { 690 let ParserMatchClass = PPCDispSPE4Operand; 691} 692def PPCDispSPE2Operand : AsmOperandClass { 693 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2"; 694 let RenderMethod = "addImmOperands"; 695} 696def dispSPE2 : Operand<iPTR> { 697 let ParserMatchClass = PPCDispSPE2Operand; 698} 699 700def memri : Operand<iPTR> { 701 let PrintMethod = "printMemRegImm"; 702 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 703 let EncoderMethod = "getMemRIEncoding"; 704 let DecoderMethod = "decodeMemRIOperands"; 705} 706def memrr : Operand<iPTR> { 707 let PrintMethod = "printMemRegReg"; 708 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg); 709} 710def memrix : Operand<iPTR> { // memri where the imm is 4-aligned. 711 let PrintMethod = "printMemRegImm"; 712 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 713 let EncoderMethod = "getMemRIXEncoding"; 714 let DecoderMethod = "decodeMemRIXOperands"; 715} 716def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27} 717 let PrintMethod = "printMemRegImm"; 718 let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); 719 let EncoderMethod = "getMemRIX16Encoding"; 720 let DecoderMethod = "decodeMemRIX16Operands"; 721} 722def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned. 723 let PrintMethod = "printMemRegImm"; 724 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); 725 let EncoderMethod = "getSPE8DisEncoding"; 726} 727def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned. 728 let PrintMethod = "printMemRegImm"; 729 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); 730 let EncoderMethod = "getSPE4DisEncoding"; 731} 732def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned. 733 let PrintMethod = "printMemRegImm"; 734 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); 735 let EncoderMethod = "getSPE2DisEncoding"; 736} 737 738// A single-register address. This is used with the SjLj 739// pseudo-instructions. 740def memr : Operand<iPTR> { 741 let MIOperandInfo = (ops ptr_rc:$ptrreg); 742} 743def PPCTLSRegOperand : AsmOperandClass { 744 let Name = "TLSReg"; let PredicateMethod = "isTLSReg"; 745 let RenderMethod = "addTLSRegOperands"; 746} 747def tlsreg32 : Operand<i32> { 748 let EncoderMethod = "getTLSRegEncoding"; 749 let ParserMatchClass = PPCTLSRegOperand; 750} 751def tlsgd32 : Operand<i32> {} 752def tlscall32 : Operand<i32> { 753 let PrintMethod = "printTLSCall"; 754 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym); 755 let EncoderMethod = "getTLSCallEncoding"; 756} 757 758// PowerPC Predicate operand. 759def pred : Operand<OtherVT> { 760 let PrintMethod = "printPredicateOperand"; 761 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg); 762} 763 764// Define PowerPC specific addressing mode. 765def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 766def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 767def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 768def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" 769 770// The address in a single register. This is used with the SjLj 771// pseudo-instructions. 772def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 773 774/// This is just the offset part of iaddr, used for preinc. 775def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 776 777//===----------------------------------------------------------------------===// 778// PowerPC Instruction Predicate Definitions. 779def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">; 780def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">; 781def IsBookE : Predicate<"PPCSubTarget->isBookE()">; 782def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">; 783def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">; 784def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">; 785def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">; 786def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">; 787def IsE500 : Predicate<"PPCSubTarget->isE500()">; 788def HasSPE : Predicate<"PPCSubTarget->HasSPE()">; 789def HasICBT : Predicate<"PPCSubTarget->hasICBT()">; 790def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">; 791def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; 792def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">; 793def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">; 794def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">; 795def IsISA3_0 : Predicate<"PPCSubTarget->isISA3_0()">; 796 797//===----------------------------------------------------------------------===// 798// PowerPC Multiclass Definitions. 799 800multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 801 string asmbase, string asmstr, InstrItinClass itin, 802 list<dag> pattern> { 803 let BaseName = asmbase in { 804 def NAME : XForm_6<opcode, xo, OOL, IOL, 805 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 806 pattern>, RecFormRel; 807 let Defs = [CR0] in 808 def o : XForm_6<opcode, xo, OOL, IOL, 809 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 810 []>, isDOT, RecFormRel; 811 } 812} 813 814multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 815 string asmbase, string asmstr, InstrItinClass itin, 816 list<dag> pattern> { 817 let BaseName = asmbase in { 818 let Defs = [CARRY] in 819 def NAME : XForm_6<opcode, xo, OOL, IOL, 820 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 821 pattern>, RecFormRel; 822 let Defs = [CARRY, CR0] in 823 def o : XForm_6<opcode, xo, OOL, IOL, 824 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 825 []>, isDOT, RecFormRel; 826 } 827} 828 829multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 830 string asmbase, string asmstr, InstrItinClass itin, 831 list<dag> pattern> { 832 let BaseName = asmbase in { 833 let Defs = [CARRY] in 834 def NAME : XForm_10<opcode, xo, OOL, IOL, 835 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 836 pattern>, RecFormRel; 837 let Defs = [CARRY, CR0] in 838 def o : XForm_10<opcode, xo, OOL, IOL, 839 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 840 []>, isDOT, RecFormRel; 841 } 842} 843 844multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 845 string asmbase, string asmstr, InstrItinClass itin, 846 list<dag> pattern> { 847 let BaseName = asmbase in { 848 def NAME : XForm_11<opcode, xo, OOL, IOL, 849 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 850 pattern>, RecFormRel; 851 let Defs = [CR0] in 852 def o : XForm_11<opcode, xo, OOL, IOL, 853 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 854 []>, isDOT, RecFormRel; 855 } 856} 857 858multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 859 string asmbase, string asmstr, InstrItinClass itin, 860 list<dag> pattern> { 861 let BaseName = asmbase in { 862 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 863 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 864 pattern>, RecFormRel; 865 let Defs = [CR0] in 866 def o : XOForm_1<opcode, xo, oe, OOL, IOL, 867 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 868 []>, isDOT, RecFormRel; 869 } 870} 871 872// Multiclass for instructions for which the non record form is not cracked 873// and the record form is cracked (i.e. divw, mullw, etc.) 874multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 875 string asmbase, string asmstr, InstrItinClass itin, 876 list<dag> pattern> { 877 let BaseName = asmbase in { 878 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 879 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 880 pattern>, RecFormRel; 881 let Defs = [CR0] in 882 def o : XOForm_1<opcode, xo, oe, OOL, IOL, 883 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 884 []>, isDOT, RecFormRel, PPC970_DGroup_First, 885 PPC970_DGroup_Cracked; 886 } 887} 888 889multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 890 string asmbase, string asmstr, InstrItinClass itin, 891 list<dag> pattern> { 892 let BaseName = asmbase in { 893 let Defs = [CARRY] in 894 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 895 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 896 pattern>, RecFormRel; 897 let Defs = [CARRY, CR0] in 898 def o : XOForm_1<opcode, xo, oe, OOL, IOL, 899 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 900 []>, isDOT, RecFormRel; 901 } 902} 903 904multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 905 string asmbase, string asmstr, InstrItinClass itin, 906 list<dag> pattern> { 907 let BaseName = asmbase in { 908 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 909 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 910 pattern>, RecFormRel; 911 let Defs = [CR0] in 912 def o : XOForm_3<opcode, xo, oe, OOL, IOL, 913 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 914 []>, isDOT, RecFormRel; 915 } 916} 917 918multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 919 string asmbase, string asmstr, InstrItinClass itin, 920 list<dag> pattern> { 921 let BaseName = asmbase in { 922 let Defs = [CARRY] in 923 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 924 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 925 pattern>, RecFormRel; 926 let Defs = [CARRY, CR0] in 927 def o : XOForm_3<opcode, xo, oe, OOL, IOL, 928 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 929 []>, isDOT, RecFormRel; 930 } 931} 932 933multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 934 string asmbase, string asmstr, InstrItinClass itin, 935 list<dag> pattern> { 936 let BaseName = asmbase in { 937 def NAME : MForm_2<opcode, OOL, IOL, 938 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 939 pattern>, RecFormRel; 940 let Defs = [CR0] in 941 def o : MForm_2<opcode, OOL, IOL, 942 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 943 []>, isDOT, RecFormRel; 944 } 945} 946 947multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 948 string asmbase, string asmstr, InstrItinClass itin, 949 list<dag> pattern> { 950 let BaseName = asmbase in { 951 def NAME : MDForm_1<opcode, xo, OOL, IOL, 952 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 953 pattern>, RecFormRel; 954 let Defs = [CR0] in 955 def o : MDForm_1<opcode, xo, OOL, IOL, 956 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 957 []>, isDOT, RecFormRel; 958 } 959} 960 961multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 962 string asmbase, string asmstr, InstrItinClass itin, 963 list<dag> pattern> { 964 let BaseName = asmbase in { 965 def NAME : MDSForm_1<opcode, xo, OOL, IOL, 966 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 967 pattern>, RecFormRel; 968 let Defs = [CR0] in 969 def o : MDSForm_1<opcode, xo, OOL, IOL, 970 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 971 []>, isDOT, RecFormRel; 972 } 973} 974 975multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 976 string asmbase, string asmstr, InstrItinClass itin, 977 list<dag> pattern> { 978 let BaseName = asmbase in { 979 let Defs = [CARRY] in 980 def NAME : XSForm_1<opcode, xo, OOL, IOL, 981 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 982 pattern>, RecFormRel; 983 let Defs = [CARRY, CR0] in 984 def o : XSForm_1<opcode, xo, OOL, IOL, 985 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 986 []>, isDOT, RecFormRel; 987 } 988} 989 990multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 991 string asmbase, string asmstr, InstrItinClass itin, 992 list<dag> pattern> { 993 let BaseName = asmbase in { 994 def NAME : XForm_26<opcode, xo, OOL, IOL, 995 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 996 pattern>, RecFormRel; 997 let Defs = [CR1] in 998 def o : XForm_26<opcode, xo, OOL, IOL, 999 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1000 []>, isDOT, RecFormRel; 1001 } 1002} 1003 1004multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1005 string asmbase, string asmstr, InstrItinClass itin, 1006 list<dag> pattern> { 1007 let BaseName = asmbase in { 1008 def NAME : XForm_28<opcode, xo, OOL, IOL, 1009 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1010 pattern>, RecFormRel; 1011 let Defs = [CR1] in 1012 def o : XForm_28<opcode, xo, OOL, IOL, 1013 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1014 []>, isDOT, RecFormRel; 1015 } 1016} 1017 1018multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1019 string asmbase, string asmstr, InstrItinClass itin, 1020 list<dag> pattern> { 1021 let BaseName = asmbase in { 1022 def NAME : AForm_1<opcode, xo, OOL, IOL, 1023 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1024 pattern>, RecFormRel; 1025 let Defs = [CR1] in 1026 def o : AForm_1<opcode, xo, OOL, IOL, 1027 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1028 []>, isDOT, RecFormRel; 1029 } 1030} 1031 1032multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1033 string asmbase, string asmstr, InstrItinClass itin, 1034 list<dag> pattern> { 1035 let BaseName = asmbase in { 1036 def NAME : AForm_2<opcode, xo, OOL, IOL, 1037 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1038 pattern>, RecFormRel; 1039 let Defs = [CR1] in 1040 def o : AForm_2<opcode, xo, OOL, IOL, 1041 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1042 []>, isDOT, RecFormRel; 1043 } 1044} 1045 1046multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1047 string asmbase, string asmstr, InstrItinClass itin, 1048 list<dag> pattern> { 1049 let BaseName = asmbase in { 1050 def NAME : AForm_3<opcode, xo, OOL, IOL, 1051 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1052 pattern>, RecFormRel; 1053 let Defs = [CR1] in 1054 def o : AForm_3<opcode, xo, OOL, IOL, 1055 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1056 []>, isDOT, RecFormRel; 1057 } 1058} 1059 1060//===----------------------------------------------------------------------===// 1061// PowerPC Instruction Definitions. 1062 1063// Pseudo-instructions: 1064 1065let hasCtrlDep = 1 in { 1066let Defs = [R1], Uses = [R1] in { 1067def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt", 1068 [(callseq_start timm:$amt)]>; 1069def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2", 1070 [(callseq_end timm:$amt1, timm:$amt2)]>; 1071} 1072 1073def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS), 1074 "UPDATE_VRSAVE $rD, $rS", []>; 1075} 1076 1077let Defs = [R1], Uses = [R1] in 1078def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", 1079 [(set i32:$result, 1080 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 1081def DYNAREAOFFSET : Pseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET", 1082 [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 1083 1084// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 1085// instruction selection into a branch sequence. 1086let usesCustomInserter = 1, // Expanded after instruction selection. 1087 PPC970_Single = 1 in { 1088 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 1089 // because either operand might become the first operand in an isel, and 1090 // that operand cannot be r0. 1091 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond, 1092 gprc_nor0:$T, gprc_nor0:$F, 1093 i32imm:$BROPC), "#SELECT_CC_I4", 1094 []>; 1095 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond, 1096 g8rc_nox0:$T, g8rc_nox0:$F, 1097 i32imm:$BROPC), "#SELECT_CC_I8", 1098 []>; 1099 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, 1100 i32imm:$BROPC), "#SELECT_CC_F4", 1101 []>; 1102 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, 1103 i32imm:$BROPC), "#SELECT_CC_F8", 1104 []>; 1105 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1106 i32imm:$BROPC), "#SELECT_CC_VRRC", 1107 []>; 1108 1109 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition 1110 // register bit directly. 1111 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond, 1112 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", 1113 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; 1114 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond, 1115 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", 1116 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; 1117 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond, 1118 f4rc:$T, f4rc:$F), "#SELECT_F4", 1119 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; 1120 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond, 1121 f8rc:$T, f8rc:$F), "#SELECT_F8", 1122 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; 1123 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1124 vrrc:$T, vrrc:$F), "#SELECT_VRRC", 1125 [(set v4i32:$dst, 1126 (select i1:$cond, v4i32:$T, v4i32:$F))]>; 1127} 1128 1129// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 1130// scavenge a register for it. 1131let mayStore = 1 in { 1132def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F), 1133 "#SPILL_CR", []>; 1134def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F), 1135 "#SPILL_CRBIT", []>; 1136} 1137 1138// RESTORE_CR - Indicate that we're restoring the CR register (previously 1139// spilled), so we'll need to scavenge a register for it. 1140let mayLoad = 1 in { 1141def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F), 1142 "#RESTORE_CR", []>; 1143def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F), 1144 "#RESTORE_CRBIT", []>; 1145} 1146 1147let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 1148 let isReturn = 1, Uses = [LR, RM] in 1149 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 1150 [(retflag)]>, Requires<[In32BitMode]>; 1151 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 1152 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1153 []>; 1154 1155 let isCodeGenOnly = 1 in { 1156 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 1157 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 1158 []>; 1159 1160 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 1161 "bcctr 12, $bi, 0", IIC_BrB, []>; 1162 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 1163 "bcctr 4, $bi, 0", IIC_BrB, []>; 1164 } 1165 } 1166} 1167 1168let Defs = [LR] in 1169 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>, 1170 PPC970_Unit_BRU; 1171let Defs = [LR] in 1172 def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>, 1173 PPC970_Unit_BRU; 1174 1175let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 1176 let isBarrier = 1 in { 1177 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 1178 "b $dst", IIC_BrB, 1179 [(br bb:$dst)]>; 1180 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst), 1181 "ba $dst", IIC_BrB, []>; 1182 } 1183 1184 // BCC represents an arbitrary conditional branch on a predicate. 1185 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 1186 // a two-value operand where a dag node expects two operands. :( 1187 let isCodeGenOnly = 1 in { 1188 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 1189 "b${cond:cc}${cond:pm} ${cond:reg}, $dst" 1190 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>; 1191 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1192 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">; 1193 1194 let isReturn = 1, Uses = [LR, RM] in 1195 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond), 1196 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; 1197 } 1198 1199 let isCodeGenOnly = 1 in { 1200 let Pattern = [(brcond i1:$bi, bb:$dst)] in 1201 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1202 "bc 12, $bi, $dst">; 1203 1204 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in 1205 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1206 "bc 4, $bi, $dst">; 1207 1208 let isReturn = 1, Uses = [LR, RM] in 1209 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi), 1210 "bclr 12, $bi, 0", IIC_BrB, []>; 1211 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi), 1212 "bclr 4, $bi, 0", IIC_BrB, []>; 1213 } 1214 1215 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 1216 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 1217 "bdzlr", IIC_BrB, []>; 1218 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 1219 "bdnzlr", IIC_BrB, []>; 1220 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), 1221 "bdzlr+", IIC_BrB, []>; 1222 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), 1223 "bdnzlr+", IIC_BrB, []>; 1224 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), 1225 "bdzlr-", IIC_BrB, []>; 1226 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), 1227 "bdnzlr-", IIC_BrB, []>; 1228 } 1229 1230 let Defs = [CTR], Uses = [CTR] in { 1231 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 1232 "bdz $dst">; 1233 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 1234 "bdnz $dst">; 1235 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst), 1236 "bdza $dst">; 1237 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst), 1238 "bdnza $dst">; 1239 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst), 1240 "bdz+ $dst">; 1241 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst), 1242 "bdnz+ $dst">; 1243 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst), 1244 "bdza+ $dst">; 1245 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst), 1246 "bdnza+ $dst">; 1247 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst), 1248 "bdz- $dst">; 1249 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst), 1250 "bdnz- $dst">; 1251 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst), 1252 "bdza- $dst">; 1253 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst), 1254 "bdnza- $dst">; 1255 } 1256} 1257 1258// The unconditional BCL used by the SjLj setjmp code. 1259let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in { 1260 let Defs = [LR], Uses = [RM] in { 1261 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst), 1262 "bcl 20, 31, $dst">; 1263 } 1264} 1265 1266let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 1267 // Convenient aliases for call instructions 1268 let Uses = [RM] in { 1269 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func), 1270 "bl $func", IIC_BrB, []>; // See Pat patterns below. 1271 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 1272 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>; 1273 1274 let isCodeGenOnly = 1 in { 1275 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func), 1276 "bl $func", IIC_BrB, []>; 1277 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst), 1278 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">; 1279 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1280 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">; 1281 1282 def BCL : BForm_4<16, 12, 0, 1, (outs), 1283 (ins crbitrc:$bi, condbrtarget:$dst), 1284 "bcl 12, $bi, $dst">; 1285 def BCLn : BForm_4<16, 4, 0, 1, (outs), 1286 (ins crbitrc:$bi, condbrtarget:$dst), 1287 "bcl 4, $bi, $dst">; 1288 } 1289 } 1290 let Uses = [CTR, RM] in { 1291 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1292 "bctrl", IIC_BrB, [(PPCbctrl)]>, 1293 Requires<[In32BitMode]>; 1294 1295 let isCodeGenOnly = 1 in { 1296 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 1297 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 1298 []>; 1299 1300 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 1301 "bcctrl 12, $bi, 0", IIC_BrB, []>; 1302 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 1303 "bcctrl 4, $bi, 0", IIC_BrB, []>; 1304 } 1305 } 1306 let Uses = [LR, RM] in { 1307 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), 1308 "blrl", IIC_BrB, []>; 1309 1310 let isCodeGenOnly = 1 in { 1311 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond), 1312 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, 1313 []>; 1314 1315 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi), 1316 "bclrl 12, $bi, 0", IIC_BrB, []>; 1317 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi), 1318 "bclrl 4, $bi, 0", IIC_BrB, []>; 1319 } 1320 } 1321 let Defs = [CTR], Uses = [CTR, RM] in { 1322 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst), 1323 "bdzl $dst">; 1324 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst), 1325 "bdnzl $dst">; 1326 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst), 1327 "bdzla $dst">; 1328 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst), 1329 "bdnzla $dst">; 1330 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst), 1331 "bdzl+ $dst">; 1332 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst), 1333 "bdnzl+ $dst">; 1334 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst), 1335 "bdzla+ $dst">; 1336 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst), 1337 "bdnzla+ $dst">; 1338 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst), 1339 "bdzl- $dst">; 1340 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst), 1341 "bdnzl- $dst">; 1342 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst), 1343 "bdzla- $dst">; 1344 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst), 1345 "bdnzla- $dst">; 1346 } 1347 let Defs = [CTR], Uses = [CTR, LR, RM] in { 1348 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), 1349 "bdzlrl", IIC_BrB, []>; 1350 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), 1351 "bdnzlrl", IIC_BrB, []>; 1352 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), 1353 "bdzlrl+", IIC_BrB, []>; 1354 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), 1355 "bdnzlrl+", IIC_BrB, []>; 1356 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), 1357 "bdzlrl-", IIC_BrB, []>; 1358 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), 1359 "bdnzlrl-", IIC_BrB, []>; 1360 } 1361} 1362 1363let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1364def TCRETURNdi :Pseudo< (outs), 1365 (ins calltarget:$dst, i32imm:$offset), 1366 "#TC_RETURNd $dst $offset", 1367 []>; 1368 1369 1370let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1371def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 1372 "#TC_RETURNa $func $offset", 1373 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 1374 1375let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1376def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 1377 "#TC_RETURNr $dst $offset", 1378 []>; 1379 1380 1381let isCodeGenOnly = 1 in { 1382 1383let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 1384 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 1385def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1386 []>, Requires<[In32BitMode]>; 1387 1388let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1389 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1390def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 1391 "b $dst", IIC_BrB, 1392 []>; 1393 1394let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1395 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1396def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 1397 "ba $dst", IIC_BrB, 1398 []>; 1399 1400} 1401 1402let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 1403 let Defs = [CTR] in 1404 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 1405 "#EH_SJLJ_SETJMP32", 1406 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 1407 Requires<[In32BitMode]>; 1408 let isTerminator = 1 in 1409 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf), 1410 "#EH_SJLJ_LONGJMP32", 1411 [(PPCeh_sjlj_longjmp addr:$buf)]>, 1412 Requires<[In32BitMode]>; 1413} 1414 1415// This pseudo is never removed from the function, as it serves as 1416// a terminator. Size is set to 0 to prevent the builtin assembler 1417// from emitting it. 1418let isBranch = 1, isTerminator = 1, Size = 0 in { 1419 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst), 1420 "#EH_SjLj_Setup\t$dst", []>; 1421} 1422 1423// System call. 1424let PPC970_Unit = 7 in { 1425 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev), 1426 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>; 1427} 1428 1429// Branch history rolling buffer. 1430def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, 1431 [(PPCclrbhrb)]>, 1432 PPC970_DGroup_Single; 1433// The $dmy argument used for MFBHRBE is not needed; however, including 1434// it avoids automatic generation of PPCFastISel::fastEmit_i(), which 1435// interferes with necessary special handling (see PPCFastISel.cpp). 1436def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD), 1437 (ins u10imm:$imm, u10imm:$dmy), 1438 "mfbhrbe $rD, $imm", IIC_BrB, 1439 [(set i32:$rD, 1440 (PPCmfbhrbe imm:$imm, imm:$dmy))]>, 1441 PPC970_DGroup_First; 1442 1443def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm", 1444 IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>, 1445 PPC970_DGroup_Single; 1446 1447// DCB* instructions. 1448def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst", 1449 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 1450 PPC970_DGroup_Single; 1451def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst", 1452 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 1453 PPC970_DGroup_Single; 1454def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst", 1455 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 1456 PPC970_DGroup_Single; 1457def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst", 1458 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 1459 PPC970_DGroup_Single; 1460def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst", 1461 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 1462 PPC970_DGroup_Single; 1463def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", 1464 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 1465 PPC970_DGroup_Single; 1466 1467let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { 1468def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst), 1469 "dcbt $dst, $TH", IIC_LdStDCBF, []>, 1470 PPC970_DGroup_Single; 1471def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst), 1472 "dcbtst $dst, $TH", IIC_LdStDCBF, []>, 1473 PPC970_DGroup_Single; 1474} // hasSideEffects = 0 1475 1476def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src), 1477 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 1478 1479def : Pat<(int_ppc_dcbt xoaddr:$dst), 1480 (DCBT 0, xoaddr:$dst)>; 1481def : Pat<(int_ppc_dcbtst xoaddr:$dst), 1482 (DCBTST 0, xoaddr:$dst)>; 1483 1484def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), 1485 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads 1486def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)), 1487 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores 1488def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)), 1489 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read) 1490 1491// Atomic operations 1492let usesCustomInserter = 1 in { 1493 let Defs = [CR0] in { 1494 def ATOMIC_LOAD_ADD_I8 : Pseudo< 1495 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", 1496 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>; 1497 def ATOMIC_LOAD_SUB_I8 : Pseudo< 1498 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", 1499 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>; 1500 def ATOMIC_LOAD_AND_I8 : Pseudo< 1501 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", 1502 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>; 1503 def ATOMIC_LOAD_OR_I8 : Pseudo< 1504 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", 1505 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>; 1506 def ATOMIC_LOAD_XOR_I8 : Pseudo< 1507 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", 1508 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>; 1509 def ATOMIC_LOAD_NAND_I8 : Pseudo< 1510 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", 1511 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>; 1512 def ATOMIC_LOAD_ADD_I16 : Pseudo< 1513 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", 1514 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>; 1515 def ATOMIC_LOAD_SUB_I16 : Pseudo< 1516 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", 1517 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>; 1518 def ATOMIC_LOAD_AND_I16 : Pseudo< 1519 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", 1520 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>; 1521 def ATOMIC_LOAD_OR_I16 : Pseudo< 1522 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", 1523 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>; 1524 def ATOMIC_LOAD_XOR_I16 : Pseudo< 1525 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", 1526 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>; 1527 def ATOMIC_LOAD_NAND_I16 : Pseudo< 1528 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", 1529 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>; 1530 def ATOMIC_LOAD_ADD_I32 : Pseudo< 1531 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", 1532 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>; 1533 def ATOMIC_LOAD_SUB_I32 : Pseudo< 1534 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", 1535 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>; 1536 def ATOMIC_LOAD_AND_I32 : Pseudo< 1537 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", 1538 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>; 1539 def ATOMIC_LOAD_OR_I32 : Pseudo< 1540 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", 1541 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>; 1542 def ATOMIC_LOAD_XOR_I32 : Pseudo< 1543 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", 1544 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>; 1545 def ATOMIC_LOAD_NAND_I32 : Pseudo< 1546 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", 1547 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>; 1548 1549 def ATOMIC_CMP_SWAP_I8 : Pseudo< 1550 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", 1551 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>; 1552 def ATOMIC_CMP_SWAP_I16 : Pseudo< 1553 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 1554 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>; 1555 def ATOMIC_CMP_SWAP_I32 : Pseudo< 1556 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 1557 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>; 1558 1559 def ATOMIC_SWAP_I8 : Pseudo< 1560 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", 1561 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>; 1562 def ATOMIC_SWAP_I16 : Pseudo< 1563 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", 1564 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>; 1565 def ATOMIC_SWAP_I32 : Pseudo< 1566 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", 1567 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>; 1568 } 1569} 1570 1571// Instructions to support atomic operations 1572let mayLoad = 1, hasSideEffects = 0 in { 1573def LBARX : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src), 1574 "lbarx $rD, $src", IIC_LdStLWARX, []>, 1575 Requires<[HasPartwordAtomics]>; 1576 1577def LHARX : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src), 1578 "lharx $rD, $src", IIC_LdStLWARX, []>, 1579 Requires<[HasPartwordAtomics]>; 1580 1581def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src), 1582 "lwarx $rD, $src", IIC_LdStLWARX, []>; 1583 1584// Instructions to support lock versions of atomics 1585// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 1586def LBARXL : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src), 1587 "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT, 1588 Requires<[HasPartwordAtomics]>; 1589 1590def LHARXL : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src), 1591 "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT, 1592 Requires<[HasPartwordAtomics]>; 1593 1594def LWARXL : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src), 1595 "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT; 1596 1597// The atomic instructions use the destination register as well as the next one 1598// or two registers in order (modulo 31). 1599let hasExtraSrcRegAllocReq = 1 in 1600def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC), 1601 "lwat $rD, $rA, $FC", IIC_LdStLoad>, 1602 Requires<[IsISA3_0]>; 1603} 1604 1605let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in { 1606def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS, memrr:$dst), 1607 "stbcx. $rS, $dst", IIC_LdStSTWCX, []>, 1608 isDOT, Requires<[HasPartwordAtomics]>; 1609 1610def STHCX : XForm_1<31, 726, (outs), (ins gprc:$rS, memrr:$dst), 1611 "sthcx. $rS, $dst", IIC_LdStSTWCX, []>, 1612 isDOT, Requires<[HasPartwordAtomics]>; 1613 1614def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst), 1615 "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT; 1616} 1617 1618let mayStore = 1, hasSideEffects = 0 in 1619def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC), 1620 "stwat $rS, $rA, $FC", IIC_LdStStore>, 1621 Requires<[IsISA3_0]>; 1622 1623let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 1624def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; 1625 1626def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm), 1627 "twi $to, $rA, $imm", IIC_IntTrapW, []>; 1628def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB), 1629 "tw $to, $rA, $rB", IIC_IntTrapW, []>; 1630def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm), 1631 "tdi $to, $rA, $imm", IIC_IntTrapD, []>; 1632def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB), 1633 "td $to, $rA, $rB", IIC_IntTrapD, []>; 1634 1635//===----------------------------------------------------------------------===// 1636// PPC32 Load Instructions. 1637// 1638 1639// Unindexed (r+i) Loads. 1640let PPC970_Unit = 2 in { 1641def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src), 1642 "lbz $rD, $src", IIC_LdStLoad, 1643 [(set i32:$rD, (zextloadi8 iaddr:$src))]>; 1644def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src), 1645 "lha $rD, $src", IIC_LdStLHA, 1646 [(set i32:$rD, (sextloadi16 iaddr:$src))]>, 1647 PPC970_DGroup_Cracked; 1648def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src), 1649 "lhz $rD, $src", IIC_LdStLoad, 1650 [(set i32:$rD, (zextloadi16 iaddr:$src))]>; 1651def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src), 1652 "lwz $rD, $src", IIC_LdStLoad, 1653 [(set i32:$rD, (load iaddr:$src))]>; 1654 1655def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src), 1656 "lfs $rD, $src", IIC_LdStLFD, 1657 [(set f32:$rD, (load iaddr:$src))]>; 1658def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src), 1659 "lfd $rD, $src", IIC_LdStLFD, 1660 [(set f64:$rD, (load iaddr:$src))]>; 1661 1662 1663// Unindexed (r+i) Loads with Update (preinc). 1664let mayLoad = 1, hasSideEffects = 0 in { 1665def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1666 "lbzu $rD, $addr", IIC_LdStLoadUpd, 1667 []>, RegConstraint<"$addr.reg = $ea_result">, 1668 NoEncode<"$ea_result">; 1669 1670def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1671 "lhau $rD, $addr", IIC_LdStLHAU, 1672 []>, RegConstraint<"$addr.reg = $ea_result">, 1673 NoEncode<"$ea_result">; 1674 1675def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1676 "lhzu $rD, $addr", IIC_LdStLoadUpd, 1677 []>, RegConstraint<"$addr.reg = $ea_result">, 1678 NoEncode<"$ea_result">; 1679 1680def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1681 "lwzu $rD, $addr", IIC_LdStLoadUpd, 1682 []>, RegConstraint<"$addr.reg = $ea_result">, 1683 NoEncode<"$ea_result">; 1684 1685def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1686 "lfsu $rD, $addr", IIC_LdStLFDU, 1687 []>, RegConstraint<"$addr.reg = $ea_result">, 1688 NoEncode<"$ea_result">; 1689 1690def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1691 "lfdu $rD, $addr", IIC_LdStLFDU, 1692 []>, RegConstraint<"$addr.reg = $ea_result">, 1693 NoEncode<"$ea_result">; 1694 1695 1696// Indexed (r+r) Loads with Update (preinc). 1697def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1698 (ins memrr:$addr), 1699 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 1700 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1701 NoEncode<"$ea_result">; 1702 1703def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1704 (ins memrr:$addr), 1705 "lhaux $rD, $addr", IIC_LdStLHAUX, 1706 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1707 NoEncode<"$ea_result">; 1708 1709def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1710 (ins memrr:$addr), 1711 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 1712 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1713 NoEncode<"$ea_result">; 1714 1715def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1716 (ins memrr:$addr), 1717 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 1718 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1719 NoEncode<"$ea_result">; 1720 1721def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), 1722 (ins memrr:$addr), 1723 "lfsux $rD, $addr", IIC_LdStLFDUX, 1724 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1725 NoEncode<"$ea_result">; 1726 1727def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), 1728 (ins memrr:$addr), 1729 "lfdux $rD, $addr", IIC_LdStLFDUX, 1730 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1731 NoEncode<"$ea_result">; 1732} 1733} 1734 1735// Indexed (r+r) Loads. 1736// 1737let PPC970_Unit = 2 in { 1738def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src), 1739 "lbzx $rD, $src", IIC_LdStLoad, 1740 [(set i32:$rD, (zextloadi8 xaddr:$src))]>; 1741def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src), 1742 "lhax $rD, $src", IIC_LdStLHA, 1743 [(set i32:$rD, (sextloadi16 xaddr:$src))]>, 1744 PPC970_DGroup_Cracked; 1745def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src), 1746 "lhzx $rD, $src", IIC_LdStLoad, 1747 [(set i32:$rD, (zextloadi16 xaddr:$src))]>; 1748def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src), 1749 "lwzx $rD, $src", IIC_LdStLoad, 1750 [(set i32:$rD, (load xaddr:$src))]>; 1751 1752 1753def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src), 1754 "lhbrx $rD, $src", IIC_LdStLoad, 1755 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>; 1756def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src), 1757 "lwbrx $rD, $src", IIC_LdStLoad, 1758 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>; 1759 1760def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src), 1761 "lfsx $frD, $src", IIC_LdStLFD, 1762 [(set f32:$frD, (load xaddr:$src))]>; 1763def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src), 1764 "lfdx $frD, $src", IIC_LdStLFD, 1765 [(set f64:$frD, (load xaddr:$src))]>; 1766 1767def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src), 1768 "lfiwax $frD, $src", IIC_LdStLFD, 1769 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>; 1770def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src), 1771 "lfiwzx $frD, $src", IIC_LdStLFD, 1772 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>; 1773} 1774 1775// Load Multiple 1776def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src), 1777 "lmw $rD, $src", IIC_LdStLMW, []>; 1778 1779//===----------------------------------------------------------------------===// 1780// PPC32 Store Instructions. 1781// 1782 1783// Unindexed (r+i) Stores. 1784let PPC970_Unit = 2 in { 1785def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src), 1786 "stb $rS, $src", IIC_LdStStore, 1787 [(truncstorei8 i32:$rS, iaddr:$src)]>; 1788def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src), 1789 "sth $rS, $src", IIC_LdStStore, 1790 [(truncstorei16 i32:$rS, iaddr:$src)]>; 1791def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src), 1792 "stw $rS, $src", IIC_LdStStore, 1793 [(store i32:$rS, iaddr:$src)]>; 1794def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst), 1795 "stfs $rS, $dst", IIC_LdStSTFD, 1796 [(store f32:$rS, iaddr:$dst)]>; 1797def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst), 1798 "stfd $rS, $dst", IIC_LdStSTFD, 1799 [(store f64:$rS, iaddr:$dst)]>; 1800} 1801 1802// Unindexed (r+i) Stores with Update (preinc). 1803let PPC970_Unit = 2, mayStore = 1 in { 1804def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1805 "stbu $rS, $dst", IIC_LdStStoreUpd, []>, 1806 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1807def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1808 "sthu $rS, $dst", IIC_LdStStoreUpd, []>, 1809 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1810def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1811 "stwu $rS, $dst", IIC_LdStStoreUpd, []>, 1812 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1813def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst), 1814 "stfsu $rS, $dst", IIC_LdStSTFDU, []>, 1815 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1816def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst), 1817 "stfdu $rS, $dst", IIC_LdStSTFDU, []>, 1818 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1819} 1820 1821// Patterns to match the pre-inc stores. We can't put the patterns on 1822// the instruction definitions directly as ISel wants the address base 1823// and offset to be separate operands, not a single complex operand. 1824def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1825 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 1826def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1827 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 1828def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1829 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 1830def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1831 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 1832def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1833 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 1834 1835// Indexed (r+r) Stores. 1836let PPC970_Unit = 2 in { 1837def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst), 1838 "stbx $rS, $dst", IIC_LdStStore, 1839 [(truncstorei8 i32:$rS, xaddr:$dst)]>, 1840 PPC970_DGroup_Cracked; 1841def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst), 1842 "sthx $rS, $dst", IIC_LdStStore, 1843 [(truncstorei16 i32:$rS, xaddr:$dst)]>, 1844 PPC970_DGroup_Cracked; 1845def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst), 1846 "stwx $rS, $dst", IIC_LdStStore, 1847 [(store i32:$rS, xaddr:$dst)]>, 1848 PPC970_DGroup_Cracked; 1849 1850def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst), 1851 "sthbrx $rS, $dst", IIC_LdStStore, 1852 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>, 1853 PPC970_DGroup_Cracked; 1854def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst), 1855 "stwbrx $rS, $dst", IIC_LdStStore, 1856 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>, 1857 PPC970_DGroup_Cracked; 1858 1859def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst), 1860 "stfiwx $frS, $dst", IIC_LdStSTFD, 1861 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>; 1862 1863def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst), 1864 "stfsx $frS, $dst", IIC_LdStSTFD, 1865 [(store f32:$frS, xaddr:$dst)]>; 1866def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst), 1867 "stfdx $frS, $dst", IIC_LdStSTFD, 1868 [(store f64:$frS, xaddr:$dst)]>; 1869} 1870 1871// Indexed (r+r) Stores with Update (preinc). 1872let PPC970_Unit = 2, mayStore = 1 in { 1873def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst), 1874 "stbux $rS, $dst", IIC_LdStStoreUpd, []>, 1875 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1876 PPC970_DGroup_Cracked; 1877def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst), 1878 "sthux $rS, $dst", IIC_LdStStoreUpd, []>, 1879 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1880 PPC970_DGroup_Cracked; 1881def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst), 1882 "stwux $rS, $dst", IIC_LdStStoreUpd, []>, 1883 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1884 PPC970_DGroup_Cracked; 1885def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst), 1886 "stfsux $rS, $dst", IIC_LdStSTFDU, []>, 1887 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1888 PPC970_DGroup_Cracked; 1889def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst), 1890 "stfdux $rS, $dst", IIC_LdStSTFDU, []>, 1891 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1892 PPC970_DGroup_Cracked; 1893} 1894 1895// Patterns to match the pre-inc stores. We can't put the patterns on 1896// the instruction definitions directly as ISel wants the address base 1897// and offset to be separate operands, not a single complex operand. 1898def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1899 (STBUX $rS, $ptrreg, $ptroff)>; 1900def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1901 (STHUX $rS, $ptrreg, $ptroff)>; 1902def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1903 (STWUX $rS, $ptrreg, $ptroff)>; 1904def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1905 (STFSUX $rS, $ptrreg, $ptroff)>; 1906def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1907 (STFDUX $rS, $ptrreg, $ptroff)>; 1908 1909// Store Multiple 1910def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst), 1911 "stmw $rS, $dst", IIC_LdStLMW, []>; 1912 1913def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L), 1914 "sync $L", IIC_LdStSync, []>; 1915 1916let isCodeGenOnly = 1 in { 1917 def MSYNC : XForm_24_sync<31, 598, (outs), (ins), 1918 "msync", IIC_LdStSync, []> { 1919 let L = 0; 1920 } 1921} 1922 1923def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>; 1924def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 1925def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 1926def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 1927 1928//===----------------------------------------------------------------------===// 1929// PPC32 Arithmetic Instructions. 1930// 1931 1932let PPC970_Unit = 1 in { // FXU Operations. 1933def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm), 1934 "addi $rD, $rA, $imm", IIC_IntSimple, 1935 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>; 1936let BaseName = "addic" in { 1937let Defs = [CARRY] in 1938def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1939 "addic $rD, $rA, $imm", IIC_IntGeneral, 1940 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>, 1941 RecFormRel, PPC970_DGroup_Cracked; 1942let Defs = [CARRY, CR0] in 1943def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1944 "addic. $rD, $rA, $imm", IIC_IntGeneral, 1945 []>, isDOT, RecFormRel; 1946} 1947def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm), 1948 "addis $rD, $rA, $imm", IIC_IntSimple, 1949 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>; 1950let isCodeGenOnly = 1 in 1951def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym), 1952 "la $rD, $sym($rA)", IIC_IntGeneral, 1953 [(set i32:$rD, (add i32:$rA, 1954 (PPClo tglobaladdr:$sym, 0)))]>; 1955def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1956 "mulli $rD, $rA, $imm", IIC_IntMulLI, 1957 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>; 1958let Defs = [CARRY] in 1959def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1960 "subfic $rD, $rA, $imm", IIC_IntGeneral, 1961 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>; 1962 1963let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 1964 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm), 1965 "li $rD, $imm", IIC_IntSimple, 1966 [(set i32:$rD, imm32SExt16:$imm)]>; 1967 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm), 1968 "lis $rD, $imm", IIC_IntSimple, 1969 [(set i32:$rD, imm16ShiftedSExt:$imm)]>; 1970} 1971} 1972 1973let PPC970_Unit = 1 in { // FXU Operations. 1974let Defs = [CR0] in { 1975def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1976 "andi. $dst, $src1, $src2", IIC_IntGeneral, 1977 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>, 1978 isDOT; 1979def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1980 "andis. $dst, $src1, $src2", IIC_IntGeneral, 1981 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>, 1982 isDOT; 1983} 1984def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1985 "ori $dst, $src1, $src2", IIC_IntSimple, 1986 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>; 1987def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1988 "oris $dst, $src1, $src2", IIC_IntSimple, 1989 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>; 1990def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1991 "xori $dst, $src1, $src2", IIC_IntSimple, 1992 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>; 1993def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1994 "xoris $dst, $src1, $src2", IIC_IntSimple, 1995 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>; 1996 1997def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, 1998 []>; 1999let isCodeGenOnly = 1 in { 2000// The POWER6 and POWER7 have special group-terminating nops. 2001def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins), 2002 "ori 1, 1, 0", IIC_IntSimple, []>; 2003def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins), 2004 "ori 2, 2, 0", IIC_IntSimple, []>; 2005} 2006 2007let isCompare = 1, hasSideEffects = 0 in { 2008 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm), 2009 "cmpwi $crD, $rA, $imm", IIC_IntCompare>; 2010 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2), 2011 "cmplwi $dst, $src1, $src2", IIC_IntCompare>; 2012 def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crbitrc:$BF), 2013 (ins u1imm:$L, g8rc:$rA, g8rc:$rB), 2014 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 2015 Requires<[IsISA3_0]>; 2016} 2017} 2018 2019let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2020let isCommutable = 1 in { 2021defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2022 "nand", "$rA, $rS, $rB", IIC_IntSimple, 2023 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>; 2024defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2025 "and", "$rA, $rS, $rB", IIC_IntSimple, 2026 [(set i32:$rA, (and i32:$rS, i32:$rB))]>; 2027} // isCommutable 2028defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2029 "andc", "$rA, $rS, $rB", IIC_IntSimple, 2030 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>; 2031let isCommutable = 1 in { 2032defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2033 "or", "$rA, $rS, $rB", IIC_IntSimple, 2034 [(set i32:$rA, (or i32:$rS, i32:$rB))]>; 2035defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2036 "nor", "$rA, $rS, $rB", IIC_IntSimple, 2037 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>; 2038} // isCommutable 2039defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2040 "orc", "$rA, $rS, $rB", IIC_IntSimple, 2041 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>; 2042let isCommutable = 1 in { 2043defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2044 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 2045 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>; 2046defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2047 "xor", "$rA, $rS, $rB", IIC_IntSimple, 2048 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>; 2049} // isCommutable 2050defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2051 "slw", "$rA, $rS, $rB", IIC_IntGeneral, 2052 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>; 2053defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2054 "srw", "$rA, $rS, $rB", IIC_IntGeneral, 2055 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>; 2056defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2057 "sraw", "$rA, $rS, $rB", IIC_IntShift, 2058 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>; 2059} 2060 2061let PPC970_Unit = 1 in { // FXU Operations. 2062let hasSideEffects = 0 in { 2063defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH), 2064 "srawi", "$rA, $rS, $SH", IIC_IntShift, 2065 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>; 2066defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS), 2067 "cntlzw", "$rA, $rS", IIC_IntGeneral, 2068 [(set i32:$rA, (ctlz i32:$rS))]>; 2069defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS), 2070 "cnttzw", "$rA, $rS", IIC_IntGeneral, 2071 [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>; 2072defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS), 2073 "extsb", "$rA, $rS", IIC_IntSimple, 2074 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>; 2075defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS), 2076 "extsh", "$rA, $rS", IIC_IntSimple, 2077 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>; 2078 2079let isCommutable = 1 in 2080def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2081 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 2082 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>; 2083} 2084let isCompare = 1, hasSideEffects = 0 in { 2085 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2086 "cmpw $crD, $rA, $rB", IIC_IntCompare>; 2087 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2088 "cmplw $crD, $rA, $rB", IIC_IntCompare>; 2089} 2090} 2091let PPC970_Unit = 3 in { // FPU Operations. 2092//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 2093// "fcmpo $crD, $fA, $fB", IIC_FPCompare>; 2094let isCompare = 1, hasSideEffects = 0 in { 2095 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), 2096 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2097 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2098 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2099 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2100} 2101 2102let Uses = [RM] in { 2103 let hasSideEffects = 0 in { 2104 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB), 2105 "fctiw", "$frD, $frB", IIC_FPGeneral, 2106 []>; 2107 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB), 2108 "fctiwz", "$frD, $frB", IIC_FPGeneral, 2109 [(set f64:$frD, (PPCfctiwz f64:$frB))]>; 2110 2111 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB), 2112 "frsp", "$frD, $frB", IIC_FPGeneral, 2113 [(set f32:$frD, (fround f64:$frB))]>; 2114 2115 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2116 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB), 2117 "frin", "$frD, $frB", IIC_FPGeneral, 2118 [(set f64:$frD, (frnd f64:$frB))]>; 2119 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB), 2120 "frin", "$frD, $frB", IIC_FPGeneral, 2121 [(set f32:$frD, (frnd f32:$frB))]>; 2122 } 2123 2124 let hasSideEffects = 0 in { 2125 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2126 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB), 2127 "frip", "$frD, $frB", IIC_FPGeneral, 2128 [(set f64:$frD, (fceil f64:$frB))]>; 2129 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB), 2130 "frip", "$frD, $frB", IIC_FPGeneral, 2131 [(set f32:$frD, (fceil f32:$frB))]>; 2132 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2133 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB), 2134 "friz", "$frD, $frB", IIC_FPGeneral, 2135 [(set f64:$frD, (ftrunc f64:$frB))]>; 2136 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB), 2137 "friz", "$frD, $frB", IIC_FPGeneral, 2138 [(set f32:$frD, (ftrunc f32:$frB))]>; 2139 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2140 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB), 2141 "frim", "$frD, $frB", IIC_FPGeneral, 2142 [(set f64:$frD, (ffloor f64:$frB))]>; 2143 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB), 2144 "frim", "$frD, $frB", IIC_FPGeneral, 2145 [(set f32:$frD, (ffloor f32:$frB))]>; 2146 2147 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB), 2148 "fsqrt", "$frD, $frB", IIC_FPSqrtD, 2149 [(set f64:$frD, (fsqrt f64:$frB))]>; 2150 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB), 2151 "fsqrts", "$frD, $frB", IIC_FPSqrtS, 2152 [(set f32:$frD, (fsqrt f32:$frB))]>; 2153 } 2154 } 2155} 2156 2157/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 2158/// often coalesced away and we don't want the dispatch group builder to think 2159/// that they will fill slots (which could cause the load of a LSU reject to 2160/// sneak into a d-group with a store). 2161let hasSideEffects = 0 in 2162defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB), 2163 "fmr", "$frD, $frB", IIC_FPGeneral, 2164 []>, // (set f32:$frD, f32:$frB) 2165 PPC970_Unit_Pseudo; 2166 2167let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations. 2168// These are artificially split into two different forms, for 4/8 byte FP. 2169defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB), 2170 "fabs", "$frD, $frB", IIC_FPGeneral, 2171 [(set f32:$frD, (fabs f32:$frB))]>; 2172let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2173defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB), 2174 "fabs", "$frD, $frB", IIC_FPGeneral, 2175 [(set f64:$frD, (fabs f64:$frB))]>; 2176defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB), 2177 "fnabs", "$frD, $frB", IIC_FPGeneral, 2178 [(set f32:$frD, (fneg (fabs f32:$frB)))]>; 2179let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2180defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB), 2181 "fnabs", "$frD, $frB", IIC_FPGeneral, 2182 [(set f64:$frD, (fneg (fabs f64:$frB)))]>; 2183defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB), 2184 "fneg", "$frD, $frB", IIC_FPGeneral, 2185 [(set f32:$frD, (fneg f32:$frB))]>; 2186let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2187defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB), 2188 "fneg", "$frD, $frB", IIC_FPGeneral, 2189 [(set f64:$frD, (fneg f64:$frB))]>; 2190 2191defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB), 2192 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2193 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>; 2194let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2195defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB), 2196 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2197 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>; 2198 2199// Reciprocal estimates. 2200defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB), 2201 "fre", "$frD, $frB", IIC_FPGeneral, 2202 [(set f64:$frD, (PPCfre f64:$frB))]>; 2203defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB), 2204 "fres", "$frD, $frB", IIC_FPGeneral, 2205 [(set f32:$frD, (PPCfre f32:$frB))]>; 2206defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB), 2207 "frsqrte", "$frD, $frB", IIC_FPGeneral, 2208 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>; 2209defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB), 2210 "frsqrtes", "$frD, $frB", IIC_FPGeneral, 2211 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>; 2212} 2213 2214// XL-Form instructions. condition register logical ops. 2215// 2216let hasSideEffects = 0 in 2217def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), 2218 "mcrf $BF, $BFA", IIC_BrMCR>, 2219 PPC970_DGroup_First, PPC970_Unit_CRU; 2220 2221// FIXME: According to the ISA (section 2.5.1 of version 2.06), the 2222// condition-register logical instructions have preferred forms. Specifically, 2223// it is preferred that the bit specified by the BT field be in the same 2224// condition register as that specified by the bit BB. We might want to account 2225// for this via hinting the register allocator and anti-dep breakers, or we 2226// could constrain the register class to force this constraint and then loosen 2227// it during register allocation via convertToThreeAddress or some similar 2228// mechanism. 2229 2230let isCommutable = 1 in { 2231def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD), 2232 (ins crbitrc:$CRA, crbitrc:$CRB), 2233 "crand $CRD, $CRA, $CRB", IIC_BrCR, 2234 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>; 2235 2236def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD), 2237 (ins crbitrc:$CRA, crbitrc:$CRB), 2238 "crnand $CRD, $CRA, $CRB", IIC_BrCR, 2239 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>; 2240 2241def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD), 2242 (ins crbitrc:$CRA, crbitrc:$CRB), 2243 "cror $CRD, $CRA, $CRB", IIC_BrCR, 2244 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>; 2245 2246def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD), 2247 (ins crbitrc:$CRA, crbitrc:$CRB), 2248 "crxor $CRD, $CRA, $CRB", IIC_BrCR, 2249 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>; 2250 2251def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD), 2252 (ins crbitrc:$CRA, crbitrc:$CRB), 2253 "crnor $CRD, $CRA, $CRB", IIC_BrCR, 2254 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>; 2255 2256def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD), 2257 (ins crbitrc:$CRA, crbitrc:$CRB), 2258 "creqv $CRD, $CRA, $CRB", IIC_BrCR, 2259 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>; 2260} // isCommutable 2261 2262def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD), 2263 (ins crbitrc:$CRA, crbitrc:$CRB), 2264 "crandc $CRD, $CRA, $CRB", IIC_BrCR, 2265 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>; 2266 2267def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), 2268 (ins crbitrc:$CRA, crbitrc:$CRB), 2269 "crorc $CRD, $CRA, $CRB", IIC_BrCR, 2270 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>; 2271 2272let isCodeGenOnly = 1 in { 2273def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins), 2274 "creqv $dst, $dst, $dst", IIC_BrCR, 2275 [(set i1:$dst, 1)]>; 2276 2277def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins), 2278 "crxor $dst, $dst, $dst", IIC_BrCR, 2279 [(set i1:$dst, 0)]>; 2280 2281let Defs = [CR1EQ], CRD = 6 in { 2282def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 2283 "creqv 6, 6, 6", IIC_BrCR, 2284 [(PPCcr6set)]>; 2285 2286def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 2287 "crxor 6, 6, 6", IIC_BrCR, 2288 [(PPCcr6unset)]>; 2289} 2290} 2291 2292// XFX-Form instructions. Instructions that deal with SPRs. 2293// 2294 2295def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR), 2296 "mfspr $RT, $SPR", IIC_SprMFSPR>; 2297def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT), 2298 "mtspr $SPR, $RT", IIC_SprMTSPR>; 2299 2300def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), 2301 "mftb $RT, $SPR", IIC_SprMFTB>; 2302 2303// A pseudo-instruction used to implement the read of the 64-bit cycle counter 2304// on a 32-bit target. 2305let hasSideEffects = 1, usesCustomInserter = 1 in 2306def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins), 2307 "#ReadTB", []>; 2308 2309let Uses = [CTR] in { 2310def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins), 2311 "mfctr $rT", IIC_SprMFSPR>, 2312 PPC970_DGroup_First, PPC970_Unit_FXU; 2313} 2314let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in { 2315def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2316 "mtctr $rS", IIC_SprMTSPR>, 2317 PPC970_DGroup_First, PPC970_Unit_FXU; 2318} 2319let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in { 2320let Pattern = [(int_ppc_mtctr i32:$rS)] in 2321def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 2322 "mtctr $rS", IIC_SprMTSPR>, 2323 PPC970_DGroup_First, PPC970_Unit_FXU; 2324} 2325 2326let Defs = [LR] in { 2327def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS), 2328 "mtlr $rS", IIC_SprMTSPR>, 2329 PPC970_DGroup_First, PPC970_Unit_FXU; 2330} 2331let Uses = [LR] in { 2332def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins), 2333 "mflr $rT", IIC_SprMFSPR>, 2334 PPC970_DGroup_First, PPC970_Unit_FXU; 2335} 2336 2337let isCodeGenOnly = 1 in { 2338 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 2339 // like a GPR on the PPC970. As such, copies in and out have the same 2340 // performance characteristics as an OR instruction. 2341 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS), 2342 "mtspr 256, $rS", IIC_IntGeneral>, 2343 PPC970_DGroup_Single, PPC970_Unit_FXU; 2344 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins), 2345 "mfspr $rT, 256", IIC_IntGeneral>, 2346 PPC970_DGroup_First, PPC970_Unit_FXU; 2347 2348 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256, 2349 (outs VRSAVERC:$reg), (ins gprc:$rS), 2350 "mtspr 256, $rS", IIC_IntGeneral>, 2351 PPC970_DGroup_Single, PPC970_Unit_FXU; 2352 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), 2353 (ins VRSAVERC:$reg), 2354 "mfspr $rT, 256", IIC_IntGeneral>, 2355 PPC970_DGroup_First, PPC970_Unit_FXU; 2356} 2357 2358// Aliases for mtvrsave/mfvrsave to mfspr/mtspr. 2359def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>; 2360def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>; 2361 2362// SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register, 2363// so we'll need to scavenge a register for it. 2364let mayStore = 1 in 2365def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F), 2366 "#SPILL_VRSAVE", []>; 2367 2368// RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously 2369// spilled), so we'll need to scavenge a register for it. 2370let mayLoad = 1 in 2371def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F), 2372 "#RESTORE_VRSAVE", []>; 2373 2374let hasSideEffects = 0 in { 2375// mtocrf's input needs to be prepared by shifting by an amount dependent 2376// on the cr register selected. Thus, post-ra anti-dep breaking must not 2377// later change that register assignment. 2378let hasExtraDefRegAllocReq = 1 in { 2379def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST), 2380 "mtocrf $FXM, $ST", IIC_BrMCRX>, 2381 PPC970_DGroup_First, PPC970_Unit_CRU; 2382 2383// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 2384// is dependent on the cr fields being set. 2385def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS), 2386 "mtcrf $FXM, $rS", IIC_BrMCRX>, 2387 PPC970_MicroCode, PPC970_Unit_CRU; 2388} // hasExtraDefRegAllocReq = 1 2389 2390// mfocrf's input needs to be prepared by shifting by an amount dependent 2391// on the cr register selected. Thus, post-ra anti-dep breaking must not 2392// later change that register assignment. 2393let hasExtraSrcRegAllocReq = 1 in { 2394def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM), 2395 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 2396 PPC970_DGroup_First, PPC970_Unit_CRU; 2397 2398// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 2399// is dependent on the cr fields being copied. 2400def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins), 2401 "mfcr $rT", IIC_SprMFCR>, 2402 PPC970_MicroCode, PPC970_Unit_CRU; 2403} // hasExtraSrcRegAllocReq = 1 2404 2405def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins), 2406 "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>; 2407} // hasSideEffects = 0 2408 2409// Pseudo instruction to perform FADD in round-to-zero mode. 2410let usesCustomInserter = 1, Uses = [RM] in { 2411 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", 2412 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>; 2413} 2414 2415// The above pseudo gets expanded to make use of the following instructions 2416// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 2417let Uses = [RM], Defs = [RM] in { 2418 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 2419 "mtfsb0 $FM", IIC_IntMTFSB0, []>, 2420 PPC970_DGroup_Single, PPC970_Unit_FPU; 2421 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 2422 "mtfsb1 $FM", IIC_IntMTFSB0, []>, 2423 PPC970_DGroup_Single, PPC970_Unit_FPU; 2424 let isCodeGenOnly = 1 in 2425 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT), 2426 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>, 2427 PPC970_DGroup_Single, PPC970_Unit_FPU; 2428} 2429let Uses = [RM] in { 2430 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins), 2431 "mffs $rT", IIC_IntMFFS, 2432 [(set f64:$rT, (PPCmffs))]>, 2433 PPC970_DGroup_Single, PPC970_Unit_FPU; 2434 2435 let Defs = [CR1] in 2436 def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins), 2437 "mffs. $rT", IIC_IntMFFS, []>, isDOT; 2438} 2439 2440 2441let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2442// XO-Form instructions. Arithmetic instructions that can set overflow bit 2443let isCommutable = 1 in 2444defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2445 "add", "$rT, $rA, $rB", IIC_IntSimple, 2446 [(set i32:$rT, (add i32:$rA, i32:$rB))]>; 2447let isCodeGenOnly = 1 in 2448def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB), 2449 "add $rT, $rA, $rB", IIC_IntSimple, 2450 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>; 2451let isCommutable = 1 in 2452defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2453 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 2454 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>, 2455 PPC970_DGroup_Cracked; 2456 2457defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2458 "divw", "$rT, $rA, $rB", IIC_IntDivW, 2459 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>; 2460defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2461 "divwu", "$rT, $rA, $rB", IIC_IntDivW, 2462 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>; 2463def DIVWE : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2464 "divwe $rT, $rA, $rB", IIC_IntDivW, 2465 [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>, 2466 Requires<[HasExtDiv]>; 2467let Defs = [CR0] in 2468def DIVWEo : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2469 "divwe. $rT, $rA, $rB", IIC_IntDivW, 2470 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 2471 Requires<[HasExtDiv]>; 2472def DIVWEU : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2473 "divweu $rT, $rA, $rB", IIC_IntDivW, 2474 [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>, 2475 Requires<[HasExtDiv]>; 2476let Defs = [CR0] in 2477def DIVWEUo : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2478 "divweu. $rT, $rA, $rB", IIC_IntDivW, 2479 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First, 2480 Requires<[HasExtDiv]>; 2481let isCommutable = 1 in { 2482defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2483 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW, 2484 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>; 2485defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2486 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU, 2487 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>; 2488defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2489 "mullw", "$rT, $rA, $rB", IIC_IntMulHW, 2490 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>; 2491} // isCommutable 2492defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2493 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 2494 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>; 2495defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2496 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 2497 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>, 2498 PPC970_DGroup_Cracked; 2499defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA), 2500 "neg", "$rT, $rA", IIC_IntSimple, 2501 [(set i32:$rT, (ineg i32:$rA))]>; 2502let Uses = [CARRY] in { 2503let isCommutable = 1 in 2504defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2505 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 2506 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>; 2507defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA), 2508 "addme", "$rT, $rA", IIC_IntGeneral, 2509 [(set i32:$rT, (adde i32:$rA, -1))]>; 2510defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA), 2511 "addze", "$rT, $rA", IIC_IntGeneral, 2512 [(set i32:$rT, (adde i32:$rA, 0))]>; 2513defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2514 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 2515 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>; 2516defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA), 2517 "subfme", "$rT, $rA", IIC_IntGeneral, 2518 [(set i32:$rT, (sube -1, i32:$rA))]>; 2519defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA), 2520 "subfze", "$rT, $rA", IIC_IntGeneral, 2521 [(set i32:$rT, (sube 0, i32:$rA))]>; 2522} 2523} 2524 2525// A-Form instructions. Most of the instructions executed in the FPU are of 2526// this type. 2527// 2528let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations. 2529let Uses = [RM] in { 2530let isCommutable = 1 in { 2531 defm FMADD : AForm_1r<63, 29, 2532 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2533 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2534 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 2535 defm FMADDS : AForm_1r<59, 29, 2536 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2537 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2538 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 2539 defm FMSUB : AForm_1r<63, 28, 2540 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2541 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2542 [(set f64:$FRT, 2543 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 2544 defm FMSUBS : AForm_1r<59, 28, 2545 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2546 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2547 [(set f32:$FRT, 2548 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 2549 defm FNMADD : AForm_1r<63, 31, 2550 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2551 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2552 [(set f64:$FRT, 2553 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 2554 defm FNMADDS : AForm_1r<59, 31, 2555 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2556 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2557 [(set f32:$FRT, 2558 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 2559 defm FNMSUB : AForm_1r<63, 30, 2560 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2561 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 2562 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC, 2563 (fneg f64:$FRB))))]>; 2564 defm FNMSUBS : AForm_1r<59, 30, 2565 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2566 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2567 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC, 2568 (fneg f32:$FRB))))]>; 2569} // isCommutable 2570} 2571// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 2572// having 4 of these, force the comparison to always be an 8-byte double (code 2573// should use an FMRSD if the input comparison value really wants to be a float) 2574// and 4/8 byte forms for the result and operand type.. 2575let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2576defm FSELD : AForm_1r<63, 23, 2577 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2578 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2579 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 2580defm FSELS : AForm_1r<63, 23, 2581 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2582 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 2583 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 2584let Uses = [RM] in { 2585 let isCommutable = 1 in { 2586 defm FADD : AForm_2r<63, 21, 2587 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2588 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub, 2589 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>; 2590 defm FADDS : AForm_2r<59, 21, 2591 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2592 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral, 2593 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>; 2594 } // isCommutable 2595 defm FDIV : AForm_2r<63, 18, 2596 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2597 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD, 2598 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>; 2599 defm FDIVS : AForm_2r<59, 18, 2600 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2601 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS, 2602 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>; 2603 let isCommutable = 1 in { 2604 defm FMUL : AForm_3r<63, 25, 2605 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC), 2606 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused, 2607 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>; 2608 defm FMULS : AForm_3r<59, 25, 2609 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC), 2610 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral, 2611 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>; 2612 } // isCommutable 2613 defm FSUB : AForm_2r<63, 20, 2614 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2615 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub, 2616 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>; 2617 defm FSUBS : AForm_2r<59, 20, 2618 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2619 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral, 2620 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>; 2621 } 2622} 2623 2624let hasSideEffects = 0 in { 2625let PPC970_Unit = 1 in { // FXU Operations. 2626 let isSelect = 1 in 2627 def ISEL : AForm_4<31, 15, 2628 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond), 2629 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 2630 []>; 2631} 2632 2633let PPC970_Unit = 1 in { // FXU Operations. 2634// M-Form instructions. rotate and mask instructions. 2635// 2636let isCommutable = 1 in { 2637// RLWIMI can be commuted if the rotate amount is zero. 2638defm RLWIMI : MForm_2r<20, (outs gprc:$rA), 2639 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB, 2640 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 2641 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 2642 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 2643} 2644let BaseName = "rlwinm" in { 2645def RLWINM : MForm_2<21, 2646 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 2647 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 2648 []>, RecFormRel; 2649let Defs = [CR0] in 2650def RLWINMo : MForm_2<21, 2651 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 2652 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 2653 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked; 2654} 2655defm RLWNM : MForm_2r<23, (outs gprc:$rA), 2656 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME), 2657 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 2658 []>; 2659} 2660} // hasSideEffects = 0 2661 2662//===----------------------------------------------------------------------===// 2663// PowerPC Instruction Patterns 2664// 2665 2666// Arbitrary immediate support. Implement in terms of LIS/ORI. 2667def : Pat<(i32 imm:$imm), 2668 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 2669 2670// Implement the 'not' operation with the NOR instruction. 2671def i32not : OutPatFrag<(ops node:$in), 2672 (NOR $in, $in)>; 2673def : Pat<(not i32:$in), 2674 (i32not $in)>; 2675 2676// ADD an arbitrary immediate. 2677def : Pat<(add i32:$in, imm:$imm), 2678 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 2679// OR an arbitrary immediate. 2680def : Pat<(or i32:$in, imm:$imm), 2681 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 2682// XOR an arbitrary immediate. 2683def : Pat<(xor i32:$in, imm:$imm), 2684 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 2685// SUBFIC 2686def : Pat<(sub imm32SExt16:$imm, i32:$in), 2687 (SUBFIC $in, imm:$imm)>; 2688 2689// SHL/SRL 2690def : Pat<(shl i32:$in, (i32 imm:$imm)), 2691 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 2692def : Pat<(srl i32:$in, (i32 imm:$imm)), 2693 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 2694 2695// ROTL 2696def : Pat<(rotl i32:$in, i32:$sh), 2697 (RLWNM $in, $sh, 0, 31)>; 2698def : Pat<(rotl i32:$in, (i32 imm:$imm)), 2699 (RLWINM $in, imm:$imm, 0, 31)>; 2700 2701// RLWNM 2702def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 2703 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 2704 2705// Calls 2706def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 2707 (BL tglobaladdr:$dst)>; 2708def : Pat<(PPCcall (i32 texternalsym:$dst)), 2709 (BL texternalsym:$dst)>; 2710 2711def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 2712 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 2713 2714def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 2715 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 2716 2717def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 2718 (TCRETURNri CTRRC:$dst, imm:$imm)>; 2719 2720 2721 2722// Hi and Lo for Darwin Global Addresses. 2723def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 2724def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 2725def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 2726def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 2727def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 2728def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 2729def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 2730def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 2731def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 2732 (ADDIS $in, tglobaltlsaddr:$g)>; 2733def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 2734 (ADDI $in, tglobaltlsaddr:$g)>; 2735def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 2736 (ADDIS $in, tglobaladdr:$g)>; 2737def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 2738 (ADDIS $in, tconstpool:$g)>; 2739def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 2740 (ADDIS $in, tjumptable:$g)>; 2741def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 2742 (ADDIS $in, tblockaddress:$g)>; 2743 2744// Support for thread-local storage. 2745def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT", 2746 [(set i32:$rD, (PPCppc32GOT))]>; 2747 2748// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode. 2749// This uses two output registers, the first as the real output, the second as a 2750// temporary register, used internally in code generation. 2751def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", 2752 []>, NoEncode<"$rT">; 2753 2754def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg), 2755 "#LDgotTprelL32", 2756 [(set i32:$rD, 2757 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; 2758def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), 2759 (ADD4TLS $in, tglobaltlsaddr:$g)>; 2760 2761def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 2762 "#ADDItlsgdL32", 2763 [(set i32:$rD, 2764 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>; 2765// LR is a true define, while the rest of the Defs are clobbers. R3 is 2766// explicitly defined when this op is created, so not mentioned here. 2767let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 2768 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 2769def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 2770 "GETtlsADDR32", 2771 [(set i32:$rD, 2772 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>; 2773// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR 2774// are true defines while the rest of the Defs are clobbers. 2775let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 2776 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 2777def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD), 2778 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 2779 "#ADDItlsgdLADDR32", 2780 [(set i32:$rD, 2781 (PPCaddiTlsgdLAddr i32:$reg, 2782 tglobaltlsaddr:$disp, 2783 tglobaltlsaddr:$sym))]>; 2784def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 2785 "#ADDItlsldL32", 2786 [(set i32:$rD, 2787 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>; 2788// LR is a true define, while the rest of the Defs are clobbers. R3 is 2789// explicitly defined when this op is created, so not mentioned here. 2790let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 2791 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 2792def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 2793 "GETtlsldADDR32", 2794 [(set i32:$rD, 2795 (PPCgetTlsldAddr i32:$reg, 2796 tglobaltlsaddr:$sym))]>; 2797// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR 2798// are true defines while the rest of the Defs are clobbers. 2799let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 2800 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 2801def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD), 2802 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 2803 "#ADDItlsldLADDR32", 2804 [(set i32:$rD, 2805 (PPCaddiTlsldLAddr i32:$reg, 2806 tglobaltlsaddr:$disp, 2807 tglobaltlsaddr:$sym))]>; 2808def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 2809 "#ADDIdtprelL32", 2810 [(set i32:$rD, 2811 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>; 2812def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 2813 "#ADDISdtprelHA32", 2814 [(set i32:$rD, 2815 (PPCaddisDtprelHA i32:$reg, 2816 tglobaltlsaddr:$disp))]>; 2817 2818// Support for Position-independent code 2819def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 2820 "#LWZtoc", 2821 [(set i32:$rD, 2822 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 2823// Get Global (GOT) Base Register offset, from the word immediately preceding 2824// the function label. 2825def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>; 2826 2827 2828// Standard shifts. These are represented separately from the real shifts above 2829// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 2830// amounts. 2831def : Pat<(sra i32:$rS, i32:$rB), 2832 (SRAW $rS, $rB)>; 2833def : Pat<(srl i32:$rS, i32:$rB), 2834 (SRW $rS, $rB)>; 2835def : Pat<(shl i32:$rS, i32:$rB), 2836 (SLW $rS, $rB)>; 2837 2838def : Pat<(zextloadi1 iaddr:$src), 2839 (LBZ iaddr:$src)>; 2840def : Pat<(zextloadi1 xaddr:$src), 2841 (LBZX xaddr:$src)>; 2842def : Pat<(extloadi1 iaddr:$src), 2843 (LBZ iaddr:$src)>; 2844def : Pat<(extloadi1 xaddr:$src), 2845 (LBZX xaddr:$src)>; 2846def : Pat<(extloadi8 iaddr:$src), 2847 (LBZ iaddr:$src)>; 2848def : Pat<(extloadi8 xaddr:$src), 2849 (LBZX xaddr:$src)>; 2850def : Pat<(extloadi16 iaddr:$src), 2851 (LHZ iaddr:$src)>; 2852def : Pat<(extloadi16 xaddr:$src), 2853 (LHZX xaddr:$src)>; 2854def : Pat<(f64 (extloadf32 iaddr:$src)), 2855 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>; 2856def : Pat<(f64 (extloadf32 xaddr:$src)), 2857 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; 2858 2859def : Pat<(f64 (fextend f32:$src)), 2860 (COPY_TO_REGCLASS $src, F8RC)>; 2861 2862// Only seq_cst fences require the heavyweight sync (SYNC 0). 2863// All others can use the lightweight sync (SYNC 1). 2864// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html 2865// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits 2866// versions of Power. 2867def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>; 2868def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>; 2869def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>; 2870def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2871 2872// Additional FNMSUB patterns: -a*c + b == -(a*c - b) 2873def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B), 2874 (FNMSUB $A, $C, $B)>; 2875def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B), 2876 (FNMSUB $A, $C, $B)>; 2877def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B), 2878 (FNMSUBS $A, $C, $B)>; 2879def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B), 2880 (FNMSUBS $A, $C, $B)>; 2881 2882// FCOPYSIGN's operand types need not agree. 2883def : Pat<(fcopysign f64:$frB, f32:$frA), 2884 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>; 2885def : Pat<(fcopysign f32:$frB, f64:$frA), 2886 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>; 2887 2888include "PPCInstrAltivec.td" 2889include "PPCInstrSPE.td" 2890include "PPCInstr64Bit.td" 2891include "PPCInstrVSX.td" 2892include "PPCInstrQPX.td" 2893include "PPCInstrHTM.td" 2894 2895def crnot : OutPatFrag<(ops node:$in), 2896 (CRNOR $in, $in)>; 2897def : Pat<(not i1:$in), 2898 (crnot $in)>; 2899 2900// Patterns for arithmetic i1 operations. 2901def : Pat<(add i1:$a, i1:$b), 2902 (CRXOR $a, $b)>; 2903def : Pat<(sub i1:$a, i1:$b), 2904 (CRXOR $a, $b)>; 2905def : Pat<(mul i1:$a, i1:$b), 2906 (CRAND $a, $b)>; 2907 2908// We're sometimes asked to materialize i1 -1, which is just 1 in this case 2909// (-1 is used to mean all bits set). 2910def : Pat<(i1 -1), (CRSET)>; 2911 2912// i1 extensions, implemented in terms of isel. 2913def : Pat<(i32 (zext i1:$in)), 2914 (SELECT_I4 $in, (LI 1), (LI 0))>; 2915def : Pat<(i32 (sext i1:$in)), 2916 (SELECT_I4 $in, (LI -1), (LI 0))>; 2917 2918def : Pat<(i64 (zext i1:$in)), 2919 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 2920def : Pat<(i64 (sext i1:$in)), 2921 (SELECT_I8 $in, (LI8 -1), (LI8 0))>; 2922 2923// FIXME: We should choose either a zext or a sext based on other constants 2924// already around. 2925def : Pat<(i32 (anyext i1:$in)), 2926 (SELECT_I4 $in, (LI 1), (LI 0))>; 2927def : Pat<(i64 (anyext i1:$in)), 2928 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 2929 2930// match setcc on i1 variables. 2931// CRANDC is: 2932// 1 1 : F 2933// 1 0 : T 2934// 0 1 : F 2935// 0 0 : F 2936// 2937// LT is: 2938// -1 -1 : F 2939// -1 0 : T 2940// 0 -1 : F 2941// 0 0 : F 2942// 2943// ULT is: 2944// 1 1 : F 2945// 1 0 : F 2946// 0 1 : T 2947// 0 0 : F 2948def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 2949 (CRANDC $s1, $s2)>; 2950def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 2951 (CRANDC $s2, $s1)>; 2952// CRORC is: 2953// 1 1 : T 2954// 1 0 : T 2955// 0 1 : F 2956// 0 0 : T 2957// 2958// LE is: 2959// -1 -1 : T 2960// -1 0 : T 2961// 0 -1 : F 2962// 0 0 : T 2963// 2964// ULE is: 2965// 1 1 : T 2966// 1 0 : F 2967// 0 1 : T 2968// 0 0 : T 2969def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 2970 (CRORC $s1, $s2)>; 2971def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 2972 (CRORC $s2, $s1)>; 2973 2974def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 2975 (CREQV $s1, $s2)>; 2976 2977// GE is: 2978// -1 -1 : T 2979// -1 0 : F 2980// 0 -1 : T 2981// 0 0 : T 2982// 2983// UGE is: 2984// 1 1 : T 2985// 1 0 : T 2986// 0 1 : F 2987// 0 0 : T 2988def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 2989 (CRORC $s2, $s1)>; 2990def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 2991 (CRORC $s1, $s2)>; 2992 2993// GT is: 2994// -1 -1 : F 2995// -1 0 : F 2996// 0 -1 : T 2997// 0 0 : F 2998// 2999// UGT is: 3000// 1 1 : F 3001// 1 0 : T 3002// 0 1 : F 3003// 0 0 : F 3004def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 3005 (CRANDC $s2, $s1)>; 3006def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), 3007 (CRANDC $s1, $s2)>; 3008 3009def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)), 3010 (CRXOR $s1, $s2)>; 3011 3012// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE, 3013// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for 3014// floating-point types. 3015 3016multiclass CRNotPat<dag pattern, dag result> { 3017 def : Pat<pattern, (crnot result)>; 3018 def : Pat<(not pattern), result>; 3019 3020 // We can also fold the crnot into an extension: 3021 def : Pat<(i32 (zext pattern)), 3022 (SELECT_I4 result, (LI 0), (LI 1))>; 3023 def : Pat<(i32 (sext pattern)), 3024 (SELECT_I4 result, (LI 0), (LI -1))>; 3025 3026 // We can also fold the crnot into an extension: 3027 def : Pat<(i64 (zext pattern)), 3028 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3029 def : Pat<(i64 (sext pattern)), 3030 (SELECT_I8 result, (LI8 0), (LI8 -1))>; 3031 3032 // FIXME: We should choose either a zext or a sext based on other constants 3033 // already around. 3034 def : Pat<(i32 (anyext pattern)), 3035 (SELECT_I4 result, (LI 0), (LI 1))>; 3036 3037 def : Pat<(i64 (anyext pattern)), 3038 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3039} 3040 3041// FIXME: Because of what seems like a bug in TableGen's type-inference code, 3042// we need to write imm:$imm in the output patterns below, not just $imm, or 3043// else the resulting matcher will not correctly add the immediate operand 3044// (making it a register operand instead). 3045 3046// extended SETCC. 3047multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag, 3048 OutPatFrag rfrag, OutPatFrag rfrag8> { 3049 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))), 3050 (rfrag $s1)>; 3051 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))), 3052 (rfrag8 $s1)>; 3053 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))), 3054 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3055 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))), 3056 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3057 3058 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))), 3059 (rfrag $s1)>; 3060 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))), 3061 (rfrag8 $s1)>; 3062 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))), 3063 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3064 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))), 3065 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3066} 3067 3068// Note that we do all inversions below with i(32|64)not, instead of using 3069// (xori x, 1) because on the A2 nor has single-cycle latency while xori 3070// has 2-cycle latency. 3071 3072defm : ExtSetCCPat<SETEQ, 3073 PatFrag<(ops node:$in, node:$cc), 3074 (setcc $in, 0, $cc)>, 3075 OutPatFrag<(ops node:$in), 3076 (RLWINM (CNTLZW $in), 27, 31, 31)>, 3077 OutPatFrag<(ops node:$in), 3078 (RLDICL (CNTLZD $in), 58, 63)> >; 3079 3080defm : ExtSetCCPat<SETNE, 3081 PatFrag<(ops node:$in, node:$cc), 3082 (setcc $in, 0, $cc)>, 3083 OutPatFrag<(ops node:$in), 3084 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>, 3085 OutPatFrag<(ops node:$in), 3086 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >; 3087 3088defm : ExtSetCCPat<SETLT, 3089 PatFrag<(ops node:$in, node:$cc), 3090 (setcc $in, 0, $cc)>, 3091 OutPatFrag<(ops node:$in), 3092 (RLWINM $in, 1, 31, 31)>, 3093 OutPatFrag<(ops node:$in), 3094 (RLDICL $in, 1, 63)> >; 3095 3096defm : ExtSetCCPat<SETGE, 3097 PatFrag<(ops node:$in, node:$cc), 3098 (setcc $in, 0, $cc)>, 3099 OutPatFrag<(ops node:$in), 3100 (RLWINM (i32not $in), 1, 31, 31)>, 3101 OutPatFrag<(ops node:$in), 3102 (RLDICL (i64not $in), 1, 63)> >; 3103 3104defm : ExtSetCCPat<SETGT, 3105 PatFrag<(ops node:$in, node:$cc), 3106 (setcc $in, 0, $cc)>, 3107 OutPatFrag<(ops node:$in), 3108 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>, 3109 OutPatFrag<(ops node:$in), 3110 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >; 3111 3112defm : ExtSetCCPat<SETLE, 3113 PatFrag<(ops node:$in, node:$cc), 3114 (setcc $in, 0, $cc)>, 3115 OutPatFrag<(ops node:$in), 3116 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>, 3117 OutPatFrag<(ops node:$in), 3118 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >; 3119 3120defm : ExtSetCCPat<SETLT, 3121 PatFrag<(ops node:$in, node:$cc), 3122 (setcc $in, -1, $cc)>, 3123 OutPatFrag<(ops node:$in), 3124 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>, 3125 OutPatFrag<(ops node:$in), 3126 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3127 3128defm : ExtSetCCPat<SETGE, 3129 PatFrag<(ops node:$in, node:$cc), 3130 (setcc $in, -1, $cc)>, 3131 OutPatFrag<(ops node:$in), 3132 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>, 3133 OutPatFrag<(ops node:$in), 3134 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3135 3136defm : ExtSetCCPat<SETGT, 3137 PatFrag<(ops node:$in, node:$cc), 3138 (setcc $in, -1, $cc)>, 3139 OutPatFrag<(ops node:$in), 3140 (RLWINM (i32not $in), 1, 31, 31)>, 3141 OutPatFrag<(ops node:$in), 3142 (RLDICL (i64not $in), 1, 63)> >; 3143 3144defm : ExtSetCCPat<SETLE, 3145 PatFrag<(ops node:$in, node:$cc), 3146 (setcc $in, -1, $cc)>, 3147 OutPatFrag<(ops node:$in), 3148 (RLWINM $in, 1, 31, 31)>, 3149 OutPatFrag<(ops node:$in), 3150 (RLDICL $in, 1, 63)> >; 3151 3152// SETCC for i32. 3153def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)), 3154 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3155def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)), 3156 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3157def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)), 3158 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3159def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)), 3160 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3161def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)), 3162 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3163def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)), 3164 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3165 3166// For non-equality comparisons, the default code would materialize the 3167// constant, then compare against it, like this: 3168// lis r2, 4660 3169// ori r2, r2, 22136 3170// cmpw cr0, r3, r2 3171// beq cr0,L6 3172// Since we are just comparing for equality, we can emit this instead: 3173// xoris r0,r3,0x1234 3174// cmplwi cr0,r0,0x5678 3175// beq cr0,L6 3176 3177def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)), 3178 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3179 (LO16 imm:$imm)), sub_eq)>; 3180 3181defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)), 3182 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3183defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)), 3184 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3185defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)), 3186 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3187defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)), 3188 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3189defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)), 3190 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3191defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)), 3192 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3193 3194defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 3195 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3196 (LO16 imm:$imm)), sub_eq)>; 3197 3198def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)), 3199 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3200def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)), 3201 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3202def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)), 3203 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3204def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)), 3205 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3206def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)), 3207 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3208 3209defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)), 3210 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3211defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)), 3212 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3213defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)), 3214 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3215defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)), 3216 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3217defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)), 3218 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3219 3220// SETCC for i64. 3221def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)), 3222 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3223def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)), 3224 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3225def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)), 3226 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3227def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)), 3228 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3229def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)), 3230 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3231def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)), 3232 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3233 3234// For non-equality comparisons, the default code would materialize the 3235// constant, then compare against it, like this: 3236// lis r2, 4660 3237// ori r2, r2, 22136 3238// cmpd cr0, r3, r2 3239// beq cr0,L6 3240// Since we are just comparing for equality, we can emit this instead: 3241// xoris r0,r3,0x1234 3242// cmpldi cr0,r0,0x5678 3243// beq cr0,L6 3244 3245def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)), 3246 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3247 (LO16 imm:$imm)), sub_eq)>; 3248 3249defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)), 3250 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3251defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)), 3252 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3253defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)), 3254 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3255defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)), 3256 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3257defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)), 3258 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3259defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)), 3260 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3261 3262defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 3263 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3264 (LO16 imm:$imm)), sub_eq)>; 3265 3266def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)), 3267 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3268def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)), 3269 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3270def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)), 3271 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3272def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)), 3273 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3274def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)), 3275 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3276 3277defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)), 3278 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3279defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)), 3280 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3281defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), 3282 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3283defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)), 3284 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3285defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)), 3286 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3287 3288// SETCC for f32. 3289def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)), 3290 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3291def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)), 3292 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3293def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)), 3294 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3295def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)), 3296 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3297def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)), 3298 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3299def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)), 3300 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3301def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)), 3302 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>; 3303 3304defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)), 3305 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3306defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)), 3307 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>; 3308defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)), 3309 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3310defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)), 3311 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>; 3312defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)), 3313 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3314defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)), 3315 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>; 3316defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)), 3317 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>; 3318 3319// SETCC for f64. 3320def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)), 3321 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3322def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)), 3323 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3324def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)), 3325 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3326def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)), 3327 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3328def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)), 3329 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3330def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)), 3331 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3332def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)), 3333 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>; 3334 3335defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)), 3336 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3337defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)), 3338 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>; 3339defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)), 3340 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3341defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)), 3342 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>; 3343defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)), 3344 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3345defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)), 3346 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>; 3347defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)), 3348 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>; 3349 3350// match select on i1 variables: 3351def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), 3352 (CROR (CRAND $cond , $tval), 3353 (CRAND (crnot $cond), $fval))>; 3354 3355// match selectcc on i1 variables: 3356// select (lhs == rhs), tval, fval is: 3357// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) 3358def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), 3359 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 3360 (CRAND (CRORC $rhs, $lhs), $fval))>; 3361def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)), 3362 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 3363 (CRAND (CRORC $lhs, $rhs), $fval))>; 3364def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)), 3365 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 3366 (CRAND (CRANDC $rhs, $lhs), $fval))>; 3367def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)), 3368 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 3369 (CRAND (CRANDC $lhs, $rhs), $fval))>; 3370def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)), 3371 (CROR (CRAND (CREQV $lhs, $rhs), $tval), 3372 (CRAND (CRXOR $lhs, $rhs), $fval))>; 3373def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), 3374 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 3375 (CRAND (CRANDC $lhs, $rhs), $fval))>; 3376def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)), 3377 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 3378 (CRAND (CRANDC $rhs, $lhs), $fval))>; 3379def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)), 3380 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 3381 (CRAND (CRORC $lhs, $rhs), $fval))>; 3382def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)), 3383 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 3384 (CRAND (CRORC $rhs, $lhs), $fval))>; 3385def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), 3386 (CROR (CRAND (CREQV $lhs, $rhs), $fval), 3387 (CRAND (CRXOR $lhs, $rhs), $tval))>; 3388 3389// match selectcc on i1 variables with non-i1 output. 3390def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)), 3391 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3392def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)), 3393 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3394def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)), 3395 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 3396def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)), 3397 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 3398def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)), 3399 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>; 3400def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)), 3401 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 3402def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)), 3403 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 3404def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)), 3405 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3406def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)), 3407 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3408def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)), 3409 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>; 3410 3411def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)), 3412 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 3413def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)), 3414 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3415def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)), 3416 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 3417def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)), 3418 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 3419def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)), 3420 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>; 3421def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)), 3422 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 3423def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)), 3424 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 3425def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), 3426 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3427def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)), 3428 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 3429def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), 3430 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; 3431 3432def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 3433 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3434def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 3435 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3436def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 3437 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 3438def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 3439 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 3440def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 3441 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>; 3442def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 3443 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 3444def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 3445 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 3446def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 3447 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 3448def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 3449 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 3450def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 3451 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>; 3452 3453def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 3454 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 3455def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 3456 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3457def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 3458 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 3459def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 3460 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 3461def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 3462 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>; 3463def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 3464 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 3465def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 3466 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 3467def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 3468 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 3469def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 3470 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 3471def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 3472 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; 3473 3474def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)), 3475 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 3476def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)), 3477 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 3478def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)), 3479 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 3480def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)), 3481 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 3482def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)), 3483 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>; 3484def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)), 3485 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 3486def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)), 3487 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 3488def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)), 3489 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 3490def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)), 3491 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 3492def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), 3493 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; 3494 3495let usesCustomInserter = 1 in { 3496def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in), 3497 "#ANDIo_1_EQ_BIT", 3498 [(set i1:$dst, (trunc (not i32:$in)))]>; 3499def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in), 3500 "#ANDIo_1_GT_BIT", 3501 [(set i1:$dst, (trunc i32:$in))]>; 3502 3503def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in), 3504 "#ANDIo_1_EQ_BIT8", 3505 [(set i1:$dst, (trunc (not i64:$in)))]>; 3506def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in), 3507 "#ANDIo_1_GT_BIT8", 3508 [(set i1:$dst, (trunc i64:$in))]>; 3509} 3510 3511def : Pat<(i1 (not (trunc i32:$in))), 3512 (ANDIo_1_EQ_BIT $in)>; 3513def : Pat<(i1 (not (trunc i64:$in))), 3514 (ANDIo_1_EQ_BIT8 $in)>; 3515 3516//===----------------------------------------------------------------------===// 3517// PowerPC Instructions used for assembler/disassembler only 3518// 3519 3520// FIXME: For B=0 or B > 8, the registers following RT are used. 3521// WARNING: Do not add patterns for this instruction without fixing this. 3522def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B), 3523 "lswi $RT, $A, $B", IIC_LdStLoad, []>; 3524 3525// FIXME: For B=0 or B > 8, the registers following RT are used. 3526// WARNING: Do not add patterns for this instruction without fixing this. 3527def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B), 3528 "stswi $RT, $A, $B", IIC_LdStLoad, []>; 3529 3530def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), 3531 "isync", IIC_SprISYNC, []>; 3532 3533def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src), 3534 "icbi $src", IIC_LdStICBI, []>; 3535 3536// We used to have EIEIO as value but E[0-9A-Z] is a reserved name 3537def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins), 3538 "eieio", IIC_LdStLoad, []>; 3539 3540def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L), 3541 "wait $L", IIC_LdStLoad, []>; 3542 3543def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO), 3544 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>; 3545 3546def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR), 3547 "mtsr $SR, $RS", IIC_SprMTSR>; 3548 3549def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR), 3550 "mfsr $RS, $SR", IIC_SprMFSR>; 3551 3552def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB), 3553 "mtsrin $RS, $RB", IIC_SprMTSR>; 3554 3555def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB), 3556 "mfsrin $RS, $RB", IIC_SprMFSR>; 3557 3558def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L), 3559 "mtmsr $RS, $L", IIC_SprMTMSR>; 3560 3561def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS), 3562 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> { 3563 let L = 0; 3564} 3565 3566def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>, 3567 Requires<[IsBookE]> { 3568 bits<1> E; 3569 3570 let Inst{16} = E; 3571 let Inst{21-30} = 163; 3572} 3573 3574def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B), 3575 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 3576def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B), 3577 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 3578 3579def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 3580def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 3581def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 3582def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 3583 3584def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins), 3585 "mfmsr $RT", IIC_SprMFMSR, []>; 3586 3587def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L), 3588 "mtmsrd $RS, $L", IIC_SprMTMSRD>; 3589 3590def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA), 3591 "mcrfs $BF, $BFA", IIC_BrMCR>; 3592 3593def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W), 3594 "mtfsfi $BF, $U, $W", IIC_IntMFFS>; 3595 3596def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W), 3597 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT; 3598 3599def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>; 3600def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>; 3601 3602def MTFSF : XFLForm_1<63, 711, (outs), 3603 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W), 3604 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>; 3605def MTFSFo : XFLForm_1<63, 711, (outs), 3606 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W), 3607 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT; 3608 3609def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>; 3610def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>; 3611 3612def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), 3613 "slbie $RB", IIC_SprSLBIE, []>; 3614 3615def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB), 3616 "slbmte $RS, $RB", IIC_SprSLBMTE, []>; 3617 3618def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB), 3619 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>; 3620 3621def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; 3622 3623def TLBIA : XForm_0<31, 370, (outs), (ins), 3624 "tlbia", IIC_SprTLBIA, []>; 3625 3626def TLBSYNC : XForm_0<31, 566, (outs), (ins), 3627 "tlbsync", IIC_SprTLBSYNC, []>; 3628 3629def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), 3630 "tlbiel $RB", IIC_SprTLBIEL, []>; 3631 3632def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB), 3633 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 3634def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB), 3635 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 3636 3637def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB), 3638 "tlbie $RB,$RS", IIC_SprTLBIE, []>; 3639 3640def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B", 3641 IIC_LdStLoad>, Requires<[IsBookE]>; 3642 3643def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B", 3644 IIC_LdStLoad>, Requires<[IsBookE]>; 3645 3646def TLBRE : XForm_24_eieio<31, 946, (outs), (ins), 3647 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>; 3648 3649def TLBWE : XForm_24_eieio<31, 978, (outs), (ins), 3650 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>; 3651 3652def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS), 3653 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 3654 3655def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS), 3656 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 3657 3658def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), 3659 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>, 3660 Requires<[IsPPC4xx]>; 3661def TLBSX2D : XForm_base_r3xo<31, 914, (outs), 3662 (ins gprc:$RST, gprc:$A, gprc:$B), 3663 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>, 3664 Requires<[IsPPC4xx]>, isDOT; 3665 3666def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>; 3667 3668def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>, 3669 Requires<[IsBookE]>; 3670def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>, 3671 Requires<[IsBookE]>; 3672 3673def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>, 3674 Requires<[IsE500]>; 3675def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>, 3676 Requires<[IsE500]>; 3677 3678def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR), 3679 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; 3680def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR), 3681 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; 3682 3683def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; 3684 3685def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B), 3686 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>; 3687def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B), 3688 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>; 3689def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B), 3690 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>; 3691def LDCIX : XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B), 3692 "ldcix $RST, $A, $B", IIC_LdStLoad, []>; 3693 3694def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), 3695 "stbcix $RST, $A, $B", IIC_LdStLoad, []>; 3696def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), 3697 "sthcix $RST, $A, $B", IIC_LdStLoad, []>; 3698def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), 3699 "stwcix $RST, $A, $B", IIC_LdStLoad, []>; 3700def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), 3701 "stdcix $RST, $A, $B", IIC_LdStLoad, []>; 3702 3703//===----------------------------------------------------------------------===// 3704// PowerPC Assembler Instruction Aliases 3705// 3706 3707// Pseudo-instructions for alternate assembly syntax (never used by codegen). 3708// These are aliases that require C++ handling to convert to the target 3709// instruction, while InstAliases can be handled directly by tblgen. 3710class PPCAsmPseudo<string asm, dag iops> 3711 : Instruction { 3712 let Namespace = "PPC"; 3713 bit PPC64 = 0; // Default value, override with isPPC64 3714 3715 let OutOperandList = (outs); 3716 let InOperandList = iops; 3717 let Pattern = []; 3718 let AsmString = asm; 3719 let isAsmParserOnly = 1; 3720 let isPseudo = 1; 3721} 3722 3723def : InstAlias<"sc", (SC 0)>; 3724 3725def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>; 3726def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>; 3727def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>; 3728def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>; 3729 3730def : InstAlias<"wait", (WAIT 0)>; 3731def : InstAlias<"waitrsv", (WAIT 1)>; 3732def : InstAlias<"waitimpl", (WAIT 2)>; 3733 3734def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>; 3735 3736def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>; 3737def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>; 3738 3739def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 3740def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 3741def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>; 3742 3743def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 3744def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 3745def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>; 3746 3747def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 3748def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 3749def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 3750def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 3751 3752def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 3753def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 3754 3755def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>; 3756def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>; 3757 3758def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>; 3759def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>; 3760 3761def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>; 3762def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>; 3763 3764def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>; 3765def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>; 3766 3767def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>; 3768def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>; 3769 3770def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>; 3771def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>; 3772 3773def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>; 3774def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>; 3775 3776def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>; 3777def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>; 3778 3779def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3780def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>; 3781 3782def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3783def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>; 3784 3785def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>; 3786def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>; 3787 3788def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>; 3789def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>; 3790 3791def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>; 3792def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>; 3793 3794def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 3795def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>; 3796def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 3797 3798def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>; 3799def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>; 3800 3801def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>; 3802def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3803def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>; 3804def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3805 3806def : InstAlias<"xnop", (XORI R0, R0, 0)>; 3807 3808def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 3809def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 3810 3811def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 3812def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 3813 3814def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 3815 3816foreach BATR = 0-3 in { 3817 def : InstAlias<"mtdbatu "#BATR#", $Rx", 3818 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>, 3819 Requires<[IsPPC6xx]>; 3820 def : InstAlias<"mfdbatu $Rx, "#BATR, 3821 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>, 3822 Requires<[IsPPC6xx]>; 3823 def : InstAlias<"mtdbatl "#BATR#", $Rx", 3824 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>, 3825 Requires<[IsPPC6xx]>; 3826 def : InstAlias<"mfdbatl $Rx, "#BATR, 3827 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>, 3828 Requires<[IsPPC6xx]>; 3829 def : InstAlias<"mtibatu "#BATR#", $Rx", 3830 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>, 3831 Requires<[IsPPC6xx]>; 3832 def : InstAlias<"mfibatu $Rx, "#BATR, 3833 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>, 3834 Requires<[IsPPC6xx]>; 3835 def : InstAlias<"mtibatl "#BATR#", $Rx", 3836 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>, 3837 Requires<[IsPPC6xx]>; 3838 def : InstAlias<"mfibatl $Rx, "#BATR, 3839 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>, 3840 Requires<[IsPPC6xx]>; 3841} 3842 3843foreach BR = 0-7 in { 3844 def : InstAlias<"mfbr"#BR#" $Rx", 3845 (MFDCR gprc:$Rx, !add(BR, 0x80))>, 3846 Requires<[IsPPC4xx]>; 3847 def : InstAlias<"mtbr"#BR#" $Rx", 3848 (MTDCR gprc:$Rx, !add(BR, 0x80))>, 3849 Requires<[IsPPC4xx]>; 3850} 3851 3852def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3853def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>; 3854 3855def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3856def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>; 3857 3858def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3859def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>; 3860 3861def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3862def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>; 3863 3864def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>; 3865def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>; 3866 3867def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>; 3868def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>; 3869 3870def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>; 3871 3872def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", 3873 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 3874def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm", 3875 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 3876def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm", 3877 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 3878def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm", 3879 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 3880 3881def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 3882def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 3883def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 3884def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 3885 3886def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>; 3887def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>; 3888 3889def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>; 3890def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>; 3891 3892foreach SPRG = 0-3 in { 3893 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>; 3894 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>; 3895 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 3896 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 3897} 3898foreach SPRG = 4-7 in { 3899 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>, 3900 Requires<[IsBookE]>; 3901 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>, 3902 Requires<[IsBookE]>; 3903 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 3904 Requires<[IsBookE]>; 3905 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 3906 Requires<[IsBookE]>; 3907} 3908 3909def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>; 3910 3911def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>; 3912def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>; 3913 3914def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>; 3915 3916def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>; 3917def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>; 3918 3919def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>; 3920def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>; 3921def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>; 3922def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>; 3923 3924def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>; 3925 3926def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>, 3927 Requires<[IsPPC4xx]>; 3928def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>, 3929 Requires<[IsPPC4xx]>; 3930def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>, 3931 Requires<[IsPPC4xx]>; 3932def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>, 3933 Requires<[IsPPC4xx]>; 3934 3935def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", 3936 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3937def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", 3938 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3939def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", 3940 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3941def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", 3942 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3943def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", 3944 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3945def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", 3946 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3947def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", 3948 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3949def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", 3950 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 3951def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", 3952 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3953def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", 3954 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3955def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", 3956 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3957def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n", 3958 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3959def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", 3960 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3961def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n", 3962 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3963def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", 3964 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3965def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", 3966 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 3967def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", 3968 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 3969def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", 3970 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 3971 3972def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 3973def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 3974def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 3975def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 3976def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 3977def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 3978 3979def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>; 3980def : InstAlias<"cntlzw. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>; 3981// The POWER variant 3982def : MnemonicAlias<"cntlz", "cntlzw">; 3983def : MnemonicAlias<"cntlz.", "cntlzw.">; 3984 3985def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", 3986 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3987def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", 3988 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3989def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", 3990 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3991def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", 3992 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3993def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", 3994 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3995def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", 3996 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 3997def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", 3998 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 3999def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", 4000 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4001def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", 4002 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4003def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n", 4004 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4005def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", 4006 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4007def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n", 4008 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4009def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", 4010 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4011def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", 4012 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4013def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", 4014 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4015def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", 4016 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4017 4018def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4019def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4020def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4021def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4022def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4023def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4024 4025def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b", 4026 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4027def RLWINMobm : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b", 4028 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4029def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b", 4030 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4031def RLWIMIobm : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b", 4032 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4033def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b", 4034 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4035def RLWNMobm : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b", 4036 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4037 4038// These generic branch instruction forms are used for the assembler parser only. 4039// Defs and Uses are conservative, since we don't know the BO value. 4040let PPC970_Unit = 7 in { 4041 let Defs = [CTR], Uses = [CTR, RM] in { 4042 def gBC : BForm_3<16, 0, 0, (outs), 4043 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 4044 "bc $bo, $bi, $dst">; 4045 def gBCA : BForm_3<16, 1, 0, (outs), 4046 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 4047 "bca $bo, $bi, $dst">; 4048 } 4049 let Defs = [LR, CTR], Uses = [CTR, RM] in { 4050 def gBCL : BForm_3<16, 0, 1, (outs), 4051 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 4052 "bcl $bo, $bi, $dst">; 4053 def gBCLA : BForm_3<16, 1, 1, (outs), 4054 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 4055 "bcla $bo, $bi, $dst">; 4056 } 4057 let Defs = [CTR], Uses = [CTR, LR, RM] in 4058 def gBCLR : XLForm_2<19, 16, 0, (outs), 4059 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4060 "bclr $bo, $bi, $bh", IIC_BrB, []>; 4061 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4062 def gBCLRL : XLForm_2<19, 16, 1, (outs), 4063 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4064 "bclrl $bo, $bi, $bh", IIC_BrB, []>; 4065 let Defs = [CTR], Uses = [CTR, LR, RM] in 4066 def gBCCTR : XLForm_2<19, 528, 0, (outs), 4067 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4068 "bcctr $bo, $bi, $bh", IIC_BrB, []>; 4069 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4070 def gBCCTRL : XLForm_2<19, 528, 1, (outs), 4071 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 4072 "bcctrl $bo, $bi, $bh", IIC_BrB, []>; 4073} 4074def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; 4075def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; 4076def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; 4077def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; 4078 4079multiclass BranchSimpleMnemonic1<string name, string pm, int bo> { 4080 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>; 4081 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4082 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>; 4083 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>; 4084 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4085 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>; 4086} 4087multiclass BranchSimpleMnemonic2<string name, string pm, int bo> 4088 : BranchSimpleMnemonic1<name, pm, bo> { 4089 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>; 4090 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>; 4091} 4092defm : BranchSimpleMnemonic2<"t", "", 12>; 4093defm : BranchSimpleMnemonic2<"f", "", 4>; 4094defm : BranchSimpleMnemonic2<"t", "-", 14>; 4095defm : BranchSimpleMnemonic2<"f", "-", 6>; 4096defm : BranchSimpleMnemonic2<"t", "+", 15>; 4097defm : BranchSimpleMnemonic2<"f", "+", 7>; 4098defm : BranchSimpleMnemonic1<"dnzt", "", 8>; 4099defm : BranchSimpleMnemonic1<"dnzf", "", 0>; 4100defm : BranchSimpleMnemonic1<"dzt", "", 10>; 4101defm : BranchSimpleMnemonic1<"dzf", "", 2>; 4102 4103multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> { 4104 def : InstAlias<"b"#name#pm#" $cc, $dst", 4105 (BCC bibo, crrc:$cc, condbrtarget:$dst)>; 4106 def : InstAlias<"b"#name#pm#" $dst", 4107 (BCC bibo, CR0, condbrtarget:$dst)>; 4108 4109 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst", 4110 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4111 def : InstAlias<"b"#name#"a"#pm#" $dst", 4112 (BCCA bibo, CR0, abscondbrtarget:$dst)>; 4113 4114 def : InstAlias<"b"#name#"lr"#pm#" $cc", 4115 (BCCLR bibo, crrc:$cc)>; 4116 def : InstAlias<"b"#name#"lr"#pm, 4117 (BCCLR bibo, CR0)>; 4118 4119 def : InstAlias<"b"#name#"ctr"#pm#" $cc", 4120 (BCCCTR bibo, crrc:$cc)>; 4121 def : InstAlias<"b"#name#"ctr"#pm, 4122 (BCCCTR bibo, CR0)>; 4123 4124 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst", 4125 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>; 4126 def : InstAlias<"b"#name#"l"#pm#" $dst", 4127 (BCCL bibo, CR0, condbrtarget:$dst)>; 4128 4129 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst", 4130 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4131 def : InstAlias<"b"#name#"la"#pm#" $dst", 4132 (BCCLA bibo, CR0, abscondbrtarget:$dst)>; 4133 4134 def : InstAlias<"b"#name#"lrl"#pm#" $cc", 4135 (BCCLRL bibo, crrc:$cc)>; 4136 def : InstAlias<"b"#name#"lrl"#pm, 4137 (BCCLRL bibo, CR0)>; 4138 4139 def : InstAlias<"b"#name#"ctrl"#pm#" $cc", 4140 (BCCCTRL bibo, crrc:$cc)>; 4141 def : InstAlias<"b"#name#"ctrl"#pm, 4142 (BCCCTRL bibo, CR0)>; 4143} 4144multiclass BranchExtendedMnemonic<string name, int bibo> { 4145 defm : BranchExtendedMnemonicPM<name, "", bibo>; 4146 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>; 4147 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>; 4148} 4149defm : BranchExtendedMnemonic<"lt", 12>; 4150defm : BranchExtendedMnemonic<"gt", 44>; 4151defm : BranchExtendedMnemonic<"eq", 76>; 4152defm : BranchExtendedMnemonic<"un", 108>; 4153defm : BranchExtendedMnemonic<"so", 108>; 4154defm : BranchExtendedMnemonic<"ge", 4>; 4155defm : BranchExtendedMnemonic<"nl", 4>; 4156defm : BranchExtendedMnemonic<"le", 36>; 4157defm : BranchExtendedMnemonic<"ng", 36>; 4158defm : BranchExtendedMnemonic<"ne", 68>; 4159defm : BranchExtendedMnemonic<"nu", 100>; 4160defm : BranchExtendedMnemonic<"ns", 100>; 4161 4162def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; 4163def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; 4164def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; 4165def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; 4166def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>; 4167def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; 4168def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>; 4169def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; 4170 4171def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>; 4172def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>; 4173def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>; 4174def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>; 4175def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>; 4176def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 4177def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>; 4178def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 4179 4180multiclass TrapExtendedMnemonic<string name, int to> { 4181 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>; 4182 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>; 4183 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>; 4184 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>; 4185} 4186defm : TrapExtendedMnemonic<"lt", 16>; 4187defm : TrapExtendedMnemonic<"le", 20>; 4188defm : TrapExtendedMnemonic<"eq", 4>; 4189defm : TrapExtendedMnemonic<"ge", 12>; 4190defm : TrapExtendedMnemonic<"gt", 8>; 4191defm : TrapExtendedMnemonic<"nl", 12>; 4192defm : TrapExtendedMnemonic<"ne", 24>; 4193defm : TrapExtendedMnemonic<"ng", 20>; 4194defm : TrapExtendedMnemonic<"llt", 2>; 4195defm : TrapExtendedMnemonic<"lle", 6>; 4196defm : TrapExtendedMnemonic<"lge", 5>; 4197defm : TrapExtendedMnemonic<"lgt", 1>; 4198defm : TrapExtendedMnemonic<"lnl", 5>; 4199defm : TrapExtendedMnemonic<"lng", 6>; 4200defm : TrapExtendedMnemonic<"u", 31>; 4201 4202// Atomic loads 4203def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>; 4204def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>; 4205def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>; 4206def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>; 4207def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>; 4208def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>; 4209 4210// Atomic stores 4211def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>; 4212def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>; 4213def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>; 4214def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>; 4215def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>; 4216def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>; 4217 4218let Predicates = [IsISA3_0] in { 4219 4220// Copy-Paste Facility 4221// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to 4222// PASTE for naming consistency. 4223let mayLoad = 1 in 4224def CP_COPY : X_L1_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>; 4225 4226let mayStore = 1 in 4227def CP_PASTE : X_L1_RA5_RB5<31, 902, "paste" , gprc, IIC_LdStPASTE, []>; 4228 4229let mayStore = 1, Defs = [CR0] in 4230def CP_PASTEo : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isDOT; 4231 4232def CP_COPYx : PPCAsmPseudo<"copy $rA, $rB" , (ins gprc:$rA, gprc:$rB)>; 4233def CP_PASTEx : PPCAsmPseudo<"paste $rA, $rB", (ins gprc:$rA, gprc:$rB)>; 4234def CP_COPY_FIRST : PPCAsmPseudo<"copy_first $rA, $rB", 4235 (ins gprc:$rA, gprc:$rB)>; 4236def CP_PASTE_LAST : PPCAsmPseudo<"paste_last $rA, $rB", 4237 (ins gprc:$rA, gprc:$rB)>; 4238def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cp_abort", IIC_SprABORT, []>; 4239 4240// Message Synchronize 4241def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>; 4242 4243// Power-Saving Mode Instruction: 4244def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>; 4245 4246} // IsISA3_0 4247