| /external/spirv-llvm/lib/SPIRV/libSPIRV/ |
| D | OpenCL.std.h | 201 Clz = 151, enumerator
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| D | SPIRVExtInst.h | 212 add(OpenCLLIB::Clz, "clz"); in init()
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| /external/v8/src/compiler/ |
| D | machine-operator.h | 669 V(Word, Clz) \ in NON_EXPORTED_BASE()
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| /external/vixl/test/aarch32/ |
| D | test-macro-assembler-cond-rd-rn-a32.cc | 56 M(Clz) \
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| D | test-macro-assembler-cond-rd-rn-t32.cc | 56 M(Clz) \
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| D | test-simulator-cond-rd-rn-t32.cc | 118 M(Clz) \
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| D | test-simulator-cond-rd-rn-a32.cc | 118 M(Clz) \
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| D | test-disasm-a32.cc | 2346 MUST_FAIL_TEST_BOTH(Clz(pc, r0), "Unpredictable instruction.\n"); in TEST()
2347 MUST_FAIL_TEST_BOTH(Clz(r0, pc), "Unpredictable instruction.\n"); in TEST()
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| D | test-assembler-aarch32.cc | 2672 __ Clz(r0, r0); in TEST_T32() local
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| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 1259 __ Clz(i.OutputRegister64(), i.InputRegister64(0)); in AssembleArchInstruction() local
1262 __ Clz(i.OutputRegister32(), i.InputRegister32(0)); in AssembleArchInstruction() local
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| /external/v8/src/arm64/ |
| D | macro-assembler-arm64-inl.h | 438 void MacroAssembler::Clz(const Register& rd, const Register& rn) { in Clz() function
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| D | macro-assembler-arm64.h | 369 inline void Clz(const Register& rd, const Register& rn);
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| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 5855 COMPARE_MACRO(Clz(v1.V8B(), v8.V8B()), in TEST()
5858 COMPARE_MACRO(Clz(v2.V16B(), v9.V16B()), in TEST()
5861 COMPARE_MACRO(Clz(v3.V4H(), v1.V4H()), in TEST()
5864 COMPARE_MACRO(Clz(v4.V8H(), v2.V8H()), in TEST()
5867 COMPARE_MACRO(Clz(v5.V2S(), v3.V2S()), in TEST()
5870 COMPARE_MACRO(Clz(v6.V4S(), v4.V4S()), in TEST()
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| D | test-assembler-aarch64.cc | 1654 __ Clz(w0, w24); in TEST() local
1655 __ Clz(x1, x24); in TEST() local
1656 __ Clz(w2, w25); in TEST() local
1657 __ Clz(x3, x25); in TEST() local
1658 __ Clz(w4, w26); in TEST() local
1659 __ Clz(x5, x26); in TEST() local
19387 __ Clz(v22.V8B(), v0.V8B()); in TEST() local
19388 __ Clz(v23.V16B(), v0.V16B()); in TEST() local
19389 __ Clz(v24.V4H(), v0.V4H()); in TEST() local
19390 __ Clz(v25.V8H(), v0.V8H()); in TEST() local
[all …]
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 1062 void Clz(const Register& rd, const Register& rn) { in Clz() function
2266 V(clz, Clz) \
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| /external/v8/src/mips/ |
| D | macro-assembler-mips.h | 319 void Clz(Register rd, Register rs);
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| /external/v8/src/mips64/ |
| D | macro-assembler-mips64.h | 351 void Clz(Register rd, Register rs);
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| /external/v8/src/compiler/mips/ |
| D | code-generator-mips.cc | 895 __ Clz(i.OutputRegister(), i.InputRegister(0)); in AssembleArchInstruction() local
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| /external/v8/src/compiler/mips64/ |
| D | code-generator-mips64.cc | 993 __ Clz(i.OutputRegister(), i.InputRegister(0)); in AssembleArchInstruction() local
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 1246 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); in LowerSETCC() local
1247 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, in LowerSETCC()
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 1605 void Clz(Condition cond, Register rd, Register rm) { in Clz() function
1614 void Clz(Register rd, Register rm) { Clz(al, rd, rm); } in Clz() function
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| /external/v8/src/crankshaft/mips/ |
| D | lithium-codegen-mips.cc | 3456 __ Clz(result, input); in DoMathClz32() local
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| /external/v8/src/crankshaft/arm64/ |
| D | lithium-codegen-arm64.cc | 3633 __ Clz(result, input); in DoMathClz32() local
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| /external/v8/src/crankshaft/mips64/ |
| D | lithium-codegen-mips64.cc | 3663 __ Clz(result, input); in DoMathClz32() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 2375 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); in LowerSETCC() local
2376 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, in LowerSETCC()
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