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Searched refs:CondCodes (Results 1 – 25 of 72) sorted by relevance

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/external/llvm/lib/Target/AVR/
DAVRInstrInfo.h32 enum CondCodes { enum
70 const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
71 AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
72 AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
DAVRInstrInfo.cpp172 const MCInstrDesc &AVRInstrInfo::getBrCond(AVRCC::CondCodes CC) const { in getBrCond()
195 AVRCC::CondCodes AVRInstrInfo::getCondFromBranchOpc(unsigned Opc) const { in getCondFromBranchOpc()
218 AVRCC::CondCodes AVRInstrInfo::getOppositeCondition(AVRCC::CondCodes CC) const { in getOppositeCondition()
302 AVRCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode()); in analyzeBranch()
364 AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm(); in analyzeBranch()
394 AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm(); in InsertBranch()
436 AVRCC::CondCodes CC = static_cast<AVRCC::CondCodes>(Cond[0].getImm()); in ReverseBranchCondition()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DThumb2ITBlockPass.cpp44 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
108 ARMCC::CondCodes CC, ARMCC::CondCodes OCC, in MoveCopyOutOfITBlock()
156 ARMCC::CondCodes NCC = llvm::getITInstrPredicate(I, NPredReg); in MoveCopyOutOfITBlock()
173 ARMCC::CondCodes CC = llvm::getITInstrPredicate(MI, PredReg); in InsertITInstructions()
196 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); in InsertITInstructions()
209 ARMCC::CondCodes NCC = llvm::getITInstrPredicate(NMI, NPredReg); in InsertITInstructions()
DARMBaseInstrInfo.h77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const { in getPredicate()
79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm() in getPredicate()
338 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
354 ARMCC::CondCodes Pred, unsigned PredReg,
360 ARMCC::CondCodes Pred, unsigned PredReg,
DARMLoadStoreOptimizer.cpp92 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
103 ARMCC::CondCodes Pred,
110 ARMCC::CondCodes Pred, unsigned PredReg,
292 int Opcode, ARMCC::CondCodes Pred, in MergeOps()
373 ARMCC::CondCodes Pred, unsigned PredReg, in MergeOpsUpdate()
440 ARMCC::CondCodes Pred, unsigned PredReg, in MergeLDR_STR()
511 ARMCC::CondCodes Pred, unsigned PredReg){ in isMatchingDecrement()
534 ARMCC::CondCodes Pred, unsigned PredReg){ in isMatchingIncrement()
689 ARMCC::CondCodes Pred = llvm::getInstrPredicate(MI, PredReg); in MergeBaseUpdateLSMultiple()
844 ARMCC::CondCodes Pred = llvm::getInstrPredicate(MI, PredReg); in MergeBaseUpdateLoadStore()
[all …]
DThumb2InstrInfo.cpp56 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg); in ReplaceTailWithBranchTo()
177 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate()
573 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg); in scheduleTwoAddrSource()
580 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); in scheduleTwoAddrSource()
589 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg); in scheduleTwoAddrSource()
605 ARMCC::CondCodes
DThumb2RegisterInfo.h37 ARMCC::CondCodes Pred = ARMCC::AL,
/external/llvm/lib/Target/ARM/
DThumb2ITBlockPass.cpp50 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
125 ARMCC::CondCodes CC, ARMCC::CondCodes OCC, in MoveCopyOutOfITBlock()
173 ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg); in MoveCopyOutOfITBlock()
190 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); in InsertITInstructions()
213 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); in InsertITInstructions()
230 ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg); in InsertITInstructions()
DARMBaseInstrInfo.h138 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const { in getPredicate()
140 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm() in getPredicate()
454 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
476 ARMCC::CondCodes Pred, unsigned PredReg,
483 ARMCC::CondCodes Pred, unsigned PredReg,
DARMLoadStoreOptimizer.cpp150 ARMCC::CondCodes Pred, unsigned PredReg);
154 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
159 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
459 ARMCC::CondCodes Pred, in UpdateBaseRegUses()
596 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreMulti()
793 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreDouble()
861 ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg); in MergeOpsUpdate()
1127 ARMCC::CondCodes Pred, unsigned PredReg) { in isIncrementOrDecrement()
1157 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { in findIncDecBefore()
1177 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { in findIncDecAfter()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZInstrInfo.h98 SystemZCC::CondCodes getOppositeCondition(SystemZCC::CondCodes CC) const;
99 SystemZCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
100 const MCInstrDesc& getBrCond(SystemZCC::CondCodes CC) const;
DSystemZInstrInfo.cpp200 SystemZCC::CondCodes CC = static_cast<SystemZCC::CondCodes>(Cond[0].getImm()); in ReverseBranchCondition()
266 SystemZCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode()); in AnalyzeBranch()
288 SystemZCC::CondCodes OldBranchCode = (SystemZCC::CondCodes)Cond[0].getImm(); in AnalyzeBranch()
338 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)Cond[0].getImm(); in InsertBranch()
351 SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const { in getBrCond()
372 SystemZCC::CondCodes
393 SystemZCC::CondCodes
394 SystemZInstrInfo::getOppositeCondition(SystemZCC::CondCodes CC) const { in getOppositeCondition()
DSystemZ.h29 enum CondCodes { enum
/external/mesa3d/src/mesa/program/
Dprog_execute.c460 if (test_cc(machine->CondCodes[GET_SWZ(swizzle, 0)], condMask) || in eval_condition()
461 test_cc(machine->CondCodes[GET_SWZ(swizzle, 1)], condMask) || in eval_condition()
462 test_cc(machine->CondCodes[GET_SWZ(swizzle, 2)], condMask) || in eval_condition()
463 test_cc(machine->CondCodes[GET_SWZ(swizzle, 3)], condMask)) { in eval_condition()
506 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 0)], in store_vector4()
511 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 1)], in store_vector4()
516 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 2)], in store_vector4()
521 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 3)], in store_vector4()
545 machine->CondCodes[0] = generate_cc(value[0]); in store_vector4()
547 machine->CondCodes[1] = generate_cc(value[1]); in store_vector4()
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/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp133 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in ReverseBranchCondition()
229 MSP430CC::CondCodes BranchCode = in analyzeBranch()
230 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm()); in analyzeBranch()
252 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in analyzeBranch()
DMSP430.h23 enum CondCodes { enum
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
DMSP430InstrInfo.cpp133 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in ReverseBranchCondition()
231 MSP430CC::CondCodes BranchCode = in AnalyzeBranch()
232 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm()); in AnalyzeBranch()
254 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in AnalyzeBranch()
DMSP430.h23 enum CondCodes { enum
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMBaseInfo.h29 enum CondCodes { // Meaning (integer) Meaning (floating-point) enum
47 inline static CondCodes getOppositeCondition(CondCodes CC) { in getOppositeCondition()
68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { in ARMCondCodeToString()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMBaseInfo.h29 enum CondCodes { // Meaning (integer) Meaning (floating-point) enum
47 inline static CondCodes getOppositeCondition(CondCodes CC) { in getOppositeCondition()
68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { in ARMCondCodeToString()
/external/mesa3d/src/mesa/swrast/
Ds_fragprog.c198 machine->CondCodes[0] = COND_EQ; in init_machine()
199 machine->CondCodes[1] = COND_EQ; in init_machine()
200 machine->CondCodes[2] = COND_EQ; in init_machine()
201 machine->CondCodes[3] = COND_EQ; in init_machine()
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparc.h38 enum CondCodes { enum
75 inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) { in SPARCCondCodeToString()
DSparcInstrInfo.cpp79 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) in GetOppositeBranchCondition()
170 SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm(); in AnalyzeBranch()
/external/llvm/lib/Target/Sparc/
DSparc.h42 enum CondCodes { enum
96 inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) { in SPARCCondCodeToString()
/external/mesa3d/src/mesa/tnl/
Dt_vb_program.c252 machine->CondCodes[0] = COND_EQ; in init_machine()
253 machine->CondCodes[1] = COND_EQ; in init_machine()
254 machine->CondCodes[2] = COND_EQ; in init_machine()
255 machine->CondCodes[3] = COND_EQ; in init_machine()

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