1 //===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
16
17 #include "ARM.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/SmallSet.h"
22
23 #define GET_INSTRINFO_HEADER
24 #include "ARMGenInstrInfo.inc"
25
26 namespace llvm {
27 class ARMSubtarget;
28 class ARMBaseRegisterInfo;
29
30 class ARMBaseInstrInfo : public ARMGenInstrInfo {
31 const ARMSubtarget &Subtarget;
32
33 protected:
34 // Can be only subclassed.
35 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
36
37 public:
38 // Return the non-pre/post incrementing version of 'Opc'. Return 0
39 // if there is not such an opcode.
40 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
41
42 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
43 MachineBasicBlock::iterator &MBBI,
44 LiveVariables *LV) const;
45
46 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
getSubtarget()47 const ARMSubtarget &getSubtarget() const { return Subtarget; }
48
49 ScheduleHazardRecognizer *
50 CreateTargetHazardRecognizer(const TargetMachine *TM,
51 const ScheduleDAG *DAG) const;
52
53 ScheduleHazardRecognizer *
54 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
55 const ScheduleDAG *DAG) const;
56
57 // Branch analysis.
58 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
59 MachineBasicBlock *&FBB,
60 SmallVectorImpl<MachineOperand> &Cond,
61 bool AllowModify = false) const;
62 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
63 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
64 MachineBasicBlock *FBB,
65 const SmallVectorImpl<MachineOperand> &Cond,
66 DebugLoc DL) const;
67
68 virtual
69 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
70
71 // Predication support.
isPredicated(const MachineInstr * MI)72 bool isPredicated(const MachineInstr *MI) const {
73 int PIdx = MI->findFirstPredOperandIdx();
74 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
75 }
76
getPredicate(const MachineInstr * MI)77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
78 int PIdx = MI->findFirstPredOperandIdx();
79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
80 : ARMCC::AL;
81 }
82
83 virtual
84 bool PredicateInstruction(MachineInstr *MI,
85 const SmallVectorImpl<MachineOperand> &Pred) const;
86
87 virtual
88 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
89 const SmallVectorImpl<MachineOperand> &Pred2) const;
90
91 virtual bool DefinesPredicate(MachineInstr *MI,
92 std::vector<MachineOperand> &Pred) const;
93
94 virtual bool isPredicable(MachineInstr *MI) const;
95
96 /// GetInstSize - Returns the size of the specified MachineInstr.
97 ///
98 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
99
100 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
101 int &FrameIndex) const;
102 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
103 int &FrameIndex) const;
104 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
105 int &FrameIndex) const;
106 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
107 int &FrameIndex) const;
108
109 virtual void copyPhysReg(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator I, DebugLoc DL,
111 unsigned DestReg, unsigned SrcReg,
112 bool KillSrc) const;
113
114 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
115 MachineBasicBlock::iterator MBBI,
116 unsigned SrcReg, bool isKill, int FrameIndex,
117 const TargetRegisterClass *RC,
118 const TargetRegisterInfo *TRI) const;
119
120 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
121 MachineBasicBlock::iterator MBBI,
122 unsigned DestReg, int FrameIndex,
123 const TargetRegisterClass *RC,
124 const TargetRegisterInfo *TRI) const;
125
126 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
127
128 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
129 int FrameIx,
130 uint64_t Offset,
131 const MDNode *MDPtr,
132 DebugLoc DL) const;
133
134 virtual void reMaterialize(MachineBasicBlock &MBB,
135 MachineBasicBlock::iterator MI,
136 unsigned DestReg, unsigned SubIdx,
137 const MachineInstr *Orig,
138 const TargetRegisterInfo &TRI) const;
139
140 MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
141
142 virtual bool produceSameValue(const MachineInstr *MI0,
143 const MachineInstr *MI1,
144 const MachineRegisterInfo *MRI) const;
145
146 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
147 /// determine if two loads are loading from the same base address. It should
148 /// only return true if the base pointers are the same and the only
149 /// differences between the two addresses is the offset. It also returns the
150 /// offsets by reference.
151 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
152 int64_t &Offset1, int64_t &Offset2)const;
153
154 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
155 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
156 /// should be scheduled togther. On some targets if two loads are loading from
157 /// addresses in the same cache line, it's better if they are scheduled
158 /// together. This function takes two integers that represent the load offsets
159 /// from the common base address. It returns true if it decides it's desirable
160 /// to schedule the two loads together. "NumLoads" is the number of loads that
161 /// have already been scheduled after Load1.
162 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
163 int64_t Offset1, int64_t Offset2,
164 unsigned NumLoads) const;
165
166 virtual bool isSchedulingBoundary(const MachineInstr *MI,
167 const MachineBasicBlock *MBB,
168 const MachineFunction &MF) const;
169
170 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
171 unsigned NumCycles, unsigned ExtraPredCycles,
172 const BranchProbability &Probability) const;
173
174 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
175 unsigned NumT, unsigned ExtraT,
176 MachineBasicBlock &FMBB,
177 unsigned NumF, unsigned ExtraF,
178 const BranchProbability &Probability) const;
179
isProfitableToDupForIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,const BranchProbability & Probability)180 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
181 unsigned NumCycles,
182 const BranchProbability
183 &Probability) const {
184 return NumCycles == 1;
185 }
186
187 /// AnalyzeCompare - For a comparison instruction, return the source register
188 /// in SrcReg and the value it compares against in CmpValue. Return true if
189 /// the comparison instruction can be analyzed.
190 virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
191 int &CmpMask, int &CmpValue) const;
192
193 /// OptimizeCompareInstr - Convert the instruction to set the zero flag so
194 /// that we can remove a "comparison with zero".
195 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
196 int CmpMask, int CmpValue,
197 const MachineRegisterInfo *MRI) const;
198
199 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
200 /// instruction, try to fold the immediate into the use instruction.
201 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
202 unsigned Reg, MachineRegisterInfo *MRI) const;
203
204 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
205 const MachineInstr *MI) const;
206
207 virtual
208 int getOperandLatency(const InstrItineraryData *ItinData,
209 const MachineInstr *DefMI, unsigned DefIdx,
210 const MachineInstr *UseMI, unsigned UseIdx) const;
211 virtual
212 int getOperandLatency(const InstrItineraryData *ItinData,
213 SDNode *DefNode, unsigned DefIdx,
214 SDNode *UseNode, unsigned UseIdx) const;
215
216 /// VFP/NEON execution domains.
217 std::pair<uint16_t, uint16_t>
218 getExecutionDomain(const MachineInstr *MI) const;
219 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
220
221 private:
222 int getVLDMDefCycle(const InstrItineraryData *ItinData,
223 const MCInstrDesc &DefMCID,
224 unsigned DefClass,
225 unsigned DefIdx, unsigned DefAlign) const;
226 int getLDMDefCycle(const InstrItineraryData *ItinData,
227 const MCInstrDesc &DefMCID,
228 unsigned DefClass,
229 unsigned DefIdx, unsigned DefAlign) const;
230 int getVSTMUseCycle(const InstrItineraryData *ItinData,
231 const MCInstrDesc &UseMCID,
232 unsigned UseClass,
233 unsigned UseIdx, unsigned UseAlign) const;
234 int getSTMUseCycle(const InstrItineraryData *ItinData,
235 const MCInstrDesc &UseMCID,
236 unsigned UseClass,
237 unsigned UseIdx, unsigned UseAlign) const;
238 int getOperandLatency(const InstrItineraryData *ItinData,
239 const MCInstrDesc &DefMCID,
240 unsigned DefIdx, unsigned DefAlign,
241 const MCInstrDesc &UseMCID,
242 unsigned UseIdx, unsigned UseAlign) const;
243
244 int getInstrLatency(const InstrItineraryData *ItinData,
245 const MachineInstr *MI, unsigned *PredCost = 0) const;
246
247 int getInstrLatency(const InstrItineraryData *ItinData,
248 SDNode *Node) const;
249
250 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
251 const MachineRegisterInfo *MRI,
252 const MachineInstr *DefMI, unsigned DefIdx,
253 const MachineInstr *UseMI, unsigned UseIdx) const;
254 bool hasLowDefLatency(const InstrItineraryData *ItinData,
255 const MachineInstr *DefMI, unsigned DefIdx) const;
256
257 /// verifyInstruction - Perform target specific instruction verification.
258 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const;
259
260 private:
261 /// Modeling special VFP / NEON fp MLA / MLS hazards.
262
263 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
264 /// MLx table.
265 DenseMap<unsigned, unsigned> MLxEntryMap;
266
267 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
268 /// stalls when scheduled together with fp MLA / MLS opcodes.
269 SmallSet<unsigned, 16> MLxHazardOpcodes;
270
271 public:
272 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
273 /// instruction.
isFpMLxInstruction(unsigned Opcode)274 bool isFpMLxInstruction(unsigned Opcode) const {
275 return MLxEntryMap.count(Opcode);
276 }
277
278 /// isFpMLxInstruction - This version also returns the multiply opcode and the
279 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
280 /// the MLX instructions with an extra lane operand.
281 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
282 unsigned &AddSubOpc, bool &NegAcc,
283 bool &HasLane) const;
284
285 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
286 /// will cause stalls when scheduled after (within 4-cycle window) a fp
287 /// MLA / MLS instruction.
canCauseFpMLxStall(unsigned Opcode)288 bool canCauseFpMLxStall(unsigned Opcode) const {
289 return MLxHazardOpcodes.count(Opcode);
290 }
291 };
292
293 static inline
AddDefaultPred(const MachineInstrBuilder & MIB)294 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
295 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
296 }
297
298 static inline
AddDefaultCC(const MachineInstrBuilder & MIB)299 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
300 return MIB.addReg(0);
301 }
302
303 static inline
304 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
305 bool isDead = false) {
306 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
307 }
308
309 static inline
AddNoT1CC(const MachineInstrBuilder & MIB)310 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
311 return MIB.addReg(0);
312 }
313
314 static inline
isUncondBranchOpcode(int Opc)315 bool isUncondBranchOpcode(int Opc) {
316 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
317 }
318
319 static inline
isCondBranchOpcode(int Opc)320 bool isCondBranchOpcode(int Opc) {
321 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
322 }
323
324 static inline
isJumpTableBranchOpcode(int Opc)325 bool isJumpTableBranchOpcode(int Opc) {
326 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
327 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
328 }
329
330 static inline
isIndirectBranchOpcode(int Opc)331 bool isIndirectBranchOpcode(int Opc) {
332 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
333 }
334
335 /// getInstrPredicate - If instruction is predicated, returns its predicate
336 /// condition, otherwise returns AL. It also returns the condition code
337 /// register by reference.
338 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
339
340 int getMatchingCondBranchOpcode(int Opc);
341
342
343 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
344 /// the instruction is encoded with an 'S' bit is determined by the optional
345 /// CPSR def operand.
346 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
347
348 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
349 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
350 /// code.
351 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
352 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
353 unsigned DestReg, unsigned BaseReg, int NumBytes,
354 ARMCC::CondCodes Pred, unsigned PredReg,
355 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
356
357 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
358 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
359 unsigned DestReg, unsigned BaseReg, int NumBytes,
360 ARMCC::CondCodes Pred, unsigned PredReg,
361 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
362 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
363 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
364 unsigned DestReg, unsigned BaseReg,
365 int NumBytes, const TargetInstrInfo &TII,
366 const ARMBaseRegisterInfo& MRI,
367 unsigned MIFlags = 0);
368
369
370 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
371 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
372 /// offset could not be handled directly in MI, and return the left-over
373 /// portion by reference.
374 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
375 unsigned FrameReg, int &Offset,
376 const ARMBaseInstrInfo &TII);
377
378 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
379 unsigned FrameReg, int &Offset,
380 const ARMBaseInstrInfo &TII);
381
382 } // End llvm namespace
383
384 #endif
385