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Searched refs:DefIdx (Results 1 – 25 of 52) sorted by relevance

123

/external/llvm/include/llvm/MC/
DMCInstrItineraries.h186 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding() argument
190 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
192 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
200 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
207 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency() argument
212 int DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
222 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
DMCSubtargetInfo.h129 unsigned DefIdx) const { in getWriteLatencyEntry() argument
130 assert(DefIdx < SC->NumWriteLatencyEntries && in getWriteLatencyEntry()
133 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; in getWriteLatencyEntry()
/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCInstrItineraries.h199 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding() argument
203 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
205 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
213 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
220 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency() argument
225 int DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
235 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
/external/llvm/lib/CodeGen/
DTargetSchedule.cpp128 unsigned DefIdx = 0; in findDefIdx() local
132 ++DefIdx; in findDefIdx()
134 return DefIdx; in findDefIdx()
188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
189 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency()
192 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
214 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " in computeOperandLatency()
228 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
229 DefIdx != DefEnd; ++DefIdx) { in computeInstrLatency()
232 STI->getWriteLatencyEntry(&SCDesc, DefIdx); in computeInstrLatency()
DPeepholeOptimizer.cpp296 unsigned DefIdx; member in __anon2734e12b0111::ValueTracker
354 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg), in ValueTracker()
358 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
369 ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg, in ValueTracker() argument
373 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg), in ValueTracker()
375 assert(DefIdx < Def->getDesc().getNumDefs() && in ValueTracker()
376 Def->getOperand(DefIdx).isReg() && "Invalid definition"); in ValueTracker()
377 Reg = Def->getOperand(DefIdx).getReg(); in ValueTracker()
1672 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromCopy()
1691 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromBitcast()
[all …]
DTargetInstrInfo.cpp982 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
992 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
994 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1056 unsigned DefIdx) const { in hasLowDefLatency()
1062 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1070 unsigned DefIdx, in getOperandLatency() argument
1075 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1096 unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const { in computeOperandLatency() argument
1106 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, *UseMI, UseIdx); in computeOperandLatency()
1109 OperLatency = ItinData->getOperandCycle(DefClass, DefIdx); in computeOperandLatency()
[all …]
DLiveRangeCalc.cpp46 SlotIndex DefIdx = in createDeadDef() local
50 LR.createDeadDef(DefIdx, Alloc); in createDeadDef()
195 unsigned DefIdx; in extendToUses() local
198 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) { in extendToUses()
201 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber(); in extendToUses()
DMachineVerifier.cpp233 SlotIndex DefIdx, const LiveRange &LR, unsigned Reg,
963 unsigned DefIdx; in visitMachineOperand() local
965 MI->isRegTiedToDefOperand(MONum, &DefIdx) && in visitMachineOperand()
966 Reg != MI->getOperand(DefIdx).getReg()) in visitMachineOperand()
1133 unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit, in checkLivenessAtDef() argument
1135 if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) { in checkLivenessAtDef()
1137 if (VNI->def != DefIdx) { in checkLivenessAtDef()
1144 report_context(DefIdx); in checkLivenessAtDef()
1152 report_context(DefIdx); in checkLivenessAtDef()
1156 LiveQueryResult LRQ = LR.Query(DefIdx); in checkLivenessAtDef()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/
DTargetInstrInfo.cpp66 const MachineInstr *DefMI, unsigned DefIdx, in getOperandLatency() argument
73 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
78 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
88 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
90 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
115 unsigned DefIdx) const { in hasLowDefLatency()
120 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.h55 const MachineInstr &MI, unsigned DefIdx,
68 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
84 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
282 const MachineInstr &DefMI, unsigned DefIdx,
286 SDNode *DefNode, unsigned DefIdx,
309 unsigned DefIdx, unsigned DefAlign) const;
313 unsigned DefIdx, unsigned DefAlign) const;
324 unsigned DefIdx, unsigned DefAlign,
329 const MachineInstr &DefMI, unsigned DefIdx,
346 const MachineInstr &DefMI, unsigned DefIdx,
[all …]
DARMBaseInstrInfo.cpp3187 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle() argument
3188 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getVLDMDefCycle()
3191 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3228 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle() argument
3229 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getLDMDefCycle()
3232 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
3331 unsigned DefIdx, unsigned DefAlign, in getOperandLatency() argument
3337 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
3338 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
3347 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMBaseInstrInfo.h209 const MachineInstr *DefMI, unsigned DefIdx,
213 SDNode *DefNode, unsigned DefIdx,
225 unsigned DefIdx, unsigned DefAlign) const;
229 unsigned DefIdx, unsigned DefAlign) const;
240 unsigned DefIdx, unsigned DefAlign,
252 const MachineInstr *DefMI, unsigned DefIdx,
255 const MachineInstr *DefMI, unsigned DefIdx) const;
DARMBaseInstrInfo.cpp2085 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle() argument
2086 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getVLDMDefCycle()
2089 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
2126 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle() argument
2127 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getLDMDefCycle()
2130 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
2229 unsigned DefIdx, unsigned DefAlign, in getOperandLatency() argument
2235 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
2236 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
2245 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
[all …]
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h391 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
409 getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
429 getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
934 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs() argument
948 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregLikeInputs() argument
962 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs() argument
1221 SDNode *DefNode, unsigned DefIdx,
1233 const MachineInstr &DefMI, unsigned DefIdx,
1249 const MachineInstr &DefMI, unsigned DefIdx,
1282 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h119 const MachineInstr &DefMI, unsigned DefIdx,
123 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
125 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
131 unsigned DefIdx) const override { in hasLowDefLatency() argument
DPPCVSXSwapRemoval.cpp617 int DefIdx = SwapMap[DefMI]; in formWebs() local
618 (void)EC->unionSets(SwapVector[DefIdx].VSEId, in formWebs()
621 DEBUG(dbgs() << format("Unioning %d with %d\n", SwapVector[DefIdx].VSEId, in formWebs()
696 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
698 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
699 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
705 DEBUG(dbgs() << " def " << DefIdx << ": "); in recordUnoptimizableWebs()
771 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
772 SwapVector[DefIdx].WillRemove = 1; in markSwapsForRemoval()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DLiveRangeEdit.cpp122 SlotIndex DefIdx; in canRematerializeAt() local
124 DefIdx = lis.getInstructionIndex(RM.OrigMI); in canRematerializeAt()
126 DefIdx = RM.ParentVNI->def; in canRematerializeAt()
127 RM.OrigMI = lis.getInstructionFromIndex(DefIdx); in canRematerializeAt()
136 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx, lis)) in canRematerializeAt()
DRegisterCoalescer.cpp659 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); in RemoveCopyByCommutingDef() local
660 assert(DefIdx != -1); in RemoveCopyByCommutingDef()
662 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) in RemoveCopyByCommutingDef()
768 SlotIndex DefIdx = UseIdx.getDefIndex(); in RemoveCopyByCommutingDef() local
769 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx); in RemoveCopyByCommutingDef()
772 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI); in RemoveCopyByCommutingDef()
773 assert(DVNI->def == DefIdx); in RemoveCopyByCommutingDef()
1016 SlotIndex DefIdx = LIS->getInstructionIndex(DefMI).getDefIndex(); in RemoveDeadDef() local
1017 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx); in RemoveDeadDef()
1018 if (DefIdx != MLR->valno->def) in RemoveDeadDef()
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DScheduleDAGInstrs.cpp600 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg); in ComputeOperandLatency() local
601 if (DefIdx != -1) { in ComputeOperandLatency()
602 const MachineOperand &MO = DefMI->getOperand(DefIdx); in ComputeOperandLatency()
604 DefIdx >= (int)DefMI->getDesc().getNumOperands()) { in ComputeOperandLatency()
611 DefIdx = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI); in ComputeOperandLatency()
625 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx, in ComputeOperandLatency()
634 Latency = InstrItins->getOperandCycle(DefClass, DefIdx); in ComputeOperandLatency()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp507 DefIdx = 0; in InitNodeNumDefs()
513 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) { in RegDefIter()
521 for (;DefIdx < NodeNumDefs; ++DefIdx) { in Advance()
522 if (!Node->hasAnyUseOfValue(DefIdx)) in Advance()
524 ValueType = Node->getValueType(DefIdx); in Advance()
525 ++DefIdx; in Advance()
587 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in ComputeOperandLatency() local
591 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in ComputeOperandLatency()
DScheduleDAGSDNodes.h125 unsigned DefIdx; variable
143 return DefIdx-1; in GetIdx()
/external/llvm/lib/MC/MCDisassembler/
DDisassembler.cpp203 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; in getLatency() local
204 DefIdx != DefEnd; ++DefIdx) { in getLatency()
207 DefIdx); in getLatency()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp554 DefIdx = 0; in InitNodeNumDefs()
560 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) { in RegDefIter()
568 for (;DefIdx < NodeNumDefs; ++DefIdx) { in Advance()
569 if (!Node->hasAnyUseOfValue(DefIdx)) in Advance()
571 ValueType = Node->getSimpleValueType(DefIdx); in Advance()
572 ++DefIdx; in Advance()
634 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() local
638 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()
DScheduleDAGSDNodes.h131 unsigned DefIdx; variable
149 return DefIdx-1; in GetIdx()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetInstrInfo.h644 const MachineInstr *DefMI, unsigned DefIdx,
648 SDNode *DefNode, unsigned DefIdx,
673 const MachineInstr *DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
682 const MachineInstr *DefMI, unsigned DefIdx) const;

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