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Searched refs:FP_EXTEND (Results 1 – 25 of 37) sorted by relevance

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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h416 FP_EXTEND, enumerator
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp84 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
85 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
89 ISD == ISD::FP_EXTEND)) { in getCastInstrCost()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h480 FP_EXTEND, enumerator
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp640 case ISD::FP_EXTEND: in isNegatibleForFree()
716 case ISD::FP_EXTEND: in GetNegatedExpression()
1418 case ISD::FP_EXTEND: return visitFP_EXTEND(N); in visit()
7819 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
7823 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7825 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7831 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
7835 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7837 DAG.getNode(ISD::FP_EXTEND, SL, VT, in visitFADDForFMACombine()
7873 DAG.getNode(ISD::FP_EXTEND, SL, VT, U), in visitFADDForFMACombine()
[all …]
DLegalizeFloatTypes.cpp94 case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break; in SoftenFloatResult()
460 Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op); in SoftenFloatRes_FP_EXTEND()
658 auto ExtendNode = DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL); in SoftenFloatRes_LOAD()
756 case ISD::FP_EXTEND: Res = SoftenFloatOp_FP_EXTEND(N); break; in SoftenFloatOperand()
1034 case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break; in ExpandFloatResult()
1271 Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0)); in ExpandFloatRes_FP_EXTEND()
1749 case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break; in PromoteFloatOperand()
1800 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Op); in PromoteFloatOp_FP_EXTEND()
2131 ISD::FP_EXTEND, DL, NVT, in PromoteFloatRes_XINT_TO_FP()
DLegalizeDAG.cpp2325 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); in ExpandLegalINT_TO_FP()
2890 case ISD::FP_EXTEND: in ExpandNode()
3176 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res)); in ExpandNode()
4122 ExtOp = ISD::FP_EXTEND; in PromoteNode()
4153 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4166 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4187 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
4188 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); in PromoteNode()
4196 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
4197 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); in PromoteNode()
[all …]
DLegalizeVectorOps.cpp325 case ISD::FP_EXTEND: in LegalizeOp()
416 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j)); in Promote()
DSelectionDAGDumper.cpp252 case ISD::FP_EXTEND: return "fp_extend"; in getOperationName()
DLegalizeVectorTypes.cpp88 case ISD::FP_EXTEND: in ScalarizeVectorResult()
646 case ISD::FP_EXTEND: in SplitVectorResult()
1501 case ISD::FP_EXTEND: in SplitVectorOperand()
2136 case ISD::FP_EXTEND: in WidenVectorResult()
3096 case ISD::FP_EXTEND: in WidenVectorOperand()
DSelectionDAG.cpp236 return IsFP ? ISD::FP_EXTEND : ISD::ANY_EXTEND; in getExtForLoadExtType()
2982 case ISD::FP_EXTEND: { in getNode()
3028 case ISD::FP_EXTEND: in getNode()
3055 case ISD::FP_EXTEND: in getNode()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp82 case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break; in SoftenFloatResult()
499 return BitConvertToInteger(DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL)); in SoftenFloatRes_LOAD()
865 case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break; in ExpandFloatResult()
1062 Hi = DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), NVT, N->getOperand(0)); in ExpandFloatRes_FP_EXTEND()
DLegalizeVectorTypes.cpp82 case ISD::FP_EXTEND: in ScalarizeVectorResult()
458 case ISD::FP_EXTEND: in SplitVectorResult()
984 case ISD::FP_EXTEND: in SplitVectorOperand()
1283 case ISD::FP_EXTEND: in WidenVectorResult()
2036 case ISD::FP_EXTEND: in WidenVectorOperand()
DLegalizeDAG.cpp513 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); in ExpandUnalignedLoad()
1360 ISD::FP_EXTEND : ISD::ANY_EXTEND); in LegalizeOp()
2510 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); in ExpandLegalINT_TO_FP()
3098 case ISD::FP_EXTEND: in ExpandNode()
3909 ExtOp = ISD::FP_EXTEND; in PromoteNode()
3941 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
DDAGCombiner.cpp411 case ISD::FP_EXTEND: in isNegatibleForFree()
481 case ISD::FP_EXTEND: in GetNegatedExpression()
1098 case ISD::FP_EXTEND: return visitFP_EXTEND(N); in visit()
5450 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) in visitFCOPYSIGN()
5542 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) in visitFP_ROUND()
5575 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); in visitFP_ROUND_INREG()
5593 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); in visitFP_EXTEND()
5604 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); in visitFP_EXTEND()
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp554 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, in getCastInstrCost()
555 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, in getCastInstrCost()
641 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, in getCastInstrCost()
719 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, in getCastInstrCost()
DX86ISelDAGToDAG.cpp591 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND) in PreprocessISelDAG()
612 if (N->getOpcode() == ISD::FP_EXTEND) in PreprocessISelDAG()
DX86IntrinsicsInfo.h549 ISD::FP_EXTEND, 0),
551 ISD::FP_EXTEND, X86ISD::VFPEXT),
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp163 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in AArch64TargetLowering()
303 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote); in AArch64TargetLowering()
309 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
369 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand); in AArch64TargetLowering()
547 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand); in AArch64TargetLowering()
1212 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS); in emitComparison()
1213 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS); in emitComparison()
1304 LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS); in emitConditionalComparison()
1305 RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS); in emitConditionalComparison()
1930 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0))); in LowerVectorFP_TO_INT()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelLowering.cpp3599 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
3607 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
3619 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
3625 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
3631 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
3637 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
3649 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); in LowerFP_TO_INT()
5239 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); in PerformDAGCombine()
5269 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); in PerformDAGCombine()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp706 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal); in PPCTargetLowering()
6309 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
6312 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
6321 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
6329 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
6342 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6345 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
6352 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6358 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
6364 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp193 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand); in InitAMDILLowering()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelDAGToDAG.cpp474 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND) in PreprocessISelDAG()
493 if (N->getOpcode() == ISD::FP_EXTEND) in PreprocessISelDAG()
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaISelLowering.cpp634 src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, src); in LowerOperation()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1748 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in SparcTargetLowering()
1776 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in SparcTargetLowering()
3075 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this); in LowerOperation()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp1705 case FPExt: return ISD::FP_EXTEND; in InstructionOpcodeToISD()

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