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Searched refs:FP_ROUND (Results 1 – 25 of 40) sorted by relevance

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/external/llvm/test/CodeGen/X86/
Dfp-double-rounding.ll26 ; Hack, to generate a precise FP_ROUND to double
/external/llvm/test/CodeGen/ARM/
Dneon_fpconv.ll3 ; PR12540: ARM backend lowering of FP_ROUND v2f64 to v2f32.
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h398 FP_ROUND, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h462 FP_ROUND, enumerator
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp95 case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break; in SoftenFloatResult()
758 case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break; in SoftenFloatOperand()
850 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16); in SoftenFloatOp_FP_ROUND()
969 Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(), in SoftenFloatOp_STORE()
1508 case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break; in ExpandFloatOperand()
1599 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ExpandFloatOp_FP_ROUND()
1614 Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res, in ExpandFloatOp_FP_TO_SINT()
1903 case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break; in PromoteFloatResult()
2132 DAG.getNode(ISD::FP_ROUND, DL, VT, NV, DAG.getIntPtrConstant(0, DL))); in PromoteFloatRes_XINT_TO_FP()
DLegalizeVectorTypes.cpp56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
202 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecRes_FP_ROUND()
458 case ISD::FP_ROUND: in ScalarizeVectorOperand()
555 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecOp_FP_ROUND()
647 case ISD::FP_ROUND: in SplitVectorResult()
1247 if (N->getOpcode() == ISD::FP_ROUND) { in SplitVecRes_UnaryOp()
1467 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; in SplitVectorOperand()
1984 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec, in SplitVecOp_TruncateHelper()
2021 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1)); in SplitVecOp_FP_ROUND()
2022 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1)); in SplitVecOp_FP_ROUND()
[all …]
DLegalizeDAG.cpp2322 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, in ExpandLegalINT_TO_FP()
2415 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd, in ExpandLegalINT_TO_FP()
2884 case ISD::FP_ROUND: in ExpandNode()
3187 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op, in ExpandNode()
4123 TruncOp = ISD::FP_ROUND; in PromoteNode()
4131 if (TruncOp != ISD::FP_ROUND) in PromoteNode()
4191 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4200 DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4217 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
4239 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
DLegalizeVectorOps.cpp324 case ISD::FP_ROUND: in LegalizeOp()
427 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl)); in Promote()
DSelectionDAGDumper.cpp249 case ISD::FP_ROUND: return "fp_round"; in getOperationName()
DDAGCombiner.cpp641 case ISD::FP_ROUND: in isNegatibleForFree()
721 case ISD::FP_ROUND: in GetNegatedExpression()
722 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
1416 case ISD::FP_ROUND: return visitFP_ROUND(N); in visit()
8829 } else if (N1.getOpcode() == ISD::FP_ROUND && in visitFDIV()
8833 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1)); in visitFDIV()
8917 N1.getOpcode() == ISD::FP_ROUND)) { in CanCombineFCOPYSIGN_EXTEND_ROUND()
9145 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1); in visitFP_ROUND()
9152 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
9173 return DAG.getNode(ISD::FP_ROUND, DL, VT, N0.getOperand(0), in visitFP_ROUND()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp83 case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break; in SoftenFloatResult()
586 case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break; in SoftenFloatOperand()
800 Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(), in SoftenFloatOp_STORE()
1266 case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break; in ExpandFloatOperand()
1347 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), in ExpandFloatOp_FP_ROUND()
1362 Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res, in ExpandFloatOp_FP_TO_SINT()
DLegalizeVectorTypes.cpp55 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
164 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), in ScalarizeVecRes_FP_ROUND()
459 case ISD::FP_ROUND: in SplitVectorResult()
818 if (N->getOpcode() == ISD::FP_ROUND) { in SplitVecRes_UnaryOp()
976 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; in SplitVectorOperand()
1200 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1)); in SplitVecOp_FP_ROUND()
1201 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1)); in SplitVecOp_FP_ROUND()
1284 case ISD::FP_ROUND: in WidenVectorResult()
DDAGCombiner.cpp412 case ISD::FP_ROUND: in isNegatibleForFree()
486 case ISD::FP_ROUND: in GetNegatedExpression()
487 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), in GetNegatedExpression()
1096 case ISD::FP_ROUND: return visitFP_ROUND(N); in visit()
5450 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) in visitFCOPYSIGN()
5539 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); in visitFP_ROUND()
5546 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
5550 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), in visitFP_ROUND()
5556 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, in visitFP_ROUND()
5588 N->use_begin()->getOpcode() == ISD::FP_ROUND) in visitFP_EXTEND()
[all …]
DLegalizeDAG.cpp2507 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, in ExpandLegalINT_TO_FP()
2596 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd, in ExpandLegalINT_TO_FP()
3092 case ISD::FP_ROUND: in ExpandNode()
3910 TruncOp = ISD::FP_ROUND; in PromoteNode()
3918 if (TruncOp != ISD::FP_ROUND) in PromoteNode()
DSelectionDAG.cpp2443 case ISD::FP_ROUND: in getNode()
2482 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node"); in getNode()
2807 case ISD::FP_ROUND: in getNode()
6036 case ISD::FP_ROUND: return "fp_round"; in getOperationName()
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp83 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost()
88 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND || in getCastInstrCost()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeISelLowering.cpp78 setOperationAction(ISD::FP_ROUND, MVT::f32, Expand); in MBlazeTargetLowering()
79 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand); in MBlazeTargetLowering()
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp556 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, in getCastInstrCost()
642 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, in getCastInstrCost()
720 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, in getCastInstrCost()
DX86ISelDAGToDAG.cpp591 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND) in PreprocessISelDAG()
623 if (N->getOpcode() == ISD::FP_ROUND) in PreprocessISelDAG()
DX86IntrinsicsInfo.h519 ISD::FP_ROUND, 0),
521 ISD::FP_ROUND, X86ISD::VFPROUND),
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1749 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in SparcTargetLowering()
1777 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in SparcTargetLowering()
1778 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in SparcTargetLowering()
3076 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); in LowerOperation()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelDAGToDAG.cpp474 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND) in PreprocessISelDAG()
504 if (N->getOpcode() == ISD::FP_ROUND) in PreprocessISelDAG()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp179 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in AArch64TargetLowering()
180 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in AArch64TargetLowering()
304 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote); in AArch64TargetLowering()
310 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
553 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand); in AArch64TargetLowering()
1996 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl)); in LowerVectorINT_TO_FP()
2019 ISD::FP_ROUND, dl, MVT::f16, in LowerINT_TO_FP()
2357 case ISD::FP_ROUND: in LowerOperation()
3755 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0, DL)); in LowerFCOPYSIGN()
4365 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0), in LowerVAARG()
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp195 setTargetDAGCombine(ISD::FP_ROUND); in R600TargetLowering()
1955 case ISD::FP_ROUND: { in PerformDAGCombine()
/external/llvm/test/CodeGen/AArch64/
Df16-instructions.ll760 ; Check that the FP promotion will use a truncating FP_ROUND, so we can fold

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