| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 37 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
142 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 452 FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR, enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 526 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, enumerator
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| D | BasicTTIImpl.h | 794 ISDs.push_back(ISD::FRINT); in getIntrinsicInstrCost()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 305 case Intrinsic::rint: Opcode = ISD::FRINT; break; in mightUseCTR()
360 Opcode = ISD::FRINT; break; in mightUseCTR()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedM1.td | 255 def : InstRW<[M1WriteFCVT3], (instregex "^FRINT.+r")>;
316 def : InstRW<[M1WriteFCVT3], (instregex "^FRINT[AIMNPXZ]v")>;
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| D | AArch64SchedA57.td | 486 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
488 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
559 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>;
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| D | AArch64SchedKryoDetails.td | 958 (instregex "FRINT(A|I|M|N|P|X|Z)(S|D)r")>;
964 (instregex "FRINT(A|I|M|N|P|X|Z)v2f32")>;
970 (instregex "FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)")>;
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| D | AArch64SchedVulcan.td | 420 (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>;
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| D | AArch64SchedCyclone.td | 574 // FRINT(AIMNPXZ) V,V
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| D | AArch64ISelLowering.cpp | 153 setOperationAction(ISD::FRINT, MVT::f128, Expand); in AArch64TargetLowering()
281 setOperationAction(ISD::FRINT, MVT::f16, Promote); in AArch64TargetLowering()
327 setOperationAction(ISD::FRINT, MVT::v4f16, Expand); in AArch64TargetLowering()
359 setOperationAction(ISD::FRINT, MVT::v8f16, Expand); in AArch64TargetLowering()
381 setOperationAction(ISD::FRINT, Ty, Legal); in AArch64TargetLowering()
537 setOperationAction(ISD::FRINT, MVT::v1f64, Expand); in AArch64TargetLowering()
625 setOperationAction(ISD::FRINT, Ty, Legal); in AArch64TargetLowering()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 186 case ISD::FRINT: in LegalizeOp()
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| D | LegalizeFloatTypes.cpp | 88 case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break; in SoftenFloatResult()
868 case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break; in ExpandFloatResult()
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| D | LegalizeVectorTypes.cpp | 85 case ISD::FRINT: in ScalarizeVectorResult()
462 case ISD::FRINT: in SplitVectorResult()
1309 case ISD::FRINT: in WidenVectorResult()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 165 case ISD::FRINT: return "frint"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 100 case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break; in SoftenFloatResult()
1037 case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break; in ExpandFloatResult()
1880 case ISD::FRINT: in PromoteFloatResult()
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| D | LegalizeVectorOps.cpp | 320 case ISD::FRINT: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 91 case ISD::FRINT: in ScalarizeVectorResult()
650 case ISD::FRINT: in SplitVectorResult()
2164 case ISD::FRINT: in WidenVectorResult()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 87 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 244 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
279 setOperationAction(ISD::FRINT, MVT::f64, Custom); in AMDGPUTargetLowering()
422 setOperationAction(ISD::FRINT, VT, Expand); in AMDGPUTargetLowering()
715 case ISD::FRINT: return LowerFRINT(Op, DAG); in LowerOperation()
1723 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0)); in LowerFNEARBYINT()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 932 setOperationAction(ISD::FRINT, VT, Expand); in initActions()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 317 setOperationAction(ISD::FRINT, Ty, Legal); in addMSAFloatType()
1895 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 378 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 448 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 512 setOperationAction(ISD::FRINT, MVT::v2f64, Expand); in ARMTargetLowering()
529 setOperationAction(ISD::FRINT, MVT::v4f32, Expand); in ARMTargetLowering()
546 setOperationAction(ISD::FRINT, MVT::v2f32, Expand); in ARMTargetLowering()
675 setOperationAction(ISD::FRINT, MVT::f64, Expand); in ARMTargetLowering()
993 setOperationAction(ISD::FRINT, MVT::f32, Legal); in ARMTargetLowering()
1007 setOperationAction(ISD::FRINT, MVT::f64, Legal); in ARMTargetLowering()
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