Home
last modified time | relevance | path

Searched refs:MRM4m (Results 1 – 25 of 27) sorted by relevance

12

/external/llvm/lib/Target/X86/
DX86InstrControl.td138 def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst",
145 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
152 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
263 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst),
314 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
326 def TAILJMPm64_REX : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
DX86InstrShiftRotate.td73 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
76 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
80 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
84 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
88 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, u8imm:$src),
92 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, u8imm:$src),
96 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, u8imm:$src),
100 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, u8imm:$src),
106 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
110 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
[all …]
DX86InstrSystem.td380 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
457 def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
489 def XSAVE : I<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
492 def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
511 def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
514 def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
DX86InstrFPStack.td245 defm SUB : FPBinary<fsub, MRM4m, "sub">;
328 def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">;
337 def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">;
344 def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">;
DX86InstrArithmetic.td86 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
96 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
101 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
106 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
1191 defm AND : ArithBinOp_RF<0x20, 0x22, 0x24, "and", MRM4r, MRM4m,
DX86InstrInfo.td1656 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1660 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1664 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
2404 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
DX86InstrFormats.td34 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
DX86InstrCompiler.td693 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">;
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h220 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 enumerator
497 case X86II::MRM4m: case X86II::MRM5m: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp545 case X86II::MRM4m: case X86II::MRM5m: in EmitVEXOpcodePrefix()
680 case X86II::MRM4m: case X86II::MRM5m: in DetermineREXPrefix()
977 case X86II::MRM4m: case X86II::MRM5m: in EncodeInstruction()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrShiftRotate.td67 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
70 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
73 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
76 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
80 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
83 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
87 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
90 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
95 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
98 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
[all …]
DX86InstrControl.td103 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
108 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
202 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
302 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst, variable_ops),
DX86InstrSystem.td328 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
388 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
412 def XSAVE : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
414 def XSAVE64 : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
DX86InstrFPStack.td211 defm SUB : FPBinary<fsub, MRM4m, "sub">;
278 def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">;
287 def FRSTORm : FPI<0xDD, MRM4m, (outs f32mem:$dst), (ins), "frstor\t$dst">;
294 def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f32mem:$src), "fbld\t$src">;
DX86CodeEmitter.cpp208 case X86II::MRM4m: case X86II::MRM5m: in determineREX()
938 case X86II::MRM4m: case X86II::MRM5m: in emitInstruction()
DX86InstrArithmetic.td71 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
81 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
86 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
90 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
1087 defm AND : ArithBinOp_RF<0x20, 0x22, 0x24, "and", MRM4r, MRM4m,
DX86InstrFormats.td29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
DX86InstrInfo.td1040 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1044 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1048 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
DX86InstrCompiler.td643 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
/external/swiftshader/third_party/LLVM/utils/TableGen/
DX86RecognizableInstr.cpp54 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, enumerator
752 case X86Local::MRM4m: in emitInstructionSpecifier()
833 case X86Local::MRM4m: in emitDecodePath()
922 case X86Local::MRM4m: in emitDecodePath()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h300 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 enumerator
693 case X86II::MRM4m: case X86II::MRM5m: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp784 case X86II::MRM4m: case X86II::MRM5m: in EmitVEXOpcodePrefix()
1014 case X86II::MRM4m: case X86II::MRM5m: in DetermineREXPrefix()
1373 case X86II::MRM4m: case X86II::MRM5m: in encodeInstruction()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp111 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, enumerator
744 case X86Local::MRM4m: in emitInstructionSpecifier()
860 case X86Local::MRM4m: case X86Local::MRM5m: in emitDecodePath()
/external/swiftshader/third_party/LLVM/test/TableGen/
DTargetInstrInfo.td56 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
/external/llvm/test/TableGen/
DTargetInstrInfo.td56 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;

12