1//===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 instruction set, defining the instructions, and
11// properties of the instructions which are needed for code generation, machine
12// code emission, and analysis.
13//
14//===----------------------------------------------------------------------===//
15
16//===----------------------------------------------------------------------===//
17// X86 specific DAG Nodes.
18//
19
20def SDTIntShiftDOp: SDTypeProfile<1, 3,
21                                  [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22                                   SDTCisInt<0>, SDTCisInt<3>]>;
23
24def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
25
26def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
28
29def SDTX86Cmov    : SDTypeProfile<1, 4,
30                                  [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31                                   SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
32
33// Unary and binary operator instructions that set EFLAGS as a side-effect.
34def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35                                           [SDTCisInt<0>, SDTCisVT<1, i32>]>;
36
37def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
38                                            [SDTCisSameAs<0, 2>,
39                                             SDTCisSameAs<0, 3>,
40                                             SDTCisInt<0>, SDTCisVT<1, i32>]>;
41
42// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
44                                            [SDTCisSameAs<0, 2>,
45                                             SDTCisSameAs<0, 3>,
46                                             SDTCisInt<0>,
47                                             SDTCisVT<1, i32>,
48                                             SDTCisVT<4, i32>]>;
49// RES1, RES2, FLAGS = op LHS, RHS
50def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
51                                            [SDTCisSameAs<0, 1>,
52                                             SDTCisSameAs<0, 2>,
53                                             SDTCisSameAs<0, 3>,
54                                             SDTCisInt<0>, SDTCisVT<1, i32>]>;
55def SDTX86BrCond  : SDTypeProfile<0, 3,
56                                  [SDTCisVT<0, OtherVT>,
57                                   SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
58
59def SDTX86SetCC   : SDTypeProfile<1, 2,
60                                  [SDTCisVT<0, i8>,
61                                   SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62def SDTX86SetCC_C : SDTypeProfile<1, 2,
63                                  [SDTCisInt<0>,
64                                   SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
65
66def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
67                                     SDTCisVT<2, i8>]>;
68def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
69
70def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
71                                SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
72def SDTX86Ret     : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
73
74def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
75def SDT_X86CallSeqEnd   : SDCallSeqEnd<[SDTCisVT<0, i32>,
76                                        SDTCisVT<1, i32>]>;
77
78def SDT_X86Call   : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
79
80def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
81                                                         SDTCisVT<1, iPTR>,
82                                                         SDTCisVT<2, iPTR>]>;
83
84def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
85                                            SDTCisPtrTy<1>,
86                                            SDTCisVT<2, i32>,
87                                            SDTCisVT<3, i8>,
88                                            SDTCisVT<4, i32>]>;
89
90def SDTX86RepStr  : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
91
92def SDTX86Void    : SDTypeProfile<0, 0, []>;
93
94def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
95
96def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
97
98def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
99
100def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
101
102def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
103
104def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
105
106def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
107def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
108
109def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
110                            [SDNPHasChain]>;
111def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
112                                [SDNPHasChain]>;
113def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
114                        [SDNPHasChain]>;
115def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
116                        [SDNPHasChain]>;
117def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
118                        [SDNPHasChain]>;
119
120
121def X86bsf     : SDNode<"X86ISD::BSF",      SDTUnaryArithWithFlags>;
122def X86bsr     : SDNode<"X86ISD::BSR",      SDTUnaryArithWithFlags>;
123def X86shld    : SDNode<"X86ISD::SHLD",     SDTIntShiftDOp>;
124def X86shrd    : SDNode<"X86ISD::SHRD",     SDTIntShiftDOp>;
125
126def X86cmp     : SDNode<"X86ISD::CMP" ,     SDTX86CmpTest>;
127def X86bt      : SDNode<"X86ISD::BT",       SDTX86CmpTest>;
128
129def X86cmov    : SDNode<"X86ISD::CMOV",     SDTX86Cmov>;
130def X86brcond  : SDNode<"X86ISD::BRCOND",   SDTX86BrCond,
131                        [SDNPHasChain]>;
132def X86setcc   : SDNode<"X86ISD::SETCC",    SDTX86SetCC>;
133def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
134
135def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
136                        [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
137                         SDNPMayLoad, SDNPMemOperand]>;
138def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
139                        [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
140                         SDNPMayLoad, SDNPMemOperand]>;
141def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
142                        [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
143                         SDNPMayLoad, SDNPMemOperand]>;
144
145def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
146                        [SDNPHasChain, SDNPMayStore,
147                         SDNPMayLoad, SDNPMemOperand]>;
148def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
149                        [SDNPHasChain, SDNPMayStore,
150                         SDNPMayLoad, SDNPMemOperand]>;
151def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
152                        [SDNPHasChain, SDNPMayStore,
153                         SDNPMayLoad, SDNPMemOperand]>;
154def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
155                        [SDNPHasChain, SDNPMayStore,
156                         SDNPMayLoad, SDNPMemOperand]>;
157def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
158                        [SDNPHasChain, SDNPMayStore,
159                         SDNPMayLoad, SDNPMemOperand]>;
160def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
161                        [SDNPHasChain, SDNPMayStore,
162                         SDNPMayLoad, SDNPMemOperand]>;
163def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
164                        [SDNPHasChain, SDNPMayStore,
165                         SDNPMayLoad, SDNPMemOperand]>;
166def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
167                        [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
168
169def X86vastart_save_xmm_regs :
170                 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
171                        SDT_X86VASTART_SAVE_XMM_REGS,
172                        [SDNPHasChain, SDNPVariadic]>;
173def X86vaarg64 :
174                 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
175                        [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
176                         SDNPMemOperand]>;
177def X86callseq_start :
178                 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
179                        [SDNPHasChain, SDNPOutGlue]>;
180def X86callseq_end :
181                 SDNode<"ISD::CALLSEQ_END",   SDT_X86CallSeqEnd,
182                        [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
183
184def X86call    : SDNode<"X86ISD::CALL",     SDT_X86Call,
185                        [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
186                         SDNPVariadic]>;
187
188def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
189                        [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
190def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
191                        [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
192                         SDNPMayLoad]>;
193
194def X86rdtsc   : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
195                        [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
196
197def X86Wrapper    : SDNode<"X86ISD::Wrapper",     SDTX86Wrapper>;
198def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP",  SDTX86Wrapper>;
199
200def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
201                        [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
202
203def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
204                        [SDNPHasChain]>;
205
206def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
207                        [SDNPHasChain,  SDNPOptInGlue, SDNPVariadic]>;
208
209def X86add_flag  : SDNode<"X86ISD::ADD",  SDTBinaryArithWithFlags,
210                          [SDNPCommutative]>;
211def X86sub_flag  : SDNode<"X86ISD::SUB",  SDTBinaryArithWithFlags>;
212def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
213                          [SDNPCommutative]>;
214def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
215                          [SDNPCommutative]>;
216def X86adc_flag  : SDNode<"X86ISD::ADC",  SDTBinaryArithWithFlagsInOut>;
217def X86sbb_flag  : SDNode<"X86ISD::SBB",  SDTBinaryArithWithFlagsInOut>;
218
219def X86inc_flag  : SDNode<"X86ISD::INC",  SDTUnaryArithWithFlags>;
220def X86dec_flag  : SDNode<"X86ISD::DEC",  SDTUnaryArithWithFlags>;
221def X86or_flag   : SDNode<"X86ISD::OR",   SDTBinaryArithWithFlags,
222                          [SDNPCommutative]>;
223def X86xor_flag  : SDNode<"X86ISD::XOR",  SDTBinaryArithWithFlags,
224                          [SDNPCommutative]>;
225def X86and_flag  : SDNode<"X86ISD::AND",  SDTBinaryArithWithFlags,
226                          [SDNPCommutative]>;
227def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>;
228
229def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
230
231def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
232                          [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
233
234def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
235                          [SDNPHasChain]>;
236
237def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
238                        [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
239
240//===----------------------------------------------------------------------===//
241// X86 Operand Definitions.
242//
243
244// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
245// the index operand of an address, to conform to x86 encoding restrictions.
246def ptr_rc_nosp : PointerLikeRegClass<1>;
247
248// *mem - Operand definitions for the funky X86 addressing mode operands.
249//
250def X86MemAsmOperand : AsmOperandClass {
251  let Name = "Mem";
252  let SuperClasses = [];
253}
254def X86AbsMemAsmOperand : AsmOperandClass {
255  let Name = "AbsMem";
256  let SuperClasses = [X86MemAsmOperand];
257}
258class X86MemOperand<string printMethod> : Operand<iPTR> {
259  let PrintMethod = printMethod;
260  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
261  let ParserMatchClass = X86MemAsmOperand;
262}
263
264let OperandType = "OPERAND_MEMORY" in {
265def opaque32mem : X86MemOperand<"printopaquemem">;
266def opaque48mem : X86MemOperand<"printopaquemem">;
267def opaque80mem : X86MemOperand<"printopaquemem">;
268def opaque512mem : X86MemOperand<"printopaquemem">;
269
270def i8mem   : X86MemOperand<"printi8mem">;
271def i16mem  : X86MemOperand<"printi16mem">;
272def i32mem  : X86MemOperand<"printi32mem">;
273def i64mem  : X86MemOperand<"printi64mem">;
274def i128mem : X86MemOperand<"printi128mem">;
275def i256mem : X86MemOperand<"printi256mem">;
276def f32mem  : X86MemOperand<"printf32mem">;
277def f64mem  : X86MemOperand<"printf64mem">;
278def f80mem  : X86MemOperand<"printf80mem">;
279def f128mem : X86MemOperand<"printf128mem">;
280def f256mem : X86MemOperand<"printf256mem">;
281}
282
283// A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
284// plain GR64, so that it doesn't potentially require a REX prefix.
285def i8mem_NOREX : Operand<i64> {
286  let PrintMethod = "printi8mem";
287  let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
288  let ParserMatchClass = X86MemAsmOperand;
289  let OperandType = "OPERAND_MEMORY";
290}
291
292// GPRs available for tailcall.
293// It represents GR64_TC or GR64_TCW64.
294def ptr_rc_tailcall : PointerLikeRegClass<2>;
295
296// Special i32mem for addresses of load folding tail calls. These are not
297// allowed to use callee-saved registers since they must be scheduled
298// after callee-saved register are popped.
299def i32mem_TC : Operand<i32> {
300  let PrintMethod = "printi32mem";
301  let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
302  let ParserMatchClass = X86MemAsmOperand;
303  let OperandType = "OPERAND_MEMORY";
304}
305
306// Special i64mem for addresses of load folding tail calls. These are not
307// allowed to use callee-saved registers since they must be scheduled
308// after callee-saved register are popped.
309def i64mem_TC : Operand<i64> {
310  let PrintMethod = "printi64mem";
311  let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
312                       ptr_rc_tailcall, i32imm, i8imm);
313  let ParserMatchClass = X86MemAsmOperand;
314  let OperandType = "OPERAND_MEMORY";
315}
316
317let OperandType = "OPERAND_PCREL",
318    ParserMatchClass = X86AbsMemAsmOperand,
319    PrintMethod = "print_pcrel_imm" in {
320def i32imm_pcrel : Operand<i32>;
321def i16imm_pcrel : Operand<i16>;
322
323def offset8 : Operand<i64>;
324def offset16 : Operand<i64>;
325def offset32 : Operand<i64>;
326def offset64 : Operand<i64>;
327
328// Branch targets have OtherVT type and print as pc-relative values.
329def brtarget : Operand<OtherVT>;
330def brtarget8 : Operand<OtherVT>;
331
332}
333
334def SSECC : Operand<i8> {
335  let PrintMethod = "printSSECC";
336  let OperandType = "OPERAND_IMMEDIATE";
337}
338
339class ImmSExtAsmOperandClass : AsmOperandClass {
340  let SuperClasses = [ImmAsmOperand];
341  let RenderMethod = "addImmOperands";
342}
343
344class ImmZExtAsmOperandClass : AsmOperandClass {
345  let SuperClasses = [ImmAsmOperand];
346  let RenderMethod = "addImmOperands";
347}
348
349// Sign-extended immediate classes. We don't need to define the full lattice
350// here because there is no instruction with an ambiguity between ImmSExti64i32
351// and ImmSExti32i8.
352//
353// The strange ranges come from the fact that the assembler always works with
354// 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
355// (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
356
357// [0, 0x7FFFFFFF]                                            |
358//   [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
359def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
360  let Name = "ImmSExti64i32";
361}
362
363// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
364//   [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
365def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
366  let Name = "ImmSExti16i8";
367  let SuperClasses = [ImmSExti64i32AsmOperand];
368}
369
370// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
371//   [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
372def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
373  let Name = "ImmSExti32i8";
374}
375
376// [0, 0x000000FF]
377def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
378  let Name = "ImmZExtu32u8";
379}
380
381
382// [0, 0x0000007F]                                            |
383//   [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
384def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
385  let Name = "ImmSExti64i8";
386  let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
387                      ImmSExti64i32AsmOperand];
388}
389
390// A couple of more descriptive operand definitions.
391// 16-bits but only 8 bits are significant.
392def i16i8imm  : Operand<i16> {
393  let ParserMatchClass = ImmSExti16i8AsmOperand;
394  let OperandType = "OPERAND_IMMEDIATE";
395}
396// 32-bits but only 8 bits are significant.
397def i32i8imm  : Operand<i32> {
398  let ParserMatchClass = ImmSExti32i8AsmOperand;
399  let OperandType = "OPERAND_IMMEDIATE";
400}
401// 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
402def u32u8imm  : Operand<i32> {
403  let ParserMatchClass = ImmZExtu32u8AsmOperand;
404  let OperandType = "OPERAND_IMMEDIATE";
405}
406
407// 64-bits but only 32 bits are significant.
408def i64i32imm  : Operand<i64> {
409  let ParserMatchClass = ImmSExti64i32AsmOperand;
410  let OperandType = "OPERAND_IMMEDIATE";
411}
412
413// 64-bits but only 32 bits are significant, and those bits are treated as being
414// pc relative.
415def i64i32imm_pcrel : Operand<i64> {
416  let PrintMethod = "print_pcrel_imm";
417  let ParserMatchClass = X86AbsMemAsmOperand;
418  let OperandType = "OPERAND_PCREL";
419}
420
421// 64-bits but only 8 bits are significant.
422def i64i8imm   : Operand<i64> {
423  let ParserMatchClass = ImmSExti64i8AsmOperand;
424  let OperandType = "OPERAND_IMMEDIATE";
425}
426
427def lea64_32mem : Operand<i32> {
428  let PrintMethod = "printi32mem";
429  let AsmOperandLowerMethod = "lower_lea64_32mem";
430  let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm);
431  let ParserMatchClass = X86MemAsmOperand;
432}
433
434
435//===----------------------------------------------------------------------===//
436// X86 Complex Pattern Definitions.
437//
438
439// Define X86 specific addressing mode.
440def addr      : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
441def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
442                               [add, sub, mul, X86mul_imm, shl, or, frameindex],
443                               []>;
444def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
445                               [tglobaltlsaddr], []>;
446
447def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
448                        [add, sub, mul, X86mul_imm, shl, or, frameindex,
449                         X86WrapperRIP], []>;
450
451def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
452                               [tglobaltlsaddr], []>;
453
454//===----------------------------------------------------------------------===//
455// X86 Instruction Predicate Definitions.
456def HasCMov      : Predicate<"Subtarget->hasCMov()">;
457def NoCMov       : Predicate<"!Subtarget->hasCMov()">;
458
459def HasMMX       : Predicate<"Subtarget->hasMMX()">;
460def Has3DNow     : Predicate<"Subtarget->has3DNow()">;
461def Has3DNowA    : Predicate<"Subtarget->has3DNowA()">;
462def HasSSE1      : Predicate<"Subtarget->hasSSE1()">;
463def HasSSE2      : Predicate<"Subtarget->hasSSE2()">;
464def HasSSE3      : Predicate<"Subtarget->hasSSE3()">;
465def HasSSSE3     : Predicate<"Subtarget->hasSSSE3()">;
466def HasSSE41     : Predicate<"Subtarget->hasSSE41()">;
467def HasSSE42     : Predicate<"Subtarget->hasSSE42()">;
468def HasSSE4A     : Predicate<"Subtarget->hasSSE4A()">;
469
470def HasAVX       : Predicate<"Subtarget->hasAVX()">;
471def HasXMM       : Predicate<"Subtarget->hasXMM()">;
472def HasXMMInt    : Predicate<"Subtarget->hasXMMInt()">;
473
474def HasPOPCNT    : Predicate<"Subtarget->hasPOPCNT()">;
475def HasAES       : Predicate<"Subtarget->hasAES()">;
476def HasCLMUL     : Predicate<"Subtarget->hasCLMUL()">;
477def HasFMA3      : Predicate<"Subtarget->hasFMA3()">;
478def HasFMA4      : Predicate<"Subtarget->hasFMA4()">;
479def HasMOVBE     : Predicate<"Subtarget->hasMOVBE()">;
480def HasRDRAND    : Predicate<"Subtarget->hasRDRAND()">;
481def HasF16C      : Predicate<"Subtarget->hasF16C()">;
482def HasLZCNT     : Predicate<"Subtarget->hasLZCNT()">;
483def HasBMI       : Predicate<"Subtarget->hasBMI()">;
484def FPStackf32   : Predicate<"!Subtarget->hasXMM()">;
485def FPStackf64   : Predicate<"!Subtarget->hasXMMInt()">;
486def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
487def In32BitMode  : Predicate<"!Subtarget->is64Bit()">,
488                             AssemblerPredicate<"!Mode64Bit">;
489def In64BitMode  : Predicate<"Subtarget->is64Bit()">,
490                             AssemblerPredicate<"Mode64Bit">;
491def IsWin64      : Predicate<"Subtarget->isTargetWin64()">;
492def NotWin64     : Predicate<"!Subtarget->isTargetWin64()">;
493def IsNaCl       : Predicate<"Subtarget->isTargetNaCl()">,
494                             AssemblerPredicate<"ModeNaCl">;
495def IsNaCl32     : Predicate<"Subtarget->isTargetNaCl32()">,
496                             AssemblerPredicate<"ModeNaCl,!Mode64Bit">;
497def IsNaCl64     : Predicate<"Subtarget->isTargetNaCl64()">,
498                             AssemblerPredicate<"ModeNaCl,Mode64Bit">;
499def NotNaCl      : Predicate<"!Subtarget->isTargetNaCl()">,
500                             AssemblerPredicate<"!ModeNaCl">;
501def SmallCode    : Predicate<"TM.getCodeModel() == CodeModel::Small">;
502def KernelCode   : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
503def FarData      : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
504                             "TM.getCodeModel() != CodeModel::Kernel">;
505def NearData     : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
506                             "TM.getCodeModel() == CodeModel::Kernel">;
507def IsStatic     : Predicate<"TM.getRelocationModel() == Reloc::Static">;
508def IsNotPIC     : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
509def OptForSize   : Predicate<"OptForSize">;
510def OptForSpeed  : Predicate<"!OptForSize">;
511def FastBTMem    : Predicate<"!Subtarget->isBTMemSlow()">;
512def CallImmAddr  : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
513
514//===----------------------------------------------------------------------===//
515// X86 Instruction Format Definitions.
516//
517
518include "X86InstrFormats.td"
519
520//===----------------------------------------------------------------------===//
521// Pattern fragments.
522//
523
524// X86 specific condition code. These correspond to CondCode in
525// X86InstrInfo.h. They must be kept in synch.
526def X86_COND_A   : PatLeaf<(i8 0)>;  // alt. COND_NBE
527def X86_COND_AE  : PatLeaf<(i8 1)>;  // alt. COND_NC
528def X86_COND_B   : PatLeaf<(i8 2)>;  // alt. COND_C
529def X86_COND_BE  : PatLeaf<(i8 3)>;  // alt. COND_NA
530def X86_COND_E   : PatLeaf<(i8 4)>;  // alt. COND_Z
531def X86_COND_G   : PatLeaf<(i8 5)>;  // alt. COND_NLE
532def X86_COND_GE  : PatLeaf<(i8 6)>;  // alt. COND_NL
533def X86_COND_L   : PatLeaf<(i8 7)>;  // alt. COND_NGE
534def X86_COND_LE  : PatLeaf<(i8 8)>;  // alt. COND_NG
535def X86_COND_NE  : PatLeaf<(i8 9)>;  // alt. COND_NZ
536def X86_COND_NO  : PatLeaf<(i8 10)>;
537def X86_COND_NP  : PatLeaf<(i8 11)>; // alt. COND_PO
538def X86_COND_NS  : PatLeaf<(i8 12)>;
539def X86_COND_O   : PatLeaf<(i8 13)>;
540def X86_COND_P   : PatLeaf<(i8 14)>; // alt. COND_PE
541def X86_COND_S   : PatLeaf<(i8 15)>;
542
543let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
544  def i16immSExt8  : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
545  def i32immSExt8  : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
546  def i64immSExt8  : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
547}
548
549def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
550
551
552// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
553// unsigned field.
554def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
555
556def i64immZExt32SExt8 : ImmLeaf<i64, [{
557  return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
558}]>;
559
560// Helper fragments for loads.
561// It's always safe to treat a anyext i16 load as a i32 load if the i16 is
562// known to be 32-bit aligned or better. Ditto for i8 to i16.
563def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
564  LoadSDNode *LD = cast<LoadSDNode>(N);
565  ISD::LoadExtType ExtType = LD->getExtensionType();
566  if (ExtType == ISD::NON_EXTLOAD)
567    return true;
568  if (ExtType == ISD::EXTLOAD)
569    return LD->getAlignment() >= 2 && !LD->isVolatile();
570  return false;
571}]>;
572
573def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
574  LoadSDNode *LD = cast<LoadSDNode>(N);
575  ISD::LoadExtType ExtType = LD->getExtensionType();
576  if (ExtType == ISD::EXTLOAD)
577    return LD->getAlignment() >= 2 && !LD->isVolatile();
578  return false;
579}]>;
580
581def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
582  LoadSDNode *LD = cast<LoadSDNode>(N);
583  ISD::LoadExtType ExtType = LD->getExtensionType();
584  if (ExtType == ISD::NON_EXTLOAD)
585    return true;
586  if (ExtType == ISD::EXTLOAD)
587    return LD->getAlignment() >= 4 && !LD->isVolatile();
588  return false;
589}]>;
590
591def loadi8  : PatFrag<(ops node:$ptr), (i8  (load node:$ptr))>;
592def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
593def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
594def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
595def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
596
597def sextloadi16i8  : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
598def sextloadi32i8  : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
599def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
600def sextloadi64i8  : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
601def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
602def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
603
604def zextloadi8i1   : PatFrag<(ops node:$ptr), (i8  (zextloadi1 node:$ptr))>;
605def zextloadi16i1  : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
606def zextloadi32i1  : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
607def zextloadi16i8  : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
608def zextloadi32i8  : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
609def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
610def zextloadi64i1  : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
611def zextloadi64i8  : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
612def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
613def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
614
615def extloadi8i1    : PatFrag<(ops node:$ptr), (i8  (extloadi1 node:$ptr))>;
616def extloadi16i1   : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
617def extloadi32i1   : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
618def extloadi16i8   : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
619def extloadi32i8   : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
620def extloadi32i16  : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
621def extloadi64i1   : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
622def extloadi64i8   : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
623def extloadi64i16  : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
624def extloadi64i32  : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
625
626
627// An 'and' node with a single use.
628def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
629  return N->hasOneUse();
630}]>;
631// An 'srl' node with a single use.
632def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
633  return N->hasOneUse();
634}]>;
635// An 'trunc' node with a single use.
636def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
637  return N->hasOneUse();
638}]>;
639
640//===----------------------------------------------------------------------===//
641// Instruction list.
642//
643
644// Nop
645let neverHasSideEffects = 1 in {
646  def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
647  def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
648                "nop{w}\t$zero", []>, TB, OpSize;
649  def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
650                "nop{l}\t$zero", []>, TB;
651}
652
653
654// Constructing a stack frame.
655def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
656                 "enter\t$len, $lvl", []>;
657
658let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
659def LEAVE    : I<0xC9, RawFrm,
660                 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
661
662let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
663def LEAVE64  : I<0xC9, RawFrm,
664                 (outs), (ins), "leave", []>, Requires<[In64BitMode]>;
665
666//===----------------------------------------------------------------------===//
667//  Miscellaneous Instructions.
668//
669
670let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
671let mayLoad = 1 in {
672def POP16r  : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
673  OpSize;
674def POP32r  : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
675def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
676  OpSize;
677def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
678  OpSize;
679def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
680def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
681
682def POPF16   : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
683def POPF32   : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
684               Requires<[In32BitMode]>;
685}
686
687let mayStore = 1 in {
688def PUSH16r  : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
689  OpSize;
690def PUSH32r  : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
691def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
692  OpSize;
693def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
694  OpSize;
695def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
696def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
697
698def PUSHi8   : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
699                      "push{l}\t$imm", []>;
700def PUSHi16  : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
701                      "push{w}\t$imm", []>, OpSize;
702def PUSHi32  : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
703                      "push{l}\t$imm", []>;
704
705def PUSHF16  : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
706def PUSHF32  : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
707               Requires<[In32BitMode]>;
708
709}
710}
711
712let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
713let mayLoad = 1 in {
714def POP64r   : I<0x58, AddRegFrm,
715                 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
716def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
717def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
718}
719let mayStore = 1 in {
720def PUSH64r  : I<0x50, AddRegFrm,
721                 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
722def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
723def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
724}
725}
726
727let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
728def PUSH64i8   : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
729                     "push{q}\t$imm", []>;
730def PUSH64i16  : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
731                      "push{q}\t$imm", []>;
732def PUSH64i32  : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
733                      "push{q}\t$imm", []>;
734}
735
736let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
737def POPF64   : I<0x9D, RawFrm, (outs), (ins), "popfq", []>,
738               Requires<[In64BitMode]>;
739let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
740def PUSHF64    : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>,
741                 Requires<[In64BitMode]>;
742
743
744
745let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
746    mayLoad=1, neverHasSideEffects=1 in {
747def POPA32   : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
748               Requires<[In32BitMode]>;
749}
750let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
751    mayStore=1, neverHasSideEffects=1 in {
752def PUSHA32  : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
753               Requires<[In32BitMode]>;
754}
755
756let Constraints = "$src = $dst" in {    // GR32 = bswap GR32
757def BSWAP32r : I<0xC8, AddRegFrm,
758                 (outs GR32:$dst), (ins GR32:$src),
759                 "bswap{l}\t$dst",
760                 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
761
762def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
763                  "bswap{q}\t$dst",
764                  [(set GR64:$dst, (bswap GR64:$src))]>, TB;
765} // Constraints = "$src = $dst"
766
767// Bit scan instructions.
768let Defs = [EFLAGS] in {
769def BSF16rr  : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
770                 "bsf{w}\t{$src, $dst|$dst, $src}",
771                 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
772def BSF16rm  : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
773                 "bsf{w}\t{$src, $dst|$dst, $src}",
774                 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
775                 OpSize;
776def BSF32rr  : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
777                 "bsf{l}\t{$src, $dst|$dst, $src}",
778                 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
779def BSF32rm  : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
780                 "bsf{l}\t{$src, $dst|$dst, $src}",
781                 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
782def BSF64rr  : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
783                  "bsf{q}\t{$src, $dst|$dst, $src}",
784                  [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
785def BSF64rm  : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
786                  "bsf{q}\t{$src, $dst|$dst, $src}",
787                  [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB;
788
789def BSR16rr  : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
790                 "bsr{w}\t{$src, $dst|$dst, $src}",
791                 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
792def BSR16rm  : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
793                 "bsr{w}\t{$src, $dst|$dst, $src}",
794                 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
795                 OpSize;
796def BSR32rr  : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
797                 "bsr{l}\t{$src, $dst|$dst, $src}",
798                 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
799def BSR32rm  : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
800                 "bsr{l}\t{$src, $dst|$dst, $src}",
801                 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
802def BSR64rr  : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
803                  "bsr{q}\t{$src, $dst|$dst, $src}",
804                  [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB;
805def BSR64rm  : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
806                  "bsr{q}\t{$src, $dst|$dst, $src}",
807                  [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB;
808} // Defs = [EFLAGS]
809
810
811// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
812let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
813def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", []>;
814def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", []>, OpSize;
815def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", []>;
816def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>;
817}
818
819// These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
820let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
821def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", []>;
822let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
823def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", []>, OpSize;
824let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
825def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", []>;
826let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
827def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>;
828
829def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", []>;
830def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", []>, OpSize;
831def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", []>;
832def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
833
834def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", []>;
835def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", []>, OpSize;
836def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", []>;
837def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
838
839
840//===----------------------------------------------------------------------===//
841//  Move Instructions.
842//
843
844let neverHasSideEffects = 1 in {
845def MOV8rr  : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
846                "mov{b}\t{$src, $dst|$dst, $src}", []>;
847def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
848                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
849def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
850                "mov{l}\t{$src, $dst|$dst, $src}", []>;
851def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
852                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
853}
854let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
855def MOV8ri  : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
856                   "mov{b}\t{$src, $dst|$dst, $src}",
857                   [(set GR8:$dst, imm:$src)]>;
858def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
859                   "mov{w}\t{$src, $dst|$dst, $src}",
860                   [(set GR16:$dst, imm:$src)]>, OpSize;
861def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
862                   "mov{l}\t{$src, $dst|$dst, $src}",
863                   [(set GR32:$dst, imm:$src)]>;
864def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
865                    "movabs{q}\t{$src, $dst|$dst, $src}",
866                    [(set GR64:$dst, imm:$src)]>;
867def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
868                      "mov{q}\t{$src, $dst|$dst, $src}",
869                      [(set GR64:$dst, i64immSExt32:$src)]>;
870}
871
872def MOV8mi  : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
873                   "mov{b}\t{$src, $dst|$dst, $src}",
874                   [(store (i8 imm:$src), addr:$dst)]>;
875def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
876                   "mov{w}\t{$src, $dst|$dst, $src}",
877                   [(store (i16 imm:$src), addr:$dst)]>, OpSize;
878def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
879                   "mov{l}\t{$src, $dst|$dst, $src}",
880                   [(store (i32 imm:$src), addr:$dst)]>;
881def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
882                      "mov{q}\t{$src, $dst|$dst, $src}",
883                      [(store i64immSExt32:$src, addr:$dst)]>;
884
885/// moffs8, moffs16 and moffs32 versions of moves.  The immediate is a
886/// 32-bit offset from the PC.  These are only valid in x86-32 mode.
887def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
888                   "mov{b}\t{$src, %al|AL, $src}", []>,
889                   Requires<[In32BitMode]>;
890def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
891                      "mov{w}\t{$src, %ax|AL, $src}", []>, OpSize,
892                     Requires<[In32BitMode]>;
893def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
894                      "mov{l}\t{$src, %eax|EAX, $src}", []>,
895                     Requires<[In32BitMode]>;
896def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
897                   "mov{b}\t{%al, $dst|$dst, AL}", []>,
898                  Requires<[In32BitMode]>;
899def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
900                      "mov{w}\t{%ax, $dst|$dst, AL}", []>, OpSize,
901                     Requires<[In32BitMode]>;
902def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
903                      "mov{l}\t{%eax, $dst|$dst, EAX}", []>,
904                     Requires<[In32BitMode]>;
905
906// FIXME: These definitions are utterly broken
907// Just leave them commented out for now because they're useless outside
908// of the large code model, and most compilers won't generate the instructions
909// in question.
910/*
911def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
912                      "mov{q}\t{$src, %rax|RAX, $src}", []>;
913def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
914                       "mov{q}\t{$src, %rax|RAX, $src}", []>;
915def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
916                       "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
917def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
918                       "mov{q}\t{%rax, $dst|$dst, RAX}", []>;
919*/
920
921
922let isCodeGenOnly = 1 in {
923def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
924                   "mov{b}\t{$src, $dst|$dst, $src}", []>;
925def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
926                    "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
927def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
928                    "mov{l}\t{$src, $dst|$dst, $src}", []>;
929def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
930                     "mov{q}\t{$src, $dst|$dst, $src}", []>;
931}
932
933let canFoldAsLoad = 1, isReMaterializable = 1 in {
934def MOV8rm  : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
935                "mov{b}\t{$src, $dst|$dst, $src}",
936                [(set GR8:$dst, (loadi8 addr:$src))]>;
937def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
938                "mov{w}\t{$src, $dst|$dst, $src}",
939                [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
940def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
941                "mov{l}\t{$src, $dst|$dst, $src}",
942                [(set GR32:$dst, (loadi32 addr:$src))]>;
943def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
944                 "mov{q}\t{$src, $dst|$dst, $src}",
945                 [(set GR64:$dst, (load addr:$src))]>;
946}
947
948def MOV8mr  : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
949                "mov{b}\t{$src, $dst|$dst, $src}",
950                [(store GR8:$src, addr:$dst)]>;
951def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
952                "mov{w}\t{$src, $dst|$dst, $src}",
953                [(store GR16:$src, addr:$dst)]>, OpSize;
954def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
955                "mov{l}\t{$src, $dst|$dst, $src}",
956                [(store GR32:$src, addr:$dst)]>;
957def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
958                 "mov{q}\t{$src, $dst|$dst, $src}",
959                 [(store GR64:$src, addr:$dst)]>;
960
961// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
962// that they can be used for copying and storing h registers, which can't be
963// encoded when a REX prefix is present.
964let isCodeGenOnly = 1 in {
965let neverHasSideEffects = 1 in
966def MOV8rr_NOREX : I<0x88, MRMDestReg,
967                     (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
968                     "mov{b}\t{$src, $dst|$dst, $src}  # NOREX", []>;
969let mayStore = 1 in
970def MOV8mr_NOREX : I<0x88, MRMDestMem,
971                     (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
972                     "mov{b}\t{$src, $dst|$dst, $src}  # NOREX", []>;
973let mayLoad = 1, neverHasSideEffects = 1,
974    canFoldAsLoad = 1, isReMaterializable = 1 in
975def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
976                     (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
977                     "mov{b}\t{$src, $dst|$dst, $src}  # NOREX", []>;
978}
979
980
981// Condition code ops, incl. set if equal/not equal/...
982let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
983def SAHF     : I<0x9E, RawFrm, (outs),  (ins), "sahf", []>;  // flags = AH
984let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
985def LAHF     : I<0x9F, RawFrm, (outs),  (ins), "lahf", []>;  // AH = flags
986
987
988//===----------------------------------------------------------------------===//
989// Bit tests instructions: BT, BTS, BTR, BTC.
990
991let Defs = [EFLAGS] in {
992def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
993               "bt{w}\t{$src2, $src1|$src1, $src2}",
994               [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
995def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
996               "bt{l}\t{$src2, $src1|$src1, $src2}",
997               [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
998def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
999               "bt{q}\t{$src2, $src1|$src1, $src2}",
1000               [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB;
1001
1002// Unlike with the register+register form, the memory+register form of the
1003// bt instruction does not ignore the high bits of the index. From ISel's
1004// perspective, this is pretty bizarre. Make these instructions disassembly
1005// only for now.
1006
1007def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1008               "bt{w}\t{$src2, $src1|$src1, $src2}",
1009//               [(X86bt (loadi16 addr:$src1), GR16:$src2),
1010//                (implicit EFLAGS)]
1011               []
1012               >, OpSize, TB, Requires<[FastBTMem]>;
1013def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1014               "bt{l}\t{$src2, $src1|$src1, $src2}",
1015//               [(X86bt (loadi32 addr:$src1), GR32:$src2),
1016//                (implicit EFLAGS)]
1017               []
1018               >, TB, Requires<[FastBTMem]>;
1019def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1020               "bt{q}\t{$src2, $src1|$src1, $src2}",
1021//               [(X86bt (loadi64 addr:$src1), GR64:$src2),
1022//                (implicit EFLAGS)]
1023                []
1024                >, TB;
1025
1026def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1027                "bt{w}\t{$src2, $src1|$src1, $src2}",
1028                [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
1029                OpSize, TB;
1030def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1031                "bt{l}\t{$src2, $src1|$src1, $src2}",
1032                [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
1033def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1034                "bt{q}\t{$src2, $src1|$src1, $src2}",
1035                [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB;
1036
1037// Note that these instructions don't need FastBTMem because that
1038// only applies when the other operand is in a register. When it's
1039// an immediate, bt is still fast.
1040def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1041                "bt{w}\t{$src2, $src1|$src1, $src2}",
1042                [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1043                 ]>, OpSize, TB;
1044def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1045                "bt{l}\t{$src2, $src1|$src1, $src2}",
1046                [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1047                 ]>, TB;
1048def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1049                "bt{q}\t{$src2, $src1|$src1, $src2}",
1050                [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1051                                     i64immSExt8:$src2))]>, TB;
1052
1053
1054def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1055                "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1056def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1057                "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1058def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1059                 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1060def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1061                "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1062def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1063                "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1064def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1065                 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1066def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1067                    "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1068def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1069                    "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1070def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1071                    "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1072def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1073                    "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1074def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1075                    "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1076def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1077                    "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1078
1079def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1080                "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1081def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1082                "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1083def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1084                 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1085def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1086                "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1087def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1088                "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1089def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1090                 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1091def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1092                    "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1093def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1094                    "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1095def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1096                    "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1097def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1098                    "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1099def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1100                    "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1101def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1102                    "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1103
1104def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1105                "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1106def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1107                "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1108def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1109                 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1110def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1111                "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1112def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1113                "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1114def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1115                 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1116def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1117                    "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1118def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1119                    "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1120def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1121                    "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1122def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1123                    "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
1124def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1125                    "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
1126def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1127                    "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1128} // Defs = [EFLAGS]
1129
1130
1131//===----------------------------------------------------------------------===//
1132// Atomic support
1133//
1134
1135
1136// Atomic swap. These are just normal xchg instructions. But since a memory
1137// operand is referenced, the atomicity is ensured.
1138let Constraints = "$val = $dst" in {
1139def XCHG8rm  : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
1140               "xchg{b}\t{$val, $ptr|$ptr, $val}",
1141               [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
1142def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr),
1143               "xchg{w}\t{$val, $ptr|$ptr, $val}",
1144               [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
1145                OpSize;
1146def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr),
1147               "xchg{l}\t{$val, $ptr|$ptr, $val}",
1148               [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
1149def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr),
1150                  "xchg{q}\t{$val, $ptr|$ptr, $val}",
1151                  [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1152
1153def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1154                "xchg{b}\t{$val, $src|$src, $val}", []>;
1155def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1156                 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
1157def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1158                 "xchg{l}\t{$val, $src|$src, $val}", []>;
1159def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1160                  "xchg{q}\t{$val, $src|$src, $val}", []>;
1161}
1162
1163def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1164                  "xchg{w}\t{$src, %ax|AX, $src}", []>, OpSize;
1165def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1166                  "xchg{l}\t{$src, %eax|EAX, $src}", []>, Requires<[In32BitMode]>;
1167// Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1168// xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1169def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1170                   "xchg{l}\t{$src, %eax|EAX, $src}", []>, Requires<[In64BitMode]>;
1171def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1172                  "xchg{q}\t{$src, %rax|RAX, $src}", []>;
1173
1174
1175
1176def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1177                "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1178def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1179                 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1180def XADD32rr  : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1181                 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1182def XADD64rr  : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1183                   "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1184
1185let mayLoad = 1, mayStore = 1 in {
1186def XADD8rm   : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1187                 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
1188def XADD16rm  : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1189                 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1190def XADD32rm  : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1191                 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
1192def XADD64rm  : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1193                   "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1194
1195}
1196
1197def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1198                   "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1199def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1200                    "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1201def CMPXCHG32rr  : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1202                     "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1203def CMPXCHG64rr  : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1204                      "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1205
1206let mayLoad = 1, mayStore = 1 in {
1207def CMPXCHG8rm   : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1208                     "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
1209def CMPXCHG16rm  : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1210                     "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
1211def CMPXCHG32rm  : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1212                     "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
1213def CMPXCHG64rm  : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1214                      "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1215}
1216
1217let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1218def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1219                  "cmpxchg8b\t$dst", []>, TB;
1220
1221let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1222def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1223                    "cmpxchg16b\t$dst", []>, TB, Requires<[HasCmpxchg16b]>;
1224
1225
1226
1227// Lock instruction prefix
1228def LOCK_PREFIX : I<0xF0, RawFrm, (outs),  (ins), "lock", []>;
1229
1230// Rex64 instruction prefix
1231def REX64_PREFIX : I<0x48, RawFrm, (outs),  (ins), "rex64", []>;
1232
1233// Data16 instruction prefix
1234def DATA16_PREFIX : I<0x66, RawFrm, (outs),  (ins), "data16", []>;
1235
1236// Repeat string operation instruction prefixes
1237// These uses the DF flag in the EFLAGS register to inc or dec ECX
1238let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1239// Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1240def REP_PREFIX : I<0xF3, RawFrm, (outs),  (ins), "rep", []>;
1241// Repeat while not equal (used with CMPS and SCAS)
1242def REPNE_PREFIX : I<0xF2, RawFrm, (outs),  (ins), "repne", []>;
1243}
1244
1245
1246// String manipulation instructions
1247def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
1248def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
1249def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
1250def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
1251
1252def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
1253def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
1254def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
1255
1256
1257// Flag instructions
1258def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
1259def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
1260def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
1261def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
1262def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
1263def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
1264def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
1265
1266def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
1267
1268// Table lookup instructions
1269def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
1270
1271// ASCII Adjust After Addition
1272// sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1273def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, Requires<[In32BitMode]>;
1274
1275// ASCII Adjust AX Before Division
1276// sets AL, AH and EFLAGS and uses AL and AH
1277def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1278                 "aad\t$src", []>, Requires<[In32BitMode]>;
1279
1280// ASCII Adjust AX After Multiply
1281// sets AL, AH and EFLAGS and uses AL
1282def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1283                 "aam\t$src", []>, Requires<[In32BitMode]>;
1284
1285// ASCII Adjust AL After Subtraction - sets
1286// sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1287def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, Requires<[In32BitMode]>;
1288
1289// Decimal Adjust AL after Addition
1290// sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1291def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, Requires<[In32BitMode]>;
1292
1293// Decimal Adjust AL after Subtraction
1294// sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1295def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, Requires<[In32BitMode]>;
1296
1297// Check Array Index Against Bounds
1298def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1299                   "bound\t{$src, $dst|$dst, $src}", []>, OpSize,
1300                   Requires<[In32BitMode]>;
1301def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1302                   "bound\t{$src, $dst|$dst, $src}", []>,
1303                   Requires<[In32BitMode]>;
1304
1305// Adjust RPL Field of Segment Selector
1306def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst),
1307                 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1308def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst),
1309                 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>;
1310
1311//===----------------------------------------------------------------------===//
1312// MOVBE Instructions
1313//
1314let Predicates = [HasMOVBE] in {
1315  def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1316                    "movbe{w}\t{$src, $dst|$dst, $src}",
1317                    [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, OpSize, T8;
1318  def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1319                    "movbe{l}\t{$src, $dst|$dst, $src}",
1320                    [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, T8;
1321  def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1322                     "movbe{q}\t{$src, $dst|$dst, $src}",
1323                     [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, T8;
1324  def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1325                    "movbe{w}\t{$src, $dst|$dst, $src}",
1326                    [(store (bswap GR16:$src), addr:$dst)]>, OpSize, T8;
1327  def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1328                    "movbe{l}\t{$src, $dst|$dst, $src}",
1329                    [(store (bswap GR32:$src), addr:$dst)]>, T8;
1330  def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1331                     "movbe{q}\t{$src, $dst|$dst, $src}",
1332                     [(store (bswap GR64:$src), addr:$dst)]>, T8;
1333}
1334
1335//===----------------------------------------------------------------------===//
1336// RDRAND Instruction
1337//
1338let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1339  def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1340                    "rdrand{w}\t$dst", []>, OpSize, TB;
1341  def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1342                    "rdrand{l}\t$dst", []>, TB;
1343  def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1344                     "rdrand{q}\t$dst", []>, TB;
1345}
1346
1347//===----------------------------------------------------------------------===//
1348// LZCNT Instruction
1349//
1350let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1351  def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1352                    "lzcnt{w}\t{$src, $dst|$dst, $src}",
1353                    [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1354                    OpSize;
1355  def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1356                    "lzcnt{w}\t{$src, $dst|$dst, $src}",
1357                    [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1358                     (implicit EFLAGS)]>, XS, OpSize;
1359
1360  def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1361                    "lzcnt{l}\t{$src, $dst|$dst, $src}",
1362                    [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS;
1363  def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1364                    "lzcnt{l}\t{$src, $dst|$dst, $src}",
1365                    [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1366                     (implicit EFLAGS)]>, XS;
1367
1368  def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1369                     "lzcnt{q}\t{$src, $dst|$dst, $src}",
1370                     [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1371                     XS;
1372  def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1373                     "lzcnt{q}\t{$src, $dst|$dst, $src}",
1374                     [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1375                      (implicit EFLAGS)]>, XS;
1376}
1377
1378//===----------------------------------------------------------------------===//
1379// TZCNT Instruction
1380//
1381let Predicates = [HasBMI], Defs = [EFLAGS] in {
1382  def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1383                    "tzcnt{w}\t{$src, $dst|$dst, $src}",
1384                    [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1385                    OpSize;
1386  def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1387                    "tzcnt{w}\t{$src, $dst|$dst, $src}",
1388                    [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1389                     (implicit EFLAGS)]>, XS, OpSize;
1390
1391  def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1392                    "tzcnt{l}\t{$src, $dst|$dst, $src}",
1393                    [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
1394  def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1395                    "tzcnt{l}\t{$src, $dst|$dst, $src}",
1396                    [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1397                     (implicit EFLAGS)]>, XS;
1398
1399  def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1400                     "tzcnt{q}\t{$src, $dst|$dst, $src}",
1401                     [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1402                     XS;
1403  def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1404                     "tzcnt{q}\t{$src, $dst|$dst, $src}",
1405                     [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1406                      (implicit EFLAGS)]>, XS;
1407}
1408
1409//===----------------------------------------------------------------------===//
1410// Subsystems.
1411//===----------------------------------------------------------------------===//
1412
1413include "X86InstrArithmetic.td"
1414include "X86InstrCMovSetCC.td"
1415include "X86InstrExtension.td"
1416include "X86InstrControl.td"
1417include "X86InstrShiftRotate.td"
1418
1419// X87 Floating Point Stack.
1420include "X86InstrFPStack.td"
1421
1422// SIMD support (SSE, MMX and AVX)
1423include "X86InstrFragmentsSIMD.td"
1424
1425// FMA - Fused Multiply-Add support (requires FMA)
1426include "X86InstrFMA.td"
1427
1428// SSE, MMX and 3DNow! vector support.
1429include "X86InstrSSE.td"
1430include "X86InstrMMX.td"
1431include "X86Instr3DNow.td"
1432
1433include "X86InstrVMX.td"
1434
1435// System instructions.
1436include "X86InstrSystem.td"
1437
1438// Compiler Pseudo Instructions and Pat Patterns
1439include "X86InstrCompiler.td"
1440
1441//===----------------------------------------------------------------------===//
1442// Assembler Mnemonic Aliases
1443//===----------------------------------------------------------------------===//
1444
1445def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>;
1446def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>;
1447
1448def : MnemonicAlias<"cbw",  "cbtw">;
1449def : MnemonicAlias<"cwd",  "cwtd">;
1450def : MnemonicAlias<"cdq", "cltd">;
1451def : MnemonicAlias<"cwde", "cwtl">;
1452def : MnemonicAlias<"cdqe", "cltq">;
1453
1454// lret maps to lretl, it is not ambiguous with lretq.
1455def : MnemonicAlias<"lret", "lretl">;
1456
1457def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>;
1458def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>;
1459
1460def : MnemonicAlias<"loopz", "loope">;
1461def : MnemonicAlias<"loopnz", "loopne">;
1462
1463def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
1464def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
1465def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>;
1466def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
1467def : MnemonicAlias<"popfd",  "popfl">;
1468
1469// FIXME: This is wrong for "push reg".  "push %bx" should turn into pushw in
1470// all modes.  However: "push (addr)" and "push $42" should default to
1471// pushl/pushq depending on the current mode.  Similar for "pop %bx"
1472def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
1473def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
1474def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
1475def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1476def : MnemonicAlias<"pushfd", "pushfl">;
1477
1478def : MnemonicAlias<"repe", "rep">;
1479def : MnemonicAlias<"repz", "rep">;
1480def : MnemonicAlias<"repnz", "repne">;
1481
1482def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>;
1483def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>;
1484
1485def : MnemonicAlias<"salb", "shlb">;
1486def : MnemonicAlias<"salw", "shlw">;
1487def : MnemonicAlias<"sall", "shll">;
1488def : MnemonicAlias<"salq", "shlq">;
1489
1490def : MnemonicAlias<"smovb", "movsb">;
1491def : MnemonicAlias<"smovw", "movsw">;
1492def : MnemonicAlias<"smovl", "movsl">;
1493def : MnemonicAlias<"smovq", "movsq">;
1494
1495def : MnemonicAlias<"ud2a", "ud2">;
1496def : MnemonicAlias<"verrw", "verr">;
1497
1498// System instruction aliases.
1499def : MnemonicAlias<"iret", "iretl">;
1500def : MnemonicAlias<"sysret", "sysretl">;
1501
1502def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>;
1503def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>;
1504def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>;
1505def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>;
1506def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>;
1507def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>;
1508def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>;
1509def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>;
1510
1511
1512// Floating point stack aliases.
1513def : MnemonicAlias<"fcmovz",   "fcmove">;
1514def : MnemonicAlias<"fcmova",   "fcmovnbe">;
1515def : MnemonicAlias<"fcmovnae", "fcmovb">;
1516def : MnemonicAlias<"fcmovna",  "fcmovbe">;
1517def : MnemonicAlias<"fcmovae",  "fcmovnb">;
1518def : MnemonicAlias<"fcomip",   "fcompi">;
1519def : MnemonicAlias<"fildq",    "fildll">;
1520def : MnemonicAlias<"fldcww",   "fldcw">;
1521def : MnemonicAlias<"fnstcww", "fnstcw">;
1522def : MnemonicAlias<"fnstsww", "fnstsw">;
1523def : MnemonicAlias<"fucomip",  "fucompi">;
1524def : MnemonicAlias<"fwait",    "wait">;
1525
1526
1527class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond>
1528  : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
1529                  !strconcat(Prefix, NewCond, Suffix)>;
1530
1531/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
1532/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
1533/// example "setz" -> "sete".
1534multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> {
1535  def C   : CondCodeAlias<Prefix, Suffix, "c",   "b">;   // setc   -> setb
1536  def Z   : CondCodeAlias<Prefix, Suffix, "z" ,  "e">;   // setz   -> sete
1537  def NA  : CondCodeAlias<Prefix, Suffix, "na",  "be">;  // setna  -> setbe
1538  def NB  : CondCodeAlias<Prefix, Suffix, "nb",  "ae">;  // setnb  -> setae
1539  def NC  : CondCodeAlias<Prefix, Suffix, "nc",  "ae">;  // setnc  -> setae
1540  def NG  : CondCodeAlias<Prefix, Suffix, "ng",  "le">;  // setng  -> setle
1541  def NL  : CondCodeAlias<Prefix, Suffix, "nl",  "ge">;  // setnl  -> setge
1542  def NZ  : CondCodeAlias<Prefix, Suffix, "nz",  "ne">;  // setnz  -> setne
1543  def PE  : CondCodeAlias<Prefix, Suffix, "pe",  "p">;   // setpe  -> setp
1544  def PO  : CondCodeAlias<Prefix, Suffix, "po",  "np">;  // setpo  -> setnp
1545
1546  def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">;   // setnae -> setb
1547  def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">;   // setnbe -> seta
1548  def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">;   // setnge -> setl
1549  def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">;   // setnle -> setg
1550}
1551
1552// Aliases for set<CC>
1553defm : IntegerCondCodeMnemonicAlias<"set", "">;
1554// Aliases for j<CC>
1555defm : IntegerCondCodeMnemonicAlias<"j", "">;
1556// Aliases for cmov<CC>{w,l,q}
1557defm : IntegerCondCodeMnemonicAlias<"cmov", "w">;
1558defm : IntegerCondCodeMnemonicAlias<"cmov", "l">;
1559defm : IntegerCondCodeMnemonicAlias<"cmov", "q">;
1560
1561
1562//===----------------------------------------------------------------------===//
1563// Assembler Instruction Aliases
1564//===----------------------------------------------------------------------===//
1565
1566// aad/aam default to base 10 if no operand is specified.
1567def : InstAlias<"aad", (AAD8i8 10)>;
1568def : InstAlias<"aam", (AAM8i8 10)>;
1569
1570// Disambiguate the mem/imm form of bt-without-a-suffix as btl.
1571def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>;
1572
1573// clr aliases.
1574def : InstAlias<"clrb $reg", (XOR8rr  GR8 :$reg, GR8 :$reg)>;
1575def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
1576def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
1577def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
1578
1579// div and idiv aliases for explicit A register.
1580def : InstAlias<"divb $src, %al",  (DIV8r  GR8 :$src)>;
1581def : InstAlias<"divw $src, %ax",  (DIV16r GR16:$src)>;
1582def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
1583def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1584def : InstAlias<"divb $src, %al",  (DIV8m  i8mem :$src)>;
1585def : InstAlias<"divw $src, %ax",  (DIV16m i16mem:$src)>;
1586def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
1587def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
1588def : InstAlias<"idivb $src, %al",  (IDIV8r  GR8 :$src)>;
1589def : InstAlias<"idivw $src, %ax",  (IDIV16r GR16:$src)>;
1590def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
1591def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
1592def : InstAlias<"idivb $src, %al",  (IDIV8m  i8mem :$src)>;
1593def : InstAlias<"idivw $src, %ax",  (IDIV16m i16mem:$src)>;
1594def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
1595def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
1596
1597
1598
1599// Various unary fpstack operations default to operating on on ST1.
1600// For example, "fxch" -> "fxch %st(1)"
1601def : InstAlias<"faddp",        (ADD_FPrST0  ST1), 0>;
1602def : InstAlias<"fsubp",        (SUBR_FPrST0 ST1)>;
1603def : InstAlias<"fsubrp",       (SUB_FPrST0  ST1)>;
1604def : InstAlias<"fmulp",        (MUL_FPrST0  ST1)>;
1605def : InstAlias<"fdivp",        (DIVR_FPrST0 ST1)>;
1606def : InstAlias<"fdivrp",       (DIV_FPrST0  ST1)>;
1607def : InstAlias<"fxch",         (XCH_F       ST1)>;
1608def : InstAlias<"fcomi",        (COM_FIr     ST1)>;
1609def : InstAlias<"fcompi",       (COM_FIPr    ST1)>;
1610def : InstAlias<"fucom",        (UCOM_Fr     ST1)>;
1611def : InstAlias<"fucomp",       (UCOM_FPr    ST1)>;
1612def : InstAlias<"fucomi",       (UCOM_FIr    ST1)>;
1613def : InstAlias<"fucompi",      (UCOM_FIPr   ST1)>;
1614
1615// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
1616// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)".  We also disambiguate
1617// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
1618// gas.
1619multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
1620 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"),
1621                 (Inst RST:$op), EmitAlias>;
1622 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"),
1623                 (Inst ST0), EmitAlias>;
1624}
1625
1626defm : FpUnaryAlias<"fadd",   ADD_FST0r>;
1627defm : FpUnaryAlias<"faddp",  ADD_FPrST0, 0>;
1628defm : FpUnaryAlias<"fsub",   SUB_FST0r>;
1629defm : FpUnaryAlias<"fsubp",  SUBR_FPrST0>;
1630defm : FpUnaryAlias<"fsubr",  SUBR_FST0r>;
1631defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>;
1632defm : FpUnaryAlias<"fmul",   MUL_FST0r>;
1633defm : FpUnaryAlias<"fmulp",  MUL_FPrST0>;
1634defm : FpUnaryAlias<"fdiv",   DIV_FST0r>;
1635defm : FpUnaryAlias<"fdivp",  DIVR_FPrST0>;
1636defm : FpUnaryAlias<"fdivr",  DIVR_FST0r>;
1637defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>;
1638defm : FpUnaryAlias<"fcomi",   COM_FIr, 0>;
1639defm : FpUnaryAlias<"fucomi",  UCOM_FIr, 0>;
1640defm : FpUnaryAlias<"fcompi",   COM_FIPr>;
1641defm : FpUnaryAlias<"fucompi",  UCOM_FIPr>;
1642
1643
1644// Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
1645// commute.  We also allow fdiv[r]p/fsubrp even though they don't commute,
1646// solely because gas supports it.
1647def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>;
1648def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>;
1649def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>;
1650def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>;
1651def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>;
1652def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
1653
1654// We accept "fnstsw %eax" even though it only writes %ax.
1655def : InstAlias<"fnstsw %eax", (FNSTSW8r)>;
1656def : InstAlias<"fnstsw %al" , (FNSTSW8r)>;
1657def : InstAlias<"fnstsw"     , (FNSTSW8r)>;
1658
1659// lcall and ljmp aliases.  This seems to be an odd mapping in 64-bit mode, but
1660// this is compatible with what GAS does.
1661def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1662def : InstAlias<"ljmp $seg, $off",  (FARJMP32i  i32imm:$off, i16imm:$seg)>;
1663def : InstAlias<"lcall *$dst",      (FARCALL32m opaque48mem:$dst)>;
1664def : InstAlias<"ljmp *$dst",       (FARJMP32m  opaque48mem:$dst)>;
1665
1666// "imul <imm>, B" is an alias for "imul <imm>, B, B".
1667def : InstAlias<"imulw $imm, $r", (IMUL16rri  GR16:$r, GR16:$r, i16imm:$imm)>;
1668def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
1669def : InstAlias<"imull $imm, $r", (IMUL32rri  GR32:$r, GR32:$r, i32imm:$imm)>;
1670def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
1671def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
1672def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
1673
1674// inb %dx -> inb %al, %dx
1675def : InstAlias<"inb %dx", (IN8rr)>;
1676def : InstAlias<"inw %dx", (IN16rr)>;
1677def : InstAlias<"inl %dx", (IN32rr)>;
1678def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
1679def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
1680def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
1681
1682
1683// jmp and call aliases for lcall and ljmp.  jmp $42,$5 -> ljmp
1684def : InstAlias<"call $seg, $off",  (FARCALL32i i32imm:$off, i16imm:$seg)>;
1685def : InstAlias<"jmp $seg, $off",   (FARJMP32i  i32imm:$off, i16imm:$seg)>;
1686def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
1687def : InstAlias<"jmpw $seg, $off",  (FARJMP16i  i16imm:$off, i16imm:$seg)>;
1688def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
1689def : InstAlias<"jmpl $seg, $off",  (FARJMP32i  i32imm:$off, i16imm:$seg)>;
1690
1691// Force mov without a suffix with a segment and mem to prefer the 'l' form of
1692// the move.  All segment/mem forms are equivalent, this has the shortest
1693// encoding.
1694def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
1695def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
1696
1697// Match 'movq <largeimm>, <reg>' as an alias for movabsq.
1698def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
1699
1700// Match 'movq GR64, MMX' as an alias for movd.
1701def : InstAlias<"movq $src, $dst",
1702                (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
1703def : InstAlias<"movq $src, $dst",
1704                (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
1705
1706// movsd with no operands (as opposed to the SSE scalar move of a double) is an
1707// alias for movsl. (as in rep; movsd)
1708def : InstAlias<"movsd", (MOVSD)>;
1709
1710// movsx aliases
1711def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
1712def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
1713def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
1714def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
1715def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
1716def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
1717def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
1718
1719// movzx aliases
1720def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
1721def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
1722def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
1723def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
1724def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
1725def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
1726// Note: No GR32->GR64 movzx form.
1727
1728// outb %dx -> outb %al, %dx
1729def : InstAlias<"outb %dx", (OUT8rr)>;
1730def : InstAlias<"outw %dx", (OUT16rr)>;
1731def : InstAlias<"outl %dx", (OUT32rr)>;
1732def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
1733def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
1734def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
1735
1736// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
1737// effect (both store to a 16-bit mem).  Force to sldtw to avoid ambiguity
1738// errors, since its encoding is the most compact.
1739def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
1740
1741// shld/shrd op,op -> shld op, op, 1
1742def : InstAlias<"shldw $r1, $r2", (SHLD16rri8 GR16:$r1, GR16:$r2, 1)>;
1743def : InstAlias<"shldl $r1, $r2", (SHLD32rri8 GR32:$r1, GR32:$r2, 1)>;
1744def : InstAlias<"shldq $r1, $r2", (SHLD64rri8 GR64:$r1, GR64:$r2, 1)>;
1745def : InstAlias<"shrdw $r1, $r2", (SHRD16rri8 GR16:$r1, GR16:$r2, 1)>;
1746def : InstAlias<"shrdl $r1, $r2", (SHRD32rri8 GR32:$r1, GR32:$r2, 1)>;
1747def : InstAlias<"shrdq $r1, $r2", (SHRD64rri8 GR64:$r1, GR64:$r2, 1)>;
1748
1749def : InstAlias<"shldw $mem, $reg", (SHLD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1750def : InstAlias<"shldl $mem, $reg", (SHLD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1751def : InstAlias<"shldq $mem, $reg", (SHLD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1752def : InstAlias<"shrdw $mem, $reg", (SHRD16mri8 i16mem:$mem, GR16:$reg, 1)>;
1753def : InstAlias<"shrdl $mem, $reg", (SHRD32mri8 i32mem:$mem, GR32:$reg, 1)>;
1754def : InstAlias<"shrdq $mem, $reg", (SHRD64mri8 i64mem:$mem, GR64:$reg, 1)>;
1755
1756/*  FIXME: This is disabled because the asm matcher is currently incapable of
1757 *  matching a fixed immediate like $1.
1758// "shl X, $1" is an alias for "shl X".
1759multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
1760 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1761                 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
1762 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1763                 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
1764 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1765                 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
1766 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1767                 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
1768 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
1769                 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
1770 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
1771                 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
1772 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
1773                 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
1774 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
1775                 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
1776}
1777
1778defm : ShiftRotateByOneAlias<"rcl", "RCL">;
1779defm : ShiftRotateByOneAlias<"rcr", "RCR">;
1780defm : ShiftRotateByOneAlias<"rol", "ROL">;
1781defm : ShiftRotateByOneAlias<"ror", "ROR">;
1782FIXME */
1783
1784// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
1785def : InstAlias<"testb $val, $mem", (TEST8rm  GR8 :$val, i8mem :$mem)>;
1786def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;
1787def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>;
1788def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>;
1789
1790// xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
1791def : InstAlias<"xchgb $mem, $val", (XCHG8rm  GR8 :$val, i8mem :$mem)>;
1792def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
1793def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
1794def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;
1795
1796// xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
1797def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16:$src)>;
1798def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
1799def : InstAlias<"xchgl %eax, $src", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
1800def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64:$src)>;
1801