| /external/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 260 unsigned &Op3) { in Decode3OpInstruction() argument
270 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode3OpInstruction()
539 unsigned Op1, Op2, Op3; in Decode3RInstruction() local
540 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RInstruction()
544 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RInstruction()
552 unsigned Op1, Op2, Op3; in Decode3RImmInstruction() local
553 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RImmInstruction()
557 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RImmInstruction()
565 unsigned Op1, Op2, Op3; in Decode2RUSInstruction() local
566 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode2RUSInstruction()
[all …]
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAGInfo.h | 60 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemcpy() argument
77 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove() argument
93 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemset() argument
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| /external/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGTargetInfo.h | 51 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
67 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove() argument
80 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
92 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
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| D | SelectionDAG.h | 1004 SDValue Op3);
1006 SDValue Op3, SDValue Op4);
1008 SDValue Op3, SDValue Op4, SDValue Op5);
1020 SDValue Op1, SDValue Op2, SDValue Op3);
1035 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
1037 EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3);
1058 SDValue Op1, SDValue Op2, SDValue Op3);
1068 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
1075 SDValue Op3);
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86CodeEmitter.cpp | 441 const MachineOperand &Op3 = MI.getOperand(Op+3); in emitMemModRMByte() local
446 if (Op3.isGlobal()) { in emitMemModRMByte()
447 DispForReloc = &Op3; in emitMemModRMByte()
448 } else if (Op3.isSymbol()) { in emitMemModRMByte()
449 DispForReloc = &Op3; in emitMemModRMByte()
450 } else if (Op3.isCPI()) { in emitMemModRMByte()
452 DispForReloc = &Op3; in emitMemModRMByte()
454 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex()); in emitMemModRMByte()
455 DispVal += Op3.getOffset(); in emitMemModRMByte()
457 } else if (Op3.isJTI()) { in emitMemModRMByte()
[all …]
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| D | X86ISelDAGToDAG.cpp | 2234 SDValue Op0, Op1, Op2, Op3, Op4; in SelectInlineAsmMemoryOperand() local
2240 if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4)) in SelectInlineAsmMemoryOperand()
2248 OutOps.push_back(Op3); in SelectInlineAsmMemoryOperand()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | SelectionDAG.h | 710 SDValue Op3);
712 SDValue Op3, SDValue Op4);
714 SDValue Op3, SDValue Op4, SDValue Op5);
727 SDValue Op1, SDValue Op2, SDValue Op3);
743 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
745 EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3);
766 SDValue Op1, SDValue Op2, SDValue Op3);
775 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
781 EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3);
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| D | SelectionDAGNodes.h | 736 const SDValue &Op2, const SDValue &Op3) {
744 Ops[3].setInitial(Op3);
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreSelectionDAGInfo.h | 27 SDValue Op3, unsigned Align, bool isVolatile,
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXSelectionDAGInfo.h | 45 SDValue Op3, unsigned Align,
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 61 SDValue Op3, unsigned Align,
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 70 const MCOperand &Op3 = MI->getOperand(3); in printInst() local
74 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
77 switch (Op3.getImm()) { in printInst()
110 if (Op2.isImm() && Op3.isImm()) { in printInst()
114 int64_t imms = Op3.getImm(); in printInst()
144 if (Op2.getImm() > Op3.getImm()) { in printInst()
147 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst()
155 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 58 SDValue Op3, unsigned Align, bool isVolatile,
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 3752 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
3753 if (Op2.isReg() && Op3.isImm()) { in MatchAndEmitInstruction()
3754 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in MatchAndEmitInstruction()
3774 NewOp4, Op3.getStartLoc(), Op3.getEndLoc(), getContext())); in MatchAndEmitInstruction()
3775 Operands[3] = AArch64Operand::CreateImm(NewOp3, Op3.getStartLoc(), in MatchAndEmitInstruction()
3776 Op3.getEndLoc(), getContext()); in MatchAndEmitInstruction()
3838 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
3841 if (Op1.isReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
3842 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in MatchAndEmitInstruction()
3857 return Error(Op3.getStartLoc(), in MatchAndEmitInstruction()
[all …]
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| /external/spirv-llvm/lib/SPIRV/libSPIRV/ |
| D | SPIRVUtil.h | 413 getVec(T Op1, T Op2, T Op3) { in getVec() argument
417 V.push_back(Op3); in getVec()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 20 bit Op3 = 0;
45 let TSFlags{5} = Op3;
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUNodes.td | 70 // Op3: Carry-generate shuffle mask
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 4730 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) { in UpdateNodeOperands() argument
4731 SDValue Ops[] = { Op1, Op2, Op3 }; in UpdateNodeOperands()
4737 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
4738 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
4744 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
4745 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
4823 SDValue Op2, SDValue Op3) { in SelectNodeTo() argument
4825 SDValue Ops[] = { Op1, Op2, Op3 }; in SelectNodeTo()
4882 SDValue Op3) { in SelectNodeTo() argument
4884 SDValue Ops[] = { Op1, Op2, Op3 }; in SelectNodeTo()
[all …]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 5775 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) { in UpdateNodeOperands() argument
5776 SDValue Ops[] = { Op1, Op2, Op3 }; in UpdateNodeOperands()
5782 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
5783 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
5789 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
5790 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
5861 SDValue Op2, SDValue Op3) { in SelectNodeTo() argument
5863 SDValue Ops[] = { Op1, Op2, Op3 }; in SelectNodeTo()
5918 SDValue Op3) { in SelectNodeTo() argument
5920 SDValue Ops[] = { Op1, Op2, Op3 }; in SelectNodeTo()
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSplitDouble.cpp | 867 MachineOperand &Op3 = MI->getOperand(3); in splitAslOr() local
868 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); in splitAslOr()
869 int64_t Sh64 = Op3.getImm(); in splitAslOr()
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| D | HexagonInstrInfo.cpp | 1237 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1241 unsigned Rt = Op3.getReg(); in expandPostRAPseudo()
1245 unsigned K3 = getKillRegState(Op3.isKill()); in expandPostRAPseudo()
1261 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1269 .addOperand(Op3); in expandPostRAPseudo()
1277 MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1285 SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::subreg_loreg); in expandPostRAPseudo()
1286 SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::subreg_hireg); in expandPostRAPseudo()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600Instructions.td | 22 bit Op3 = 0;
35 let TSFlags{5} = Op3;
107 let Op3 = 1;
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| /external/llvm/include/llvm/IR/ |
| D | PatternMatch.h | 1253 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) {
1254 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2698 SDValue Op0, Op1, Op2, Op3, Op4; in SelectInlineAsmMemoryOperand() local
2710 if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) in SelectInlineAsmMemoryOperand()
2718 OutOps.push_back(Op3); in SelectInlineAsmMemoryOperand()
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| /external/llvm/lib/Analysis/ |
| D | ConstantFolding.cpp | 1823 if (const auto *Op3 = dyn_cast<ConstantFP>(Operands[2])) { in ConstantFoldScalarCall() local
1830 Op3->getValueAPF(), in ConstantFoldScalarCall()
|