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Searched refs:OpNode (Results 1 – 25 of 54) sorted by relevance

123

/external/llvm/lib/Target/X86/
DX86InstrAVX512.td1354 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1361 (OpNode (_.VT _.RC:$src1),
1369 (OpNode (_.VT _.RC:$src1),
1409 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1418 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1432 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1437 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1442 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1450 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1457 (OpNode (_.VT _.RC:$src1),
[all …]
DX86InstrXOP.td86 multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode,
92 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
98 (vt128 (OpNode (vt128 VR128:$src1),
105 (vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))),
125 multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
131 (vt128 (OpNode (vt128 VR128:$src1), imm:$src2)))]>, XOP;
136 (vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))), imm:$src2)))]>, XOP;
180 multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128> {
187 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
195 (vt128 (OpNode (vt128 VR128:$src1),
[all …]
DX86InstrFMA.td145 SDPatternOperator OpNode = null_frag> {
151 [(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>;
159 (OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>;
195 SDNode OpNode, RegisterClass RC,
199 OpNode>;
225 SDNode OpNode> {
227 defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", OpNode,
232 defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", OpNode,
268 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
276 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
[all …]
DX86InstrFPStack.td127 multiclass FPBinary_rr<SDNode OpNode> {
131 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
133 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
135 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
140 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring,
147 (OpNode RFP32:$src1, (loadf32 addr:$src2))),
149 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>;
154 (OpNode RFP64:$src1, (loadf64 addr:$src2))),
156 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>;
161 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))),
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td1327 SDNode OpNode>
1329 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1332 SDNode OpNode>
1334 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1340 SDNode OpNode, SDNode OpNode_setflags> {
1341 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1345 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1364 SDPatternOperator OpNode>
1367 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1380 SDPatternOperator OpNode>
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/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.h80 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
82 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
84 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
87 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
89 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
91 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
DNVPTXInstrInfo.td169 multiclass I3<string OpcStr, SDNode OpNode> {
173 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, Int64Regs:$b))]>;
177 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
181 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
185 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
189 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, Int16Regs:$b))]>;
193 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
198 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
202 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
206 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
[all …]
DNVPTXVector.td239 class VecBinaryOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass,
243 [(set regclass:$dst, (OpNode regclass:$a, regclass:$b))],
246 class VecShiftOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass1,
250 [(set regclass1:$dst, (OpNode regclass1:$a, regclass2:$b))],
253 class VecUnaryOp<BinOpAsmString asmstr, PatFrag OpNode, NVPTXRegClass regclass,
257 [(set regclass:$dst, (OpNode regclass:$a))], sInst>;
259 multiclass IntBinVOp<string asmstr, SDNode OpNode,
262 def V2I64 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "64")>, OpNode, V2I64Regs,
264 def V4I32 : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "32")>, OpNode, V4I32Regs,
266 def V2I32 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "32")>, OpNode, V2I32Regs,
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeInstrFSL.td13 class FSLGet<bits<6> op, bits<5> flags, string instr_asm, Intrinsic OpNode> :
16 [(set GPR:$dst, (OpNode immZExt4:$b))],IIC_FSLg>
29 class FSLGetD<bits<6> op, bits<5> flags, string instr_asm, Intrinsic OpNode> :
32 [(set GPR:$dst, (OpNode GPR:$b))], IIC_FSLg>
45 class FSLPut<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
48 [(OpNode GPR:$v, immZExt4:$b)], IIC_FSLp>
61 class FSLPutD<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
64 [(OpNode GPR:$v, GPR:$b)], IIC_FSLp>
77 class FSLPutT<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
80 [(OpNode immZExt4:$b)], IIC_FSLp>
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DMBlazeInstrFPU.td21 class LoadFM<bits<6> op, string instr_asm, PatFrag OpNode> :
24 [(set (f32 GPR:$dst), (OpNode xaddr:$addr))], IIC_MEMl>;
26 class LoadFMI<bits<6> op, string instr_asm, PatFrag OpNode> :
29 [(set (f32 GPR:$dst), (OpNode iaddr:$addr))], IIC_MEMl>;
31 class StoreFM<bits<6> op, string instr_asm, PatFrag OpNode> :
34 [(OpNode (f32 GPR:$dst), xaddr:$addr)], IIC_MEMs>;
36 class StoreFMI<bits<6> op, string instr_asm, PatFrag OpNode> :
39 [(OpNode (f32 GPR:$dst), iaddr:$addr)], IIC_MEMs>;
41 class ArithF<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
45 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
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DMBlazeInstrInfo.td163 class Arith<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
167 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
169 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
173 [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIC_ALU>;
180 class ShiftI<bits<6> op, bits<2> flags, string instr_asm, SDNode OpNode,
184 [(set GPR:$dst, (OpNode GPR:$b, imm_type:$c))], IIC_SHT>;
186 class ArithR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
190 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
192 class ArithRI<bits<6> op, string instr_asm, SDNode OpNode,
196 [(set GPR:$dst, (OpNode imm_type:$b, GPR:$c))], IIC_ALU>;
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/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td259 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
265 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
270 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
276 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
281 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
287 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
292 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
298 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
303 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
309 list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
[all …]
DMipsInstrFPU.td105 SDPatternOperator OpNode= null_frag> :
108 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
114 SDPatternOperator OpNode = null_frag> {
115 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
116 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
122 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
129 SDPatternOperator OpNode= null_frag> {
130 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
132 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
[all …]
DMipsMSAInstrInfo.td1108 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1115 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1119 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1126 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1130 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1137 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1141 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1148 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1152 class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1159 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
[all …]
DMicroMips64r6InstrInfo.td175 SDPatternOperator OpNode = null_frag>
180 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rs, RO:$rt))];
226 SDPatternOperator OpNode = null_frag,
231 list<dag> Pattern = [(set GPR64Opnd:$rt, (OpNode GPR64Opnd:$rs, PO:$sa))];
239 SDPatternOperator OpNode = null_frag> {
244 (OpNode GPR64Opnd:$rt, GPR32Opnd:$rs))];
269 SDPatternOperator OpNode = null_frag> {
273 list<dag> Pattern = [(set GPR64Opnd:$rt, (OpNode addr:$addr))];
/external/llvm/lib/Target/BPF/
DBPFInstrInfo.td140 class ALU_RI<bits<4> Opc, string OpcodeStr, SDNode OpNode>
143 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]> {
159 class ALU_RR<bits<4> Opc, string OpcodeStr, SDNode OpNode>
162 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]> {
178 multiclass ALU<bits<4> Opc, string OpcodeStr, SDNode OpNode> {
179 def _rr : ALU_RR<Opc, OpcodeStr, OpNode>;
180 def _ri : ALU_RI<Opc, OpcodeStr, OpNode>;
316 class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode>
317 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
344 class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
[all …]
/external/skia/src/gpu/
DGrAuditTrail.cpp47 OpNode* opNode = new OpNode(renderTargetID); in addOp()
59 OpNode& consumerOp = *fOpList[index]; in opsCombined()
66 OpNode& consumedOp = *fOpList[consumedIndex]; in opsCombined()
89 const OpNode* bn = fOpList[opListID].get(); in copyOutFromOpList()
286 SkString GrAuditTrail::OpNode::toJson() const { in toJson()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td1816 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1819 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
1822 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1825 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
1847 ValueType TyD, ValueType TyQ, SDNode OpNode>
1850 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
1865 ValueType TyQ, ValueType TyD, SDNode OpNode>
1868 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
1894 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1898 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
[all …]
/external/skia/include/private/
DGrAuditTrail.h138 struct OpNode { struct
139 OpNode(const GrGpuResource::UniqueID& id) : fRenderTargetUniqueID(id) {} in OpNode() function
145 typedef SkTArray<std::unique_ptr<OpNode>, true> OpList; argument
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsInstrInfo.td266 class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
270 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
284 class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode,
288 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu>;
290 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
317 SDNode OpNode>:
320 [(set CPURegs:$rd, (OpNode CPURegs:$rt, (i32 immZExt5:$shamt)))], IIAlu> {
325 SDNode OpNode>:
328 [(set CPURegs:$rd, (OpNode CPURegs:$rt, CPURegs:$rs))], IIAlu> {
348 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
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DMipsInstrFPU.td107 multiclass FFR1P_M<bits<6> funct, string opstr, SDNode OpNode> {
108 def _S : FFR1P<funct, 16, opstr, "s", FGR32, FGR32, OpNode>;
109 def _D32 : FFR1P<funct, 17, opstr, "d", AFGR64, AFGR64, OpNode>,
111 def _D64 : FFR1P<funct, 17, opstr, "d", FGR64, FGR64, OpNode>,
115 multiclass FFR2P_M<bits<6> funct, string opstr, SDNode OpNode, bit isComm = 0> {
117 def _S : FFR2P<funct, 16, opstr, "s", FGR32, OpNode>;
118 def _D32 : FFR2P<funct, 17, opstr, "d", AFGR64, OpNode>,
120 def _D64 : FFR2P<funct, 17, opstr, "d", FGR64, OpNode>,
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrFPStack.td128 multiclass FPBinary_rr<SDNode OpNode> {
132 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
134 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
136 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
141 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
146 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
150 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
154 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>;
158 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>;
162 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>;
[all …]
/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td275 multiclass ALUbase<bits<3> subOp, string AsmStr, SDNode OpNode,
290 multiclass ALUarith<bits<3> subOp, string AsmStr, SDNode OpNode,
292 defm I_ : ALUbase<subOp, AsmStr, OpNode, LoExt, HiExt, [], []>;
298 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
301 multiclass ALUlogic<bits<3> subOp, string AsmStr, SDNode OpNode,
303 defm I_ : ALUbase<subOp, AsmStr, OpNode, LoExt, HiExt,
304 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
305 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
311 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
482 class LoadRR<string OpcString, PatFrag OpNode, ValueType Ty>
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td2435 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2438 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2441 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2444 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2500 ValueType TyD, ValueType TyQ, SDNode OpNode>
2503 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2518 ValueType TyQ, ValueType TyD, SDNode OpNode>
2521 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2547 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2551 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreInstrInfo.td203 multiclass F3R_2RUS<string OpcStr, SDNode OpNode> {
207 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
211 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
225 multiclass F3R_2RBITP<string OpcStr, SDNode OpNode> {
229 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
233 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
236 class F3R<string OpcStr, SDNode OpNode> : _F3R<
239 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
248 multiclass FL3R_L2RUS<string OpcStr, SDNode OpNode> {
252 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
[all …]

123