| /external/llvm/lib/Target/Lanai/InstPrinter/ |
| D | LanaiInstPrinter.cpp | 211 const MCOperand &RegOp) { in printMemoryBaseRegister() argument
212 assert(RegOp.isReg() && "Register operand expected"); in printMemoryBaseRegister()
216 OS << "%" << LanaiInstPrinter::getRegisterName(RegOp.getReg()); in printMemoryBaseRegister()
237 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRiOperand() local
246 printMemoryBaseRegister(OS, AluCode, RegOp); in printMemRiOperand()
252 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRrOperand() local
256 assert(OffsetOp.isReg() && RegOp.isReg() && "Registers expected."); in printMemRrOperand()
262 OS << "%" << getRegisterName(RegOp.getReg()); in printMemRrOperand()
273 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemSplsOperand() local
282 printMemoryBaseRegister(OS, AluCode, RegOp); in printMemSplsOperand()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 395 inline unsigned getRegState(const MachineOperand &RegOp) { in getRegState() argument
396 assert(RegOp.isReg() && "Not a register operand"); in getRegState()
397 return getDefRegState(RegOp.isDef()) | in getRegState()
398 getImplRegState(RegOp.isImplicit()) | in getRegState()
399 getKillRegState(RegOp.isKill()) | in getRegState()
400 getDeadRegState(RegOp.isDead()) | in getRegState()
401 getUndefRegState(RegOp.isUndef()) | in getRegState()
402 getInternalReadRegState(RegOp.isInternalRead()) | in getRegState()
403 getDebugRegState(RegOp.isDebug()); in getRegState()
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| /external/llvm/lib/Target/BPF/InstPrinter/ |
| D | BPFInstPrinter.cpp | 68 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemOperand() local
77 assert(RegOp.isReg() && "Register operand not a register"); in printMemOperand()
78 O << '(' << getRegisterName(RegOp.getReg()) << ')'; in printMemOperand()
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiAsmPrinter.cpp | 132 unsigned RegOp = OpNo + 1; in PrintAsmOperand() local
133 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
135 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 498 unsigned RegOp = OpNum; in PrintAsmOperand() local
504 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; in PrintAsmOperand()
507 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; in PrintAsmOperand()
510 RegOp = OpNum + 1; in PrintAsmOperand()
512 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
514 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfCompileUnit.cpp | 511 const MachineOperand RegOp = DVInsn->getOperand(0); in constructVariableDIEImpl() local
514 MachineLocation Location(RegOp.getReg(), in constructVariableDIEImpl()
517 } else if (RegOp.getReg()) in constructVariableDIEImpl()
518 addVariableAddress(DV, *VariableDie, MachineLocation(RegOp.getReg())); in constructVariableDIEImpl()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 260 unsigned RegOp = IsStore ? 0 : 5; in SimplifyShortMoveForm() local
262 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && in SimplifyShortMoveForm()
272 unsigned Reg = Inst.getOperand(RegOp).getReg(); in SimplifyShortMoveForm()
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| D | X86InstrInfo.h | 149 unsigned RegOp, unsigned MemOp, unsigned Flags);
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| D | X86InstrInfo.cpp | 263 unsigned RegOp = OpTbl2Addr[i][0]; in X86InstrInfo() local
267 RegOp, MemOp, in X86InstrInfo()
373 unsigned RegOp = OpTbl0[i][0]; in X86InstrInfo() local
377 RegOp, MemOp, TB_INDEX_0 | Flags); in X86InstrInfo()
533 unsigned RegOp = OpTbl1[i][0]; in X86InstrInfo() local
537 RegOp, MemOp, in X86InstrInfo()
894 unsigned RegOp = OpTbl2[i][0]; in X86InstrInfo() local
898 RegOp, MemOp, in X86InstrInfo()
907 unsigned RegOp, unsigned MemOp, unsigned Flags) { in AddTableEntry() argument
909 assert(!R2MTable.count(RegOp) && "Duplicate entry!"); in AddTableEntry()
[all …]
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86Operand.h | 44 struct RegOp { struct
64 struct RegOp Reg;
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/AsmPrinter/ |
| D | DwarfCompileUnit.cpp | 1246 const MachineOperand RegOp = DVInsn->getOperand(0); in constructVariableDIE() local
1249 TRI->getFrameRegister(*Asm->MF) == RegOp.getReg()) { in constructVariableDIE()
1259 } else if (RegOp.getReg()) in constructVariableDIE()
1261 MachineLocation(RegOp.getReg())); in constructVariableDIE()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 165 uint16_t RegOp, uint16_t MemOp, uint16_t Flags);
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| D | X86MCInstLower.cpp | 310 unsigned RegOp = IsStore ? 0 : 5; in SimplifyShortMoveForm() local
312 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && in SimplifyShortMoveForm()
322 unsigned Reg = Inst.getOperand(RegOp).getReg(); in SimplifyShortMoveForm()
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| D | X86InstrInfo.cpp | 107 uint16_t RegOp; member
289 Entry.RegOp, Entry.MemOp, in X86InstrInfo()
444 Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags); in X86InstrInfo()
881 Entry.RegOp, Entry.MemOp, in X86InstrInfo()
1754 Entry.RegOp, Entry.MemOp, in X86InstrInfo()
1991 Entry.RegOp, Entry.MemOp, in X86InstrInfo()
2040 Entry.RegOp, Entry.MemOp, in X86InstrInfo()
2049 uint16_t RegOp, uint16_t MemOp, uint16_t Flags) { in AddTableEntry() argument
2051 assert(!R2MTable.count(RegOp) && "Duplicate entry!"); in AddTableEntry()
2052 R2MTable[RegOp] = std::make_pair(MemOp, Flags); in AddTableEntry()
[all …]
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| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 86 struct RegOp { struct in __anon920606c00111::SystemZOperand
113 RegOp Reg;
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | LiveIntervalAnalysis.cpp | 943 unsigned RegOp = 0; in getReMatImplicitUse() local
956 assert(!RegOp && in getReMatImplicitUse()
958 RegOp = MO.getReg(); in getReMatImplicitUse()
963 return RegOp; in getReMatImplicitUse()
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| /external/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 105 struct RegOp { struct
122 struct RegOp Reg;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 361 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1; in PrintAsmOperand() local
362 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
364 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 486 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1; in PrintAsmOperand() local
487 if (RegOp >= MI->getNumOperands()) in PrintAsmOperand()
489 const MachineOperand &MO = MI->getOperand(RegOp); in PrintAsmOperand()
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 201 struct RegOp { struct in __anoncba7d3b40111::SparcOperand
218 struct RegOp Reg;
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 177 struct RegOp { struct in __anon26fd99540211::AArch64Operand
252 struct RegOp Reg;
4000 AArch64Operand &RegOp = static_cast<AArch64Operand &>(*Operands[1]); in MatchAndEmitInstruction() local
4002 if (RegOp.isReg() && ImmOp.isFPImm() && ImmOp.getFPImm() == (unsigned)-1) { in MatchAndEmitInstruction()
4005 RegOp.getReg()) in MatchAndEmitInstruction()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGRRList.cpp | 1249 if (const auto *RegOp = dyn_cast<RegisterMaskSDNode>(Op.getNode())) in getNodeRegMask() local
1250 return RegOp->getRegMask(); in getNodeRegMask()
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 145 struct RegOp { struct in __anon2fa8e53e0111::AMDGPUOperand
156 RegOp Reg;
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 488 struct RegOp { struct in __anonef5d38c20311::ARMOperand
572 struct RegOp Reg;
4763 unsigned RegOp = 4; in cvtThumbMultiply() local
4767 RegOp = 5; in cvtThumbMultiply()
4768 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); in cvtThumbMultiply()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfoV4.td | 1575 bits<5> RegOp; // Non-New-Value Operand
1583 let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
1591 let Inst{12-8} = RegOp;
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