| /external/llvm/lib/CodeGen/ |
| D | RegisterPressure.cpp | 75 dbgs() << PrintVRegOrUnit(P.RegUnit, TRI); in dump()
83 dbgs() << PrintVRegOrUnit(P.RegUnit, TRI); in dump()
112 void RegPressureTracker::increaseRegPressure(unsigned RegUnit, in increaseRegPressure() argument
118 PSetIterator PSetI = MRI->getPressureSets(RegUnit); in increaseRegPressure()
127 void RegPressureTracker::decreaseRegPressure(unsigned RegUnit, in decreaseRegPressure() argument
130 decreaseSetPressure(CurrSetPressure, *MRI, RegUnit, PreviousMask, NewMask); in decreaseRegPressure()
322 unsigned RegUnit = Pair.RegUnit; in initLiveThru() local
323 if (TargetRegisterInfo::isVirtualRegister(RegUnit) in initLiveThru()
324 && !RPTracker.hasUntiedDef(RegUnit)) in initLiveThru()
325 increaseSetPressure(LiveThruPressure, *MRI, RegUnit, 0, Pair.LaneMask); in initLiveThru()
[all …]
|
| D | LiveRegMatrix.cpp | 172 unsigned RegUnit) { in query() argument
173 LiveIntervalUnion::Query &Q = Queries[RegUnit]; in query()
174 Q.init(UserTag, &VirtReg, &Matrix[RegUnit]); in query()
|
| D | MachineTraceMetrics.cpp | 681 unsigned RegUnit; member
686 unsigned getSparseSetIndex() const { return RegUnit; } in getSparseSetIndex()
688 LiveRegUnit(unsigned RU) : RegUnit(RU), Cycle(0), MI(nullptr), Op(0) {} in LiveRegUnit()
1120 TBI.LiveIns.push_back(LiveInReg(RI->RegUnit, RI->Cycle)); in computeInstrHeights()
1121 DEBUG(dbgs() << ' ' << PrintRegUnit(RI->RegUnit, MTM.TRI) in computeInstrHeights()
|
| D | MachineScheduler.cpp | 992 unsigned Reg = P.RegUnit; in updatePressureDiffs()
1210 unsigned Reg = P.RegUnit; in computeCyclicCriticalPath()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterPressure.h | 30 unsigned RegUnit; ///< Virtual register or register unit. member
33 RegisterMaskPair(unsigned RegUnit, LaneBitmask LaneMask) in RegisterMaskPair()
34 : RegUnit(RegUnit), LaneMask(LaneMask) {} in RegisterMaskPair()
146 void addPressureChange(unsigned RegUnit, bool IsDec,
288 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
301 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
538 void increaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask,
540 void decreaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask,
551 LaneBitmask getLastUsedLanes(unsigned RegUnit, SlotIndex Pos) const;
552 LaneBitmask getLiveLanesAt(unsigned RegUnit, SlotIndex Pos) const;
[all …]
|
| D | MachineRegisterInfo.h | 564 PSetIterator getPressureSets(unsigned RegUnit) const;
1029 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { in PSetIterator() argument
1031 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) { in PSetIterator()
1032 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); in PSetIterator()
1037 PSet = TRI->getRegUnitPressureSets(RegUnit); in PSetIterator()
1038 Weight = TRI->getRegUnitWeight(RegUnit); in PSetIterator()
1058 getPressureSets(unsigned RegUnit) const { in getPressureSets() argument
1059 return PSetIterator(RegUnit, this); in getPressureSets()
|
| D | LiveRegMatrix.h | 139 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned RegUnit);
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 435 struct RegUnit { struct
450 RegUnit() : Weight(0), RegClassUnitSetsIdx(0) { in RegUnit() function
499 SmallVector<RegUnit, 8> RegUnits;
646 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; } in getRegUnit()
647 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; } in getRegUnit()
|
| D | RegisterInfoEmitter.cpp | 232 const RegUnit &RU = RegBank.getRegUnit(UnitIdx); in EmitRegUnitPressure()
|
| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 617 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { in MCRegUnitRootIterator() argument
618 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); in MCRegUnitRootIterator()
619 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
620 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 429 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const { in hasRegUnit() argument
431 if (*Units == RegUnit) in hasRegUnit()
723 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
743 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIMachineScheduler.h | 465 InRegs.insert(RegMaskPair.RegUnit); in getInRegs()
|
| D | SIMachineScheduler.cpp | 331 if (TargetRegisterInfo::isVirtualRegister(RegMaskPair.RegUnit)) in initRegPressure()
332 LiveInRegs.insert(RegMaskPair.RegUnit); in initRegPressure()
358 unsigned Reg = RegMaskPair.RegUnit; in initRegPressure()
|