1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "CodeGenRegisters.h"
17 #include "CodeGenTarget.h"
18 #include "SequenceToOffsetTable.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/SetVector.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/SparseBitVector.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/CodeGen/MachineValueType.h"
27 #include "llvm/Support/Casting.h"
28 #include "llvm/Support/Format.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include "llvm/TableGen/Error.h"
31 #include "llvm/TableGen/Record.h"
32 #include "llvm/TableGen/SetTheory.h"
33 #include "llvm/TableGen/TableGenBackend.h"
34 #include <algorithm>
35 #include <cassert>
36 #include <cstddef>
37 #include <cstdint>
38 #include <deque>
39 #include <iterator>
40 #include <set>
41 #include <string>
42 #include <vector>
43
44 using namespace llvm;
45
46 namespace {
47
48 class RegisterInfoEmitter {
49 RecordKeeper &Records;
50
51 public:
RegisterInfoEmitter(RecordKeeper & R)52 RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
53
54 // runEnums - Print out enum values for all of the registers.
55 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
56
57 // runMCDesc - Print out MC register descriptions.
58 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
59
60 // runTargetHeader - Emit a header fragment for the register info emitter.
61 void runTargetHeader(raw_ostream &o, CodeGenTarget &Target,
62 CodeGenRegBank &Bank);
63
64 // runTargetDesc - Output the target register and register file descriptions.
65 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target,
66 CodeGenRegBank &Bank);
67
68 // run - Output the register file description.
69 void run(raw_ostream &o);
70
71 private:
72 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
73 bool isCtor);
74 void EmitRegMappingTables(raw_ostream &o,
75 const std::deque<CodeGenRegister> &Regs,
76 bool isCtor);
77 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
78 const std::string &ClassName);
79 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
80 const std::string &ClassName);
81 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
82 const std::string &ClassName);
83 };
84
85 } // end anonymous namespace
86
87 // runEnums - Print out enum values for all of the registers.
runEnums(raw_ostream & OS,CodeGenTarget & Target,CodeGenRegBank & Bank)88 void RegisterInfoEmitter::runEnums(raw_ostream &OS,
89 CodeGenTarget &Target, CodeGenRegBank &Bank) {
90 const auto &Registers = Bank.getRegisters();
91
92 // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
93 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
94
95 std::string Namespace =
96 Registers.front().TheDef->getValueAsString("Namespace");
97
98 emitSourceFileHeader("Target Register Enum Values", OS);
99
100 OS << "\n#ifdef GET_REGINFO_ENUM\n";
101 OS << "#undef GET_REGINFO_ENUM\n\n";
102
103 OS << "namespace llvm {\n\n";
104
105 OS << "class MCRegisterClass;\n"
106 << "extern const MCRegisterClass " << Namespace
107 << "MCRegisterClasses[];\n\n";
108
109 if (!Namespace.empty())
110 OS << "namespace " << Namespace << " {\n";
111 OS << "enum {\n NoRegister,\n";
112
113 for (const auto &Reg : Registers)
114 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n";
115 assert(Registers.size() == Registers.back().EnumValue &&
116 "Register enum value mismatch!");
117 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
118 OS << "};\n";
119 if (!Namespace.empty())
120 OS << "} // end namespace " << Namespace << "\n";
121
122 const auto &RegisterClasses = Bank.getRegClasses();
123 if (!RegisterClasses.empty()) {
124
125 // RegisterClass enums are stored as uint16_t in the tables.
126 assert(RegisterClasses.size() <= 0xffff &&
127 "Too many register classes to fit in tables");
128
129 OS << "\n// Register classes\n\n";
130 if (!Namespace.empty())
131 OS << "namespace " << Namespace << " {\n";
132 OS << "enum {\n";
133 for (const auto &RC : RegisterClasses)
134 OS << " " << RC.getName() << "RegClassID"
135 << " = " << RC.EnumValue << ",\n";
136 OS << "\n };\n";
137 if (!Namespace.empty())
138 OS << "} // end namespace " << Namespace << "\n\n";
139 }
140
141 const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices();
142 // If the only definition is the default NoRegAltName, we don't need to
143 // emit anything.
144 if (RegAltNameIndices.size() > 1) {
145 OS << "\n// Register alternate name indices\n\n";
146 if (!Namespace.empty())
147 OS << "namespace " << Namespace << " {\n";
148 OS << "enum {\n";
149 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
150 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
151 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
152 OS << "};\n";
153 if (!Namespace.empty())
154 OS << "} // end namespace " << Namespace << "\n\n";
155 }
156
157 auto &SubRegIndices = Bank.getSubRegIndices();
158 if (!SubRegIndices.empty()) {
159 OS << "\n// Subregister indices\n\n";
160 std::string Namespace = SubRegIndices.front().getNamespace();
161 if (!Namespace.empty())
162 OS << "namespace " << Namespace << " {\n";
163 OS << "enum {\n NoSubRegister,\n";
164 unsigned i = 0;
165 for (const auto &Idx : SubRegIndices)
166 OS << " " << Idx.getName() << ",\t// " << ++i << "\n";
167 OS << " NUM_TARGET_SUBREGS\n};\n";
168 if (!Namespace.empty())
169 OS << "} // end namespace " << Namespace << "\n\n";
170 }
171
172 OS << "} // end namespace llvm\n\n";
173 OS << "#endif // GET_REGINFO_ENUM\n\n";
174 }
175
printInt(raw_ostream & OS,int Val)176 static void printInt(raw_ostream &OS, int Val) {
177 OS << Val;
178 }
179
getMinimalTypeForRange(uint64_t Range)180 static const char *getMinimalTypeForRange(uint64_t Range) {
181 assert(Range < 0xFFFFFFFFULL && "Enum too large");
182 if (Range > 0xFFFF)
183 return "uint32_t";
184 if (Range > 0xFF)
185 return "uint16_t";
186 return "uint8_t";
187 }
188
189 void RegisterInfoEmitter::
EmitRegUnitPressure(raw_ostream & OS,const CodeGenRegBank & RegBank,const std::string & ClassName)190 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
191 const std::string &ClassName) {
192 unsigned NumRCs = RegBank.getRegClasses().size();
193 unsigned NumSets = RegBank.getNumRegPressureSets();
194
195 OS << "/// Get the weight in units of pressure for this register class.\n"
196 << "const RegClassWeight &" << ClassName << "::\n"
197 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
198 << " static const RegClassWeight RCWeightTable[] = {\n";
199 for (const auto &RC : RegBank.getRegClasses()) {
200 const CodeGenRegister::Vec &Regs = RC.getMembers();
201 if (Regs.empty())
202 OS << " {0, 0";
203 else {
204 std::vector<unsigned> RegUnits;
205 RC.buildRegUnitSet(RegUnits);
206 OS << " {" << (*Regs.begin())->getWeight(RegBank)
207 << ", " << RegBank.getRegUnitSetWeight(RegUnits);
208 }
209 OS << "}, \t// " << RC.getName() << "\n";
210 }
211 OS << " };\n"
212 << " return RCWeightTable[RC->getID()];\n"
213 << "}\n\n";
214
215 // Reasonable targets (not ARMv7) have unit weight for all units, so don't
216 // bother generating a table.
217 bool RegUnitsHaveUnitWeight = true;
218 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
219 UnitIdx < UnitEnd; ++UnitIdx) {
220 if (RegBank.getRegUnit(UnitIdx).Weight > 1)
221 RegUnitsHaveUnitWeight = false;
222 }
223 OS << "/// Get the weight in units of pressure for this register unit.\n"
224 << "unsigned " << ClassName << "::\n"
225 << "getRegUnitWeight(unsigned RegUnit) const {\n"
226 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
227 << " && \"invalid register unit\");\n";
228 if (!RegUnitsHaveUnitWeight) {
229 OS << " static const uint8_t RUWeightTable[] = {\n ";
230 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
231 UnitIdx < UnitEnd; ++UnitIdx) {
232 const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
233 assert(RU.Weight < 256 && "RegUnit too heavy");
234 OS << RU.Weight << ", ";
235 }
236 OS << "};\n"
237 << " return RUWeightTable[RegUnit];\n";
238 }
239 else {
240 OS << " // All register units have unit weight.\n"
241 << " return 1;\n";
242 }
243 OS << "}\n\n";
244
245 OS << "\n"
246 << "// Get the number of dimensions of register pressure.\n"
247 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
248 << " return " << NumSets << ";\n}\n\n";
249
250 OS << "// Get the name of this register unit pressure set.\n"
251 << "const char *" << ClassName << "::\n"
252 << "getRegPressureSetName(unsigned Idx) const {\n"
253 << " static const char *const PressureNameTable[] = {\n";
254 unsigned MaxRegUnitWeight = 0;
255 for (unsigned i = 0; i < NumSets; ++i ) {
256 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
257 MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight);
258 OS << " \"" << RegUnits.Name << "\",\n";
259 }
260 OS << " };\n"
261 << " return PressureNameTable[Idx];\n"
262 << "}\n\n";
263
264 OS << "// Get the register unit pressure limit for this dimension.\n"
265 << "// This limit must be adjusted dynamically for reserved registers.\n"
266 << "unsigned " << ClassName << "::\n"
267 << "getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {\n"
268 << " static const " << getMinimalTypeForRange(MaxRegUnitWeight)
269 << " PressureLimitTable[] = {\n";
270 for (unsigned i = 0; i < NumSets; ++i ) {
271 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
272 OS << " " << RegUnits.Weight << ", \t// " << i << ": "
273 << RegUnits.Name << "\n";
274 }
275 OS << " };\n"
276 << " return PressureLimitTable[Idx];\n"
277 << "}\n\n";
278
279 SequenceToOffsetTable<std::vector<int>> PSetsSeqs;
280
281 // This table may be larger than NumRCs if some register units needed a list
282 // of unit sets that did not correspond to a register class.
283 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();
284 std::vector<std::vector<int>> PSets(NumRCUnitSets);
285
286 for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) {
287 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
288 PSets[i].reserve(PSetIDs.size());
289 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
290 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
291 PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order);
292 }
293 std::sort(PSets[i].begin(), PSets[i].end());
294 PSetsSeqs.add(PSets[i]);
295 }
296
297 PSetsSeqs.layout();
298
299 OS << "/// Table of pressure sets per register class or unit.\n"
300 << "static const int RCSetsTable[] = {\n";
301 PSetsSeqs.emit(OS, printInt, "-1");
302 OS << "};\n\n";
303
304 OS << "/// Get the dimensions of register pressure impacted by this "
305 << "register class.\n"
306 << "/// Returns a -1 terminated array of pressure set IDs\n"
307 << "const int* " << ClassName << "::\n"
308 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
309 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1)
310 << " RCSetStartTable[] = {\n ";
311 for (unsigned i = 0, e = NumRCs; i != e; ++i) {
312 OS << PSetsSeqs.get(PSets[i]) << ",";
313 }
314 OS << "};\n"
315 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n"
316 << "}\n\n";
317
318 OS << "/// Get the dimensions of register pressure impacted by this "
319 << "register unit.\n"
320 << "/// Returns a -1 terminated array of pressure set IDs\n"
321 << "const int* " << ClassName << "::\n"
322 << "getRegUnitPressureSets(unsigned RegUnit) const {\n"
323 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
324 << " && \"invalid register unit\");\n";
325 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1)
326 << " RUSetStartTable[] = {\n ";
327 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
328 UnitIdx < UnitEnd; ++UnitIdx) {
329 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])
330 << ",";
331 }
332 OS << "};\n"
333 << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n"
334 << "}\n\n";
335 }
336
EmitRegMappingTables(raw_ostream & OS,const std::deque<CodeGenRegister> & Regs,bool isCtor)337 void RegisterInfoEmitter::EmitRegMappingTables(
338 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
339 // Collect all information about dwarf register numbers
340 typedef std::map<Record*, std::vector<int64_t>, LessRecordRegister> DwarfRegNumsMapTy;
341 DwarfRegNumsMapTy DwarfRegNums;
342
343 // First, just pull all provided information to the map
344 unsigned maxLength = 0;
345 for (auto &RE : Regs) {
346 Record *Reg = RE.TheDef;
347 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
348 maxLength = std::max((size_t)maxLength, RegNums.size());
349 if (DwarfRegNums.count(Reg))
350 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
351 getQualifiedName(Reg) + "specified multiple times");
352 DwarfRegNums[Reg] = RegNums;
353 }
354
355 if (!maxLength)
356 return;
357
358 // Now we know maximal length of number list. Append -1's, where needed
359 for (DwarfRegNumsMapTy::iterator
360 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
361 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
362 I->second.push_back(-1);
363
364 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
365
366 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
367
368 // Emit reverse information about the dwarf register numbers.
369 for (unsigned j = 0; j < 2; ++j) {
370 for (unsigned i = 0, e = maxLength; i != e; ++i) {
371 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
372 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
373 OS << i << "Dwarf2L[]";
374
375 if (!isCtor) {
376 OS << " = {\n";
377
378 // Store the mapping sorted by the LLVM reg num so lookup can be done
379 // with a binary search.
380 std::map<uint64_t, Record*> Dwarf2LMap;
381 for (DwarfRegNumsMapTy::iterator
382 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
383 int DwarfRegNo = I->second[i];
384 if (DwarfRegNo < 0)
385 continue;
386 Dwarf2LMap[DwarfRegNo] = I->first;
387 }
388
389 for (std::map<uint64_t, Record*>::iterator
390 I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
391 OS << " { " << I->first << "U, " << getQualifiedName(I->second)
392 << " },\n";
393
394 OS << "};\n";
395 } else {
396 OS << ";\n";
397 }
398
399 // We have to store the size in a const global, it's used in multiple
400 // places.
401 OS << "extern const unsigned " << Namespace
402 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
403 if (!isCtor)
404 OS << " = array_lengthof(" << Namespace
405 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
406 << "Dwarf2L);\n\n";
407 else
408 OS << ";\n\n";
409 }
410 }
411
412 for (auto &RE : Regs) {
413 Record *Reg = RE.TheDef;
414 const RecordVal *V = Reg->getValue("DwarfAlias");
415 if (!V || !V->getValue())
416 continue;
417
418 DefInit *DI = cast<DefInit>(V->getValue());
419 Record *Alias = DI->getDef();
420 DwarfRegNums[Reg] = DwarfRegNums[Alias];
421 }
422
423 // Emit information about the dwarf register numbers.
424 for (unsigned j = 0; j < 2; ++j) {
425 for (unsigned i = 0, e = maxLength; i != e; ++i) {
426 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
427 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
428 OS << i << "L2Dwarf[]";
429 if (!isCtor) {
430 OS << " = {\n";
431 // Store the mapping sorted by the Dwarf reg num so lookup can be done
432 // with a binary search.
433 for (DwarfRegNumsMapTy::iterator
434 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
435 int RegNo = I->second[i];
436 if (RegNo == -1) // -1 is the default value, don't emit a mapping.
437 continue;
438
439 OS << " { " << getQualifiedName(I->first) << ", " << RegNo
440 << "U },\n";
441 }
442 OS << "};\n";
443 } else {
444 OS << ";\n";
445 }
446
447 // We have to store the size in a const global, it's used in multiple
448 // places.
449 OS << "extern const unsigned " << Namespace
450 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
451 if (!isCtor)
452 OS << " = array_lengthof(" << Namespace
453 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n";
454 else
455 OS << ";\n\n";
456 }
457 }
458 }
459
EmitRegMapping(raw_ostream & OS,const std::deque<CodeGenRegister> & Regs,bool isCtor)460 void RegisterInfoEmitter::EmitRegMapping(
461 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
462 // Emit the initializer so the tables from EmitRegMappingTables get wired up
463 // to the MCRegisterInfo object.
464 unsigned maxLength = 0;
465 for (auto &RE : Regs) {
466 Record *Reg = RE.TheDef;
467 maxLength = std::max((size_t)maxLength,
468 Reg->getValueAsListOfInts("DwarfNumbers").size());
469 }
470
471 if (!maxLength)
472 return;
473
474 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
475
476 // Emit reverse information about the dwarf register numbers.
477 for (unsigned j = 0; j < 2; ++j) {
478 OS << " switch (";
479 if (j == 0)
480 OS << "DwarfFlavour";
481 else
482 OS << "EHFlavour";
483 OS << ") {\n"
484 << " default:\n"
485 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
486
487 for (unsigned i = 0, e = maxLength; i != e; ++i) {
488 OS << " case " << i << ":\n";
489 OS << " ";
490 if (!isCtor)
491 OS << "RI->";
492 std::string Tmp;
493 raw_string_ostream(Tmp) << Namespace
494 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
495 << "Dwarf2L";
496 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
497 if (j == 0)
498 OS << "false";
499 else
500 OS << "true";
501 OS << ");\n";
502 OS << " break;\n";
503 }
504 OS << " }\n";
505 }
506
507 // Emit information about the dwarf register numbers.
508 for (unsigned j = 0; j < 2; ++j) {
509 OS << " switch (";
510 if (j == 0)
511 OS << "DwarfFlavour";
512 else
513 OS << "EHFlavour";
514 OS << ") {\n"
515 << " default:\n"
516 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
517
518 for (unsigned i = 0, e = maxLength; i != e; ++i) {
519 OS << " case " << i << ":\n";
520 OS << " ";
521 if (!isCtor)
522 OS << "RI->";
523 std::string Tmp;
524 raw_string_ostream(Tmp) << Namespace
525 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
526 << "L2Dwarf";
527 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
528 if (j == 0)
529 OS << "false";
530 else
531 OS << "true";
532 OS << ");\n";
533 OS << " break;\n";
534 }
535 OS << " }\n";
536 }
537 }
538
539 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
540 // Width is the number of bits per hex number.
printBitVectorAsHex(raw_ostream & OS,const BitVector & Bits,unsigned Width)541 static void printBitVectorAsHex(raw_ostream &OS,
542 const BitVector &Bits,
543 unsigned Width) {
544 assert(Width <= 32 && "Width too large");
545 unsigned Digits = (Width + 3) / 4;
546 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
547 unsigned Value = 0;
548 for (unsigned j = 0; j != Width && i + j != e; ++j)
549 Value |= Bits.test(i + j) << j;
550 OS << format("0x%0*x, ", Digits, Value);
551 }
552 }
553
554 // Helper to emit a set of bits into a constant byte array.
555 class BitVectorEmitter {
556 BitVector Values;
557 public:
add(unsigned v)558 void add(unsigned v) {
559 if (v >= Values.size())
560 Values.resize(((v/8)+1)*8); // Round up to the next byte.
561 Values[v] = true;
562 }
563
print(raw_ostream & OS)564 void print(raw_ostream &OS) {
565 printBitVectorAsHex(OS, Values, 8);
566 }
567 };
568
printSimpleValueType(raw_ostream & OS,MVT::SimpleValueType VT)569 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
570 OS << getEnumName(VT);
571 }
572
printSubRegIndex(raw_ostream & OS,const CodeGenSubRegIndex * Idx)573 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
574 OS << Idx->EnumValue;
575 }
576
577 // Differentially encoded register and regunit lists allow for better
578 // compression on regular register banks. The sequence is computed from the
579 // differential list as:
580 //
581 // out[0] = InitVal;
582 // out[n+1] = out[n] + diff[n]; // n = 0, 1, ...
583 //
584 // The initial value depends on the specific list. The list is terminated by a
585 // 0 differential which means we can't encode repeated elements.
586
587 typedef SmallVector<uint16_t, 4> DiffVec;
588 typedef SmallVector<unsigned, 4> MaskVec;
589
590 // Differentially encode a sequence of numbers into V. The starting value and
591 // terminating 0 are not added to V, so it will have the same size as List.
592 static
diffEncode(DiffVec & V,unsigned InitVal,SparseBitVector<> List)593 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, SparseBitVector<> List) {
594 assert(V.empty() && "Clear DiffVec before diffEncode.");
595 uint16_t Val = uint16_t(InitVal);
596
597 for (uint16_t Cur : List) {
598 V.push_back(Cur - Val);
599 Val = Cur;
600 }
601 return V;
602 }
603
604 template<typename Iter>
605 static
diffEncode(DiffVec & V,unsigned InitVal,Iter Begin,Iter End)606 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) {
607 assert(V.empty() && "Clear DiffVec before diffEncode.");
608 uint16_t Val = uint16_t(InitVal);
609 for (Iter I = Begin; I != End; ++I) {
610 uint16_t Cur = (*I)->EnumValue;
611 V.push_back(Cur - Val);
612 Val = Cur;
613 }
614 return V;
615 }
616
printDiff16(raw_ostream & OS,uint16_t Val)617 static void printDiff16(raw_ostream &OS, uint16_t Val) {
618 OS << Val;
619 }
620
printMask(raw_ostream & OS,unsigned Val)621 static void printMask(raw_ostream &OS, unsigned Val) {
622 OS << format("0x%08X", Val);
623 }
624
625 // Try to combine Idx's compose map into Vec if it is compatible.
626 // Return false if it's not possible.
combine(const CodeGenSubRegIndex * Idx,SmallVectorImpl<CodeGenSubRegIndex * > & Vec)627 static bool combine(const CodeGenSubRegIndex *Idx,
628 SmallVectorImpl<CodeGenSubRegIndex*> &Vec) {
629 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites();
630 for (const auto &I : Map) {
631 CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1];
632 if (Entry && Entry != I.second)
633 return false;
634 }
635
636 // All entries are compatible. Make it so.
637 for (const auto &I : Map) {
638 auto *&Entry = Vec[I.first->EnumValue - 1];
639 assert((!Entry || Entry == I.second) &&
640 "Expected EnumValue to be unique");
641 Entry = I.second;
642 }
643 return true;
644 }
645
646 void
emitComposeSubRegIndices(raw_ostream & OS,CodeGenRegBank & RegBank,const std::string & ClName)647 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
648 CodeGenRegBank &RegBank,
649 const std::string &ClName) {
650 const auto &SubRegIndices = RegBank.getSubRegIndices();
651 OS << "unsigned " << ClName
652 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n";
653
654 // Many sub-register indexes are composition-compatible, meaning that
655 //
656 // compose(IdxA, IdxB) == compose(IdxA', IdxB)
657 //
658 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed.
659 // The illegal entries can be use as wildcards to compress the table further.
660
661 // Map each Sub-register index to a compatible table row.
662 SmallVector<unsigned, 4> RowMap;
663 SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows;
664
665 auto SubRegIndicesSize =
666 std::distance(SubRegIndices.begin(), SubRegIndices.end());
667 for (const auto &Idx : SubRegIndices) {
668 unsigned Found = ~0u;
669 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
670 if (combine(&Idx, Rows[r])) {
671 Found = r;
672 break;
673 }
674 }
675 if (Found == ~0u) {
676 Found = Rows.size();
677 Rows.resize(Found + 1);
678 Rows.back().resize(SubRegIndicesSize);
679 combine(&Idx, Rows.back());
680 }
681 RowMap.push_back(Found);
682 }
683
684 // Output the row map if there is multiple rows.
685 if (Rows.size() > 1) {
686 OS << " static const " << getMinimalTypeForRange(Rows.size()) << " RowMap["
687 << SubRegIndicesSize << "] = {\n ";
688 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
689 OS << RowMap[i] << ", ";
690 OS << "\n };\n";
691 }
692
693 // Output the rows.
694 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1)
695 << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n";
696 for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
697 OS << " { ";
698 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
699 if (Rows[r][i])
700 OS << Rows[r][i]->EnumValue << ", ";
701 else
702 OS << "0, ";
703 OS << "},\n";
704 }
705 OS << " };\n\n";
706
707 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n"
708 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n";
709 if (Rows.size() > 1)
710 OS << " return Rows[RowMap[IdxA]][IdxB];\n";
711 else
712 OS << " return Rows[0][IdxB];\n";
713 OS << "}\n\n";
714 }
715
716 void
emitComposeSubRegIndexLaneMask(raw_ostream & OS,CodeGenRegBank & RegBank,const std::string & ClName)717 RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS,
718 CodeGenRegBank &RegBank,
719 const std::string &ClName) {
720 // See the comments in computeSubRegLaneMasks() for our goal here.
721 const auto &SubRegIndices = RegBank.getSubRegIndices();
722
723 // Create a list of Mask+Rotate operations, with equivalent entries merged.
724 SmallVector<unsigned, 4> SubReg2SequenceIndexMap;
725 SmallVector<SmallVector<MaskRolPair, 1>, 4> Sequences;
726 for (const auto &Idx : SubRegIndices) {
727 const SmallVector<MaskRolPair, 1> &IdxSequence
728 = Idx.CompositionLaneMaskTransform;
729
730 unsigned Found = ~0u;
731 unsigned SIdx = 0;
732 unsigned NextSIdx;
733 for (size_t s = 0, se = Sequences.size(); s != se; ++s, SIdx = NextSIdx) {
734 SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s];
735 NextSIdx = SIdx + Sequence.size() + 1;
736 if (Sequence == IdxSequence) {
737 Found = SIdx;
738 break;
739 }
740 }
741 if (Found == ~0u) {
742 Sequences.push_back(IdxSequence);
743 Found = SIdx;
744 }
745 SubReg2SequenceIndexMap.push_back(Found);
746 }
747
748 OS << " struct MaskRolOp {\n"
749 " unsigned Mask;\n"
750 " uint8_t RotateLeft;\n"
751 " };\n"
752 " static const MaskRolOp LaneMaskComposeSequences[] = {\n";
753 unsigned Idx = 0;
754 for (size_t s = 0, se = Sequences.size(); s != se; ++s) {
755 OS << " ";
756 const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s];
757 for (size_t p = 0, pe = Sequence.size(); p != pe; ++p) {
758 const MaskRolPair &P = Sequence[p];
759 OS << format("{ 0x%08X, %2u }, ", P.Mask, P.RotateLeft);
760 }
761 OS << "{ 0, 0 }";
762 if (s+1 != se)
763 OS << ", ";
764 OS << " // Sequence " << Idx << "\n";
765 Idx += Sequence.size() + 1;
766 }
767 OS << " };\n"
768 " static const MaskRolOp *const CompositeSequences[] = {\n";
769 for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) {
770 OS << " ";
771 unsigned Idx = SubReg2SequenceIndexMap[i];
772 OS << format("&LaneMaskComposeSequences[%u]", Idx);
773 if (i+1 != e)
774 OS << ",";
775 OS << " // to " << SubRegIndices[i].getName() << "\n";
776 }
777 OS << " };\n\n";
778
779 OS << "LaneBitmask " << ClName
780 << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)"
781 " const {\n"
782 " --IdxA; assert(IdxA < " << SubRegIndices.size()
783 << " && \"Subregister index out of bounds\");\n"
784 " LaneBitmask Result = 0;\n"
785 " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask != 0; ++Ops)"
786 " {\n"
787 " LaneBitmask Masked = LaneMask & Ops->Mask;\n"
788 " Result |= (Masked << Ops->RotateLeft) & 0xFFFFFFFF;\n"
789 " Result |= (Masked >> ((32 - Ops->RotateLeft) & 0x1F));\n"
790 " }\n"
791 " return Result;\n"
792 "}\n\n";
793
794 OS << "LaneBitmask " << ClName
795 << "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, "
796 " LaneBitmask LaneMask) const {\n"
797 " LaneMask &= getSubRegIndexLaneMask(IdxA);\n"
798 " --IdxA; assert(IdxA < " << SubRegIndices.size()
799 << " && \"Subregister index out of bounds\");\n"
800 " LaneBitmask Result = 0;\n"
801 " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask != 0; ++Ops)"
802 " {\n"
803 " LaneBitmask Rotated = (LaneMask >> Ops->RotateLeft) |\n"
804 " ((LaneMask << ((32 - Ops->RotateLeft) & 0x1F)) & 0xFFFFFFFF);\n"
805 " Result |= Rotated & Ops->Mask;\n"
806 " }\n"
807 " return Result;\n"
808 "}\n\n";
809 }
810
811 //
812 // runMCDesc - Print out MC register descriptions.
813 //
814 void
runMCDesc(raw_ostream & OS,CodeGenTarget & Target,CodeGenRegBank & RegBank)815 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
816 CodeGenRegBank &RegBank) {
817 emitSourceFileHeader("MC Register Information", OS);
818
819 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
820 OS << "#undef GET_REGINFO_MC_DESC\n\n";
821
822 const auto &Regs = RegBank.getRegisters();
823
824 auto &SubRegIndices = RegBank.getSubRegIndices();
825 // The lists of sub-registers and super-registers go in the same array. That
826 // allows us to share suffixes.
827 typedef std::vector<const CodeGenRegister*> RegVec;
828
829 // Differentially encoded lists.
830 SequenceToOffsetTable<DiffVec> DiffSeqs;
831 SmallVector<DiffVec, 4> SubRegLists(Regs.size());
832 SmallVector<DiffVec, 4> SuperRegLists(Regs.size());
833 SmallVector<DiffVec, 4> RegUnitLists(Regs.size());
834 SmallVector<unsigned, 4> RegUnitInitScale(Regs.size());
835
836 // List of lane masks accompanying register unit sequences.
837 SequenceToOffsetTable<MaskVec> LaneMaskSeqs;
838 SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size());
839
840 // Keep track of sub-register names as well. These are not differentially
841 // encoded.
842 typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec;
843 SequenceToOffsetTable<SubRegIdxVec, deref<llvm::less>> SubRegIdxSeqs;
844 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
845
846 SequenceToOffsetTable<std::string> RegStrings;
847
848 // Precompute register lists for the SequenceToOffsetTable.
849 unsigned i = 0;
850 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) {
851 const auto &Reg = *I;
852 RegStrings.add(Reg.getName());
853
854 // Compute the ordered sub-register list.
855 SetVector<const CodeGenRegister*> SR;
856 Reg.addSubRegsPreOrder(SR, RegBank);
857 diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end());
858 DiffSeqs.add(SubRegLists[i]);
859
860 // Compute the corresponding sub-register indexes.
861 SubRegIdxVec &SRIs = SubRegIdxLists[i];
862 for (unsigned j = 0, je = SR.size(); j != je; ++j)
863 SRIs.push_back(Reg.getSubRegIndex(SR[j]));
864 SubRegIdxSeqs.add(SRIs);
865
866 // Super-registers are already computed.
867 const RegVec &SuperRegList = Reg.getSuperRegs();
868 diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(),
869 SuperRegList.end());
870 DiffSeqs.add(SuperRegLists[i]);
871
872 // Differentially encode the register unit list, seeded by register number.
873 // First compute a scale factor that allows more diff-lists to be reused:
874 //
875 // D0 -> (S0, S1)
876 // D1 -> (S2, S3)
877 //
878 // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial
879 // value for the differential decoder is the register number multiplied by
880 // the scale.
881 //
882 // Check the neighboring registers for arithmetic progressions.
883 unsigned ScaleA = ~0u, ScaleB = ~0u;
884 SparseBitVector<> RUs = Reg.getNativeRegUnits();
885 if (I != Regs.begin() &&
886 std::prev(I)->getNativeRegUnits().count() == RUs.count())
887 ScaleB = *RUs.begin() - *std::prev(I)->getNativeRegUnits().begin();
888 if (std::next(I) != Regs.end() &&
889 std::next(I)->getNativeRegUnits().count() == RUs.count())
890 ScaleA = *std::next(I)->getNativeRegUnits().begin() - *RUs.begin();
891 unsigned Scale = std::min(ScaleB, ScaleA);
892 // Default the scale to 0 if it can't be encoded in 4 bits.
893 if (Scale >= 16)
894 Scale = 0;
895 RegUnitInitScale[i] = Scale;
896 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs));
897
898 const auto &RUMasks = Reg.getRegUnitLaneMasks();
899 MaskVec &LaneMaskVec = RegUnitLaneMasks[i];
900 assert(LaneMaskVec.empty());
901 LaneMaskVec.insert(LaneMaskVec.begin(), RUMasks.begin(), RUMasks.end());
902 // Terminator mask should not be used inside of the list.
903 #ifndef NDEBUG
904 for (unsigned M : LaneMaskVec) {
905 assert(M != ~0u && "terminator mask should not be part of the list");
906 }
907 #endif
908 LaneMaskSeqs.add(LaneMaskVec);
909 }
910
911 // Compute the final layout of the sequence table.
912 DiffSeqs.layout();
913 LaneMaskSeqs.layout();
914 SubRegIdxSeqs.layout();
915
916 OS << "namespace llvm {\n\n";
917
918 const std::string &TargetName = Target.getName();
919
920 // Emit the shared table of differential lists.
921 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n";
922 DiffSeqs.emit(OS, printDiff16);
923 OS << "};\n\n";
924
925 // Emit the shared table of regunit lane mask sequences.
926 OS << "extern const unsigned " << TargetName << "LaneMaskLists[] = {\n";
927 LaneMaskSeqs.emit(OS, printMask, "~0u");
928 OS << "};\n\n";
929
930 // Emit the table of sub-register indexes.
931 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";
932 SubRegIdxSeqs.emit(OS, printSubRegIndex);
933 OS << "};\n\n";
934
935 // Emit the table of sub-register index sizes.
936 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
937 << TargetName << "SubRegIdxRanges[] = {\n";
938 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
939 for (const auto &Idx : SubRegIndices) {
940 OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// "
941 << Idx.getName() << "\n";
942 }
943 OS << "};\n\n";
944
945 // Emit the string table.
946 RegStrings.layout();
947 OS << "extern const char " << TargetName << "RegStrings[] = {\n";
948 RegStrings.emit(OS, printChar);
949 OS << "};\n\n";
950
951 OS << "extern const MCRegisterDesc " << TargetName
952 << "RegDesc[] = { // Descriptors\n";
953 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n";
954
955 // Emit the register descriptors now.
956 i = 0;
957 for (const auto &Reg : Regs) {
958 OS << " { " << RegStrings.get(Reg.getName()) << ", "
959 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i])
960 << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", "
961 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", "
962 << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << " },\n";
963 ++i;
964 }
965 OS << "};\n\n"; // End of register descriptors...
966
967 // Emit the table of register unit roots. Each regunit has one or two root
968 // registers.
969 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n";
970 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
971 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();
972 assert(!Roots.empty() && "All regunits must have a root register.");
973 assert(Roots.size() <= 2 && "More than two roots not supported yet.");
974 OS << " { " << getQualifiedName(Roots.front()->TheDef);
975 for (unsigned r = 1; r != Roots.size(); ++r)
976 OS << ", " << getQualifiedName(Roots[r]->TheDef);
977 OS << " },\n";
978 }
979 OS << "};\n\n";
980
981 const auto &RegisterClasses = RegBank.getRegClasses();
982
983 // Loop over all of the register classes... emitting each one.
984 OS << "namespace { // Register classes...\n";
985
986 SequenceToOffsetTable<std::string> RegClassStrings;
987
988 // Emit the register enum value arrays for each RegisterClass
989 for (const auto &RC : RegisterClasses) {
990 ArrayRef<Record*> Order = RC.getOrder();
991
992 // Give the register class a legal C name if it's anonymous.
993 const std::string &Name = RC.getName();
994
995 RegClassStrings.add(Name);
996
997 // Emit the register list now.
998 OS << " // " << Name << " Register Class...\n"
999 << " const MCPhysReg " << Name
1000 << "[] = {\n ";
1001 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
1002 Record *Reg = Order[i];
1003 OS << getQualifiedName(Reg) << ", ";
1004 }
1005 OS << "\n };\n\n";
1006
1007 OS << " // " << Name << " Bit set.\n"
1008 << " const uint8_t " << Name
1009 << "Bits[] = {\n ";
1010 BitVectorEmitter BVE;
1011 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
1012 Record *Reg = Order[i];
1013 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
1014 }
1015 BVE.print(OS);
1016 OS << "\n };\n\n";
1017
1018 }
1019 OS << "} // end anonymous namespace\n\n";
1020
1021 RegClassStrings.layout();
1022 OS << "extern const char " << TargetName << "RegClassStrings[] = {\n";
1023 RegClassStrings.emit(OS, printChar);
1024 OS << "};\n\n";
1025
1026 OS << "extern const MCRegisterClass " << TargetName
1027 << "MCRegisterClasses[] = {\n";
1028
1029 for (const auto &RC : RegisterClasses) {
1030 // Asserts to make sure values will fit in table assuming types from
1031 // MCRegisterInfo.h
1032 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
1033 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
1034 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
1035
1036 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, "
1037 << RegClassStrings.get(RC.getName()) << ", "
1038 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
1039 << RC.getQualifiedName() + "RegClassID" << ", "
1040 << RC.SpillSize/8 << ", "
1041 << RC.SpillAlignment/8 << ", "
1042 << RC.CopyCost << ", "
1043 << ( RC.Allocatable ? "true" : "false" ) << " },\n";
1044 }
1045
1046 OS << "};\n\n";
1047
1048 EmitRegMappingTables(OS, Regs, false);
1049
1050 // Emit Reg encoding table
1051 OS << "extern const uint16_t " << TargetName;
1052 OS << "RegEncodingTable[] = {\n";
1053 // Add entry for NoRegister
1054 OS << " 0,\n";
1055 for (const auto &RE : Regs) {
1056 Record *Reg = RE.TheDef;
1057 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding");
1058 uint64_t Value = 0;
1059 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
1060 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b)))
1061 Value |= (uint64_t)B->getValue() << b;
1062 }
1063 OS << " " << Value << ",\n";
1064 }
1065 OS << "};\n"; // End of HW encoding table
1066
1067 // MCRegisterInfo initialization routine.
1068 OS << "static inline void Init" << TargetName
1069 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
1070 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) "
1071 "{\n"
1072 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
1073 << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
1074 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, "
1075 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "
1076 << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, "
1077 << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, "
1078 << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n"
1079 << TargetName << "SubRegIdxRanges, " << TargetName
1080 << "RegEncodingTable);\n\n";
1081
1082 EmitRegMapping(OS, Regs, false);
1083
1084 OS << "}\n\n";
1085
1086 OS << "} // end namespace llvm\n\n";
1087 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
1088 }
1089
1090 void
runTargetHeader(raw_ostream & OS,CodeGenTarget & Target,CodeGenRegBank & RegBank)1091 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
1092 CodeGenRegBank &RegBank) {
1093 emitSourceFileHeader("Register Information Header Fragment", OS);
1094
1095 OS << "\n#ifdef GET_REGINFO_HEADER\n";
1096 OS << "#undef GET_REGINFO_HEADER\n\n";
1097
1098 const std::string &TargetName = Target.getName();
1099 std::string ClassName = TargetName + "GenRegisterInfo";
1100
1101 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
1102
1103 OS << "namespace llvm {\n\n";
1104
1105 OS << "class " << TargetName << "FrameLowering;\n\n";
1106
1107 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
1108 << " explicit " << ClassName
1109 << "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n";
1110 if (!RegBank.getSubRegIndices().empty()) {
1111 OS << " unsigned composeSubRegIndicesImpl"
1112 << "(unsigned, unsigned) const override;\n"
1113 << " LaneBitmask composeSubRegIndexLaneMaskImpl"
1114 << "(unsigned, LaneBitmask) const override;\n"
1115 << " LaneBitmask reverseComposeSubRegIndexLaneMaskImpl"
1116 << "(unsigned, LaneBitmask) const override;\n"
1117 << " const TargetRegisterClass *getSubClassWithSubReg"
1118 << "(const TargetRegisterClass*, unsigned) const override;\n";
1119 }
1120 OS << " const RegClassWeight &getRegClassWeight("
1121 << "const TargetRegisterClass *RC) const override;\n"
1122 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n"
1123 << " unsigned getNumRegPressureSets() const override;\n"
1124 << " const char *getRegPressureSetName(unsigned Idx) const override;\n"
1125 << " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned "
1126 "Idx) const override;\n"
1127 << " const int *getRegClassPressureSets("
1128 << "const TargetRegisterClass *RC) const override;\n"
1129 << " const int *getRegUnitPressureSets("
1130 << "unsigned RegUnit) const override;\n"
1131 << " ArrayRef<const char *> getRegMaskNames() const override;\n"
1132 << " ArrayRef<const uint32_t *> getRegMasks() const override;\n"
1133 << " /// Devirtualized TargetFrameLowering.\n"
1134 << " static const " << TargetName << "FrameLowering *getFrameLowering(\n"
1135 << " const MachineFunction &MF);\n"
1136 << "};\n\n";
1137
1138 const auto &RegisterClasses = RegBank.getRegClasses();
1139
1140 if (!RegisterClasses.empty()) {
1141 OS << "namespace " << RegisterClasses.front().Namespace
1142 << " { // Register classes\n";
1143
1144 for (const auto &RC : RegisterClasses) {
1145 const std::string &Name = RC.getName();
1146
1147 // Output the extern for the instance.
1148 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
1149 }
1150 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n";
1151 }
1152 OS << "} // end namespace llvm\n\n";
1153 OS << "#endif // GET_REGINFO_HEADER\n\n";
1154 }
1155
1156 //
1157 // runTargetDesc - Output the target register and register file descriptions.
1158 //
1159 void
runTargetDesc(raw_ostream & OS,CodeGenTarget & Target,CodeGenRegBank & RegBank)1160 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
1161 CodeGenRegBank &RegBank){
1162 emitSourceFileHeader("Target Register and Register Classes Information", OS);
1163
1164 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
1165 OS << "#undef GET_REGINFO_TARGET_DESC\n\n";
1166
1167 OS << "namespace llvm {\n\n";
1168
1169 // Get access to MCRegisterClass data.
1170 OS << "extern const MCRegisterClass " << Target.getName()
1171 << "MCRegisterClasses[];\n";
1172
1173 // Start out by emitting each of the register classes.
1174 const auto &RegisterClasses = RegBank.getRegClasses();
1175 const auto &SubRegIndices = RegBank.getSubRegIndices();
1176
1177 // Collect all registers belonging to any allocatable class.
1178 std::set<Record*> AllocatableRegs;
1179
1180 // Collect allocatable registers.
1181 for (const auto &RC : RegisterClasses) {
1182 ArrayRef<Record*> Order = RC.getOrder();
1183
1184 if (RC.Allocatable)
1185 AllocatableRegs.insert(Order.begin(), Order.end());
1186 }
1187
1188 // Build a shared array of value types.
1189 SequenceToOffsetTable<SmallVector<MVT::SimpleValueType, 4> > VTSeqs;
1190 for (const auto &RC : RegisterClasses)
1191 VTSeqs.add(RC.VTs);
1192 VTSeqs.layout();
1193 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
1194 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
1195 OS << "};\n";
1196
1197 // Emit SubRegIndex names, skipping 0.
1198 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \"";
1199
1200 for (const auto &Idx : SubRegIndices) {
1201 OS << Idx.getName();
1202 OS << "\", \"";
1203 }
1204 OS << "\" };\n\n";
1205
1206 // Emit SubRegIndex lane masks, including 0.
1207 OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n";
1208 for (const auto &Idx : SubRegIndices) {
1209 OS << format(" 0x%08x, // ", Idx.LaneMask) << Idx.getName() << '\n';
1210 }
1211 OS << " };\n\n";
1212
1213 OS << "\n";
1214
1215 // Now that all of the structs have been emitted, emit the instances.
1216 if (!RegisterClasses.empty()) {
1217 OS << "\nstatic const TargetRegisterClass *const "
1218 << "NullRegClasses[] = { nullptr };\n\n";
1219
1220 // Emit register class bit mask tables. The first bit mask emitted for a
1221 // register class, RC, is the set of sub-classes, including RC itself.
1222 //
1223 // If RC has super-registers, also create a list of subreg indices and bit
1224 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass,
1225 // SuperRC, that satisfies:
1226 //
1227 // For all SuperReg in SuperRC: SuperReg:Idx in RC
1228 //
1229 // The 0-terminated list of subreg indices starts at:
1230 //
1231 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
1232 //
1233 // The corresponding bitmasks follow the sub-class mask in memory. Each
1234 // mask has RCMaskWords uint32_t entries.
1235 //
1236 // Every bit mask present in the list has at least one bit set.
1237
1238 // Compress the sub-reg index lists.
1239 typedef std::vector<const CodeGenSubRegIndex*> IdxList;
1240 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
1241 SequenceToOffsetTable<IdxList, deref<llvm::less>> SuperRegIdxSeqs;
1242 BitVector MaskBV(RegisterClasses.size());
1243
1244 for (const auto &RC : RegisterClasses) {
1245 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n ";
1246 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
1247
1248 // Emit super-reg class masks for any relevant SubRegIndices that can
1249 // project into RC.
1250 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue];
1251 for (auto &Idx : SubRegIndices) {
1252 MaskBV.reset();
1253 RC.getSuperRegClasses(&Idx, MaskBV);
1254 if (MaskBV.none())
1255 continue;
1256 SRIList.push_back(&Idx);
1257 OS << "\n ";
1258 printBitVectorAsHex(OS, MaskBV, 32);
1259 OS << "// " << Idx.getName();
1260 }
1261 SuperRegIdxSeqs.add(SRIList);
1262 OS << "\n};\n\n";
1263 }
1264
1265 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";
1266 SuperRegIdxSeqs.layout();
1267 SuperRegIdxSeqs.emit(OS, printSubRegIndex);
1268 OS << "};\n\n";
1269
1270 // Emit NULL terminated super-class lists.
1271 for (const auto &RC : RegisterClasses) {
1272 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
1273
1274 // Skip classes without supers. We can reuse NullRegClasses.
1275 if (Supers.empty())
1276 continue;
1277
1278 OS << "static const TargetRegisterClass *const "
1279 << RC.getName() << "Superclasses[] = {\n";
1280 for (const auto *Super : Supers)
1281 OS << " &" << Super->getQualifiedName() << "RegClass,\n";
1282 OS << " nullptr\n};\n\n";
1283 }
1284
1285 // Emit methods.
1286 for (const auto &RC : RegisterClasses) {
1287 if (!RC.AltOrderSelect.empty()) {
1288 OS << "\nstatic inline unsigned " << RC.getName()
1289 << "AltOrderSelect(const MachineFunction &MF) {"
1290 << RC.AltOrderSelect << "}\n\n"
1291 << "static ArrayRef<MCPhysReg> " << RC.getName()
1292 << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
1293 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
1294 ArrayRef<Record*> Elems = RC.getOrder(oi);
1295 if (!Elems.empty()) {
1296 OS << " static const MCPhysReg AltOrder" << oi << "[] = {";
1297 for (unsigned elem = 0; elem != Elems.size(); ++elem)
1298 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
1299 OS << " };\n";
1300 }
1301 }
1302 OS << " const MCRegisterClass &MCR = " << Target.getName()
1303 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
1304 << " const ArrayRef<MCPhysReg> Order[] = {\n"
1305 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
1306 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
1307 if (RC.getOrder(oi).empty())
1308 OS << "),\n ArrayRef<MCPhysReg>(";
1309 else
1310 OS << "),\n makeArrayRef(AltOrder" << oi;
1311 OS << ")\n };\n const unsigned Select = " << RC.getName()
1312 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
1313 << ");\n return Order[Select];\n}\n";
1314 }
1315 }
1316
1317 // Now emit the actual value-initialized register class instances.
1318 OS << "\nnamespace " << RegisterClasses.front().Namespace
1319 << " { // Register class instances\n";
1320
1321 for (const auto &RC : RegisterClasses) {
1322 OS << " extern const TargetRegisterClass " << RC.getName()
1323 << "RegClass = {\n " << '&' << Target.getName()
1324 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n "
1325 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n " << RC.getName()
1326 << "SubClassMask,\n SuperRegIdxSeqs + "
1327 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n "
1328 << format("0x%08x,\n ", RC.LaneMask)
1329 << (unsigned)RC.AllocationPriority << ",\n "
1330 << (RC.HasDisjunctSubRegs?"true":"false")
1331 << ", /* HasDisjunctSubRegs */\n "
1332 << (RC.CoveredBySubRegs?"true":"false")
1333 << ", /* CoveredBySubRegs */\n ";
1334 if (RC.getSuperClasses().empty())
1335 OS << "NullRegClasses,\n ";
1336 else
1337 OS << RC.getName() << "Superclasses,\n ";
1338 if (RC.AltOrderSelect.empty())
1339 OS << "nullptr\n";
1340 else
1341 OS << RC.getName() << "GetRawAllocationOrder\n";
1342 OS << " };\n\n";
1343 }
1344
1345 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n";
1346 }
1347
1348 OS << "\nnamespace {\n";
1349 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
1350 for (const auto &RC : RegisterClasses)
1351 OS << " &" << RC.getQualifiedName() << "RegClass,\n";
1352 OS << " };\n";
1353 OS << "} // end anonymous namespace\n";
1354
1355 // Emit extra information about registers.
1356 const std::string &TargetName = Target.getName();
1357 OS << "\nstatic const TargetRegisterInfoDesc "
1358 << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
1359 OS << " { 0, false },\n";
1360
1361 const auto &Regs = RegBank.getRegisters();
1362 for (const auto &Reg : Regs) {
1363 OS << " { ";
1364 OS << Reg.CostPerUse << ", "
1365 << ( AllocatableRegs.count(Reg.TheDef) != 0 ? "true" : "false" )
1366 << " },\n";
1367 }
1368 OS << "};\n"; // End of register descriptors...
1369
1370
1371 std::string ClassName = Target.getName() + "GenRegisterInfo";
1372
1373 auto SubRegIndicesSize =
1374 std::distance(SubRegIndices.begin(), SubRegIndices.end());
1375
1376 if (!SubRegIndices.empty()) {
1377 emitComposeSubRegIndices(OS, RegBank, ClassName);
1378 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName);
1379 }
1380
1381 // Emit getSubClassWithSubReg.
1382 if (!SubRegIndices.empty()) {
1383 OS << "const TargetRegisterClass *" << ClassName
1384 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
1385 << " const {\n";
1386 // Use the smallest type that can hold a regclass ID with room for a
1387 // sentinel.
1388 if (RegisterClasses.size() < UINT8_MAX)
1389 OS << " static const uint8_t Table[";
1390 else if (RegisterClasses.size() < UINT16_MAX)
1391 OS << " static const uint16_t Table[";
1392 else
1393 PrintFatalError("Too many register classes.");
1394 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n";
1395 for (const auto &RC : RegisterClasses) {
1396 OS << " {\t// " << RC.getName() << "\n";
1397 for (auto &Idx : SubRegIndices) {
1398 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx))
1399 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName()
1400 << " -> " << SRC->getName() << "\n";
1401 else
1402 OS << " 0,\t// " << Idx.getName() << "\n";
1403 }
1404 OS << " },\n";
1405 }
1406 OS << " };\n assert(RC && \"Missing regclass\");\n"
1407 << " if (!Idx) return RC;\n --Idx;\n"
1408 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n"
1409 << " unsigned TV = Table[RC->getID()][Idx];\n"
1410 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
1411 }
1412
1413 EmitRegUnitPressure(OS, RegBank, ClassName);
1414
1415 // Emit the constructor of the class...
1416 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
1417 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";
1418 OS << "extern const unsigned " << TargetName << "LaneMaskLists[];\n";
1419 OS << "extern const char " << TargetName << "RegStrings[];\n";
1420 OS << "extern const char " << TargetName << "RegClassStrings[];\n";
1421 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
1422 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
1423 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
1424 << TargetName << "SubRegIdxRanges[];\n";
1425 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
1426
1427 EmitRegMappingTables(OS, Regs, true);
1428
1429 OS << ClassName << "::\n" << ClassName
1430 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n"
1431 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
1432 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
1433 << " SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0x";
1434 OS.write_hex(RegBank.CoveringLanes);
1435 OS << ") {\n"
1436 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1
1437 << ", RA, PC,\n " << TargetName
1438 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
1439 << " " << TargetName << "RegUnitRoots,\n"
1440 << " " << RegBank.getNumNativeRegUnits() << ",\n"
1441 << " " << TargetName << "RegDiffLists,\n"
1442 << " " << TargetName << "LaneMaskLists,\n"
1443 << " " << TargetName << "RegStrings,\n"
1444 << " " << TargetName << "RegClassStrings,\n"
1445 << " " << TargetName << "SubRegIdxLists,\n"
1446 << " " << SubRegIndicesSize + 1 << ",\n"
1447 << " " << TargetName << "SubRegIdxRanges,\n"
1448 << " " << TargetName << "RegEncodingTable);\n\n";
1449
1450 EmitRegMapping(OS, Regs, true);
1451
1452 OS << "}\n\n";
1453
1454 // Emit CalleeSavedRegs information.
1455 std::vector<Record*> CSRSets =
1456 Records.getAllDerivedDefinitions("CalleeSavedRegs");
1457 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
1458 Record *CSRSet = CSRSets[i];
1459 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1460 assert(Regs && "Cannot expand CalleeSavedRegs instance");
1461
1462 // Emit the *_SaveList list of callee-saved registers.
1463 OS << "static const MCPhysReg " << CSRSet->getName()
1464 << "_SaveList[] = { ";
1465 for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1466 OS << getQualifiedName((*Regs)[r]) << ", ";
1467 OS << "0 };\n";
1468
1469 // Emit the *_RegMask bit mask of call-preserved registers.
1470 BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
1471
1472 // Check for an optional OtherPreserved set.
1473 // Add those registers to RegMask, but not to SaveList.
1474 if (DagInit *OPDag =
1475 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) {
1476 SetTheory::RecSet OPSet;
1477 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
1478 Covered |= RegBank.computeCoveredRegisters(
1479 ArrayRef<Record*>(OPSet.begin(), OPSet.end()));
1480 }
1481
1482 OS << "static const uint32_t " << CSRSet->getName()
1483 << "_RegMask[] = { ";
1484 printBitVectorAsHex(OS, Covered, 32);
1485 OS << "};\n";
1486 }
1487 OS << "\n\n";
1488
1489 OS << "ArrayRef<const uint32_t *> " << ClassName
1490 << "::getRegMasks() const {\n";
1491 if (!CSRSets.empty()) {
1492 OS << " static const uint32_t *const Masks[] = {\n";
1493 for (Record *CSRSet : CSRSets)
1494 OS << " " << CSRSet->getName() << "_RegMask,\n";
1495 OS << " };\n";
1496 OS << " return makeArrayRef(Masks);\n";
1497 } else {
1498 OS << " return None;\n";
1499 }
1500 OS << "}\n\n";
1501
1502 OS << "ArrayRef<const char *> " << ClassName
1503 << "::getRegMaskNames() const {\n";
1504 if (!CSRSets.empty()) {
1505 OS << " static const char *const Names[] = {\n";
1506 for (Record *CSRSet : CSRSets)
1507 OS << " " << '"' << CSRSet->getName() << '"' << ",\n";
1508 OS << " };\n";
1509 OS << " return makeArrayRef(Names);\n";
1510 } else {
1511 OS << " return None;\n";
1512 }
1513 OS << "}\n\n";
1514
1515 OS << "const " << TargetName << "FrameLowering *\n" << TargetName
1516 << "GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {\n"
1517 << " return static_cast<const " << TargetName << "FrameLowering *>(\n"
1518 << " MF.getSubtarget().getFrameLowering());\n"
1519 << "}\n\n";
1520
1521 OS << "} // end namespace llvm\n\n";
1522 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1523 }
1524
run(raw_ostream & OS)1525 void RegisterInfoEmitter::run(raw_ostream &OS) {
1526 CodeGenTarget Target(Records);
1527 CodeGenRegBank &RegBank = Target.getRegBank();
1528 RegBank.computeDerivedInfo();
1529
1530 runEnums(OS, Target, RegBank);
1531 runMCDesc(OS, Target, RegBank);
1532 runTargetHeader(OS, Target, RegBank);
1533 runTargetDesc(OS, Target, RegBank);
1534 }
1535
1536 namespace llvm {
1537
EmitRegisterInfo(RecordKeeper & RK,raw_ostream & OS)1538 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) {
1539 RegisterInfoEmitter(RK).run(OS);
1540 }
1541
1542 } // end namespace llvm
1543