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Searched refs:Rss (Results 1 – 15 of 15) sorted by relevance

/external/chromium-trace/catapult/telemetry/telemetry/internal/testing/
Dsmaps3 Rss: 584 kB
18 Rss: 4 kB
33 Rss: 24 kB
48 Rss: 44 kB
63 Rss: 3116 kB
78 Rss: 52 kB
93 Rss: 0 kB
108 Rss: 4 kB
123 Rss: 4 kB
138 Rss: 28 kB
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/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinRegisterInfo.td59 multiclass Rss<bits<3> group, bits<3> num, string n> {
90 defm R0 : Rss<0, 0, "r0">;
92 defm R1 : Rss<0, 1, "r1">;
94 defm R2 : Rss<0, 2, "r2">;
96 defm R3 : Rss<0, 3, "r3">;
98 defm R4 : Rss<0, 4, "r4">;
100 defm R5 : Rss<0, 5, "r5">;
102 defm R6 : Rss<0, 6, "r6">;
104 defm R7 : Rss<0, 7, "r7">;
108 defm P0 : Rss<1, 0, "p0">;
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/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV3.td201 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
202 "$Rdd = vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, []> {
204 bits<5> Rss;
211 let Inst{20-16} = Rss;
223 : MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
224 "$Rdd=vrcmpys($Rss,$Rt):<<1:sat">;
230 (ins DoubleRegs:$_src_, DoubleRegs:$Rss, DoubleRegs:$Rtt),
231 "$Rxx += vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, [],
234 bits<5> Rss;
241 let Inst{20-16} = Rss;
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DHexagonInstrInfoV5.td18 //Rdd[+]=vrmpybsu(Rss,Rtt)
23 //Rdd[+]=vrmpybu(Rss,Rtt)
41 // Rd=vaddhub(Rss,Rtt):sat
127 def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
128 "$Rd = popcount($Rss)",
129 [(set I32:$Rd, (HexagonPOPCOUNT I64:$Rss))], "", S_2op_tc_2_SLOT23>,
132 bits<5> Rss;
139 let Inst{20-16} = Rss;
438 // Rss <= Rtt -> Rtt >= Rss.
510 // Rss <= Rtt -> Rtt >= Rss.
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DHexagonIntrinsicsV4.td16 //Rdd=vrmpyweh(Rss,Rtt)[:<<1]
20 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
24 //Rdd+=vrmpyweh(Rss,Rtt)[:<<1]
28 //Rdd=vrmpywoh(Rss,Rtt)[:<<1]
53 //Rxx^=asr(Rss,Rt)
55 //Rxx^=asl(Rss,Rt)
57 //Rxx^=lsr(Rss,Rt)
59 //Rxx^=lsl(Rss,Rt)
146 // Rdd=vcnegh(Rss,Rt)
174 // Rxx+=vrcrotate(Rss,Rt,#u2)
DHexagonIntrinsicsV5.td10 //Rdd[+]=vrmpybsu(Rss,Rtt)
11 //Rdd[+]=vrmpybuu(Rss,Rtt)
20 //Rxx+=vdmpybsu(Rss,Rtt):sat
32 // Rd=vaddhub(Rss,Rtt):sat
DHexagonInstrInfo.td857 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
858 "$Rdd = "#opc#"($Rss, $Rtt)"#!if(isRnd, ":rnd", "")
863 bits<5> Rss;
870 let Inst{20-16} = !if (SwapOps, Rtt, Rss);
871 let Inst{12-8} = !if (SwapOps, Rss, Rtt);
877 // Rdd=vadd[u][bhw](Rss,Rtt)
884 // Rdd=vadd[u][bhw](Rss,Rtt):sat
893 // Rdd=vavg[u][bhw](Rss,Rtt)
902 // Rdd=vavg[u][bhw](Rss,Rtt)[:rnd|:crnd]
912 // Rdd=vnavg[bh](Rss,Rtt)
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DHexagonInstrInfoV4.td1955 // Rdd=add(Rss,Rtt,Px):carry
1957 // Rdd=sub(Rss,Rtt,Px):carry
1960 // Rdd=extract(Rss,#u6,#U6)
1961 // Rdd=extract(Rss,Rtt)
1992 // Rxx^=xor(Rss,Rtt)
1996 (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
1997 "$Rxx ^= xor($Rss, $Rtt)",
1999 (xor (i64 DoubleRegs:$dst2), (xor (i64 DoubleRegs:$Rss),
2003 bits<5> Rss;
2009 let Inst{20-16} = Rss;
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DHexagonIntrinsics.td412 // Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
416 // Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
420 // Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat
424 // Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
428 //Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat
434 //Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat
440 //Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat
446 //Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat
456 // Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt)
460 // Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss)
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DHexagonSelectCCInfo.td96 // selectcc(Rss, Rdd, tval, fval, cond) ->
97 // combine(mux(cmp_cond(Rss, Rdd), tval.hi, fval.hi),
98 // mux(cmp_cond(Rss, Rdd), tval.lo, fval.lo))
DHexagonInstrInfoVector.td97 : Pat <(Op Type:$Rss, Type:$Rtt),
98 (MI Type:$Rss, Type:$Rtt)>;
320 // Map from vcmpne(Rss) -> !vcmpew(Rss).
DHexagonInstrAlias.td448 def : InstAlias<"$Rdd = vaddb($Rss, $Rtt)",
449 (A2_vaddub DoubleRegs:$Rdd, DoubleRegs:$Rss, DoubleRegs:$Rtt), 1>;
451 def : InstAlias<"$Rdd = vsubb($Rss,$Rtt)",
452 (A2_vsubub DoubleRegs:$Rdd, DoubleRegs:$Rss, DoubleRegs:$Rtt), 0>;
DHexagonInstrInfoV60.td2180 // defm S2_cabacencbin : _VV <"Rdd=encbin(Rss,$src2,Pu)">, S2_cabacencbin_enc;
/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1964 MCOperand &Rss = Inst.getOperand(1); in processInstruction() local
1972 unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg()); in processInstruction()
1975 Rss.setReg(matchRegister(Reg1)); in processInstruction()
1981 TmpInst.addOperand(Rss); in processInstruction()
2054 MCOperand &Rss = Inst.getOperand(2); in processInstruction() local
2073 TmpInst.addOperand(Rss); in processInstruction()
2118 MCOperand &Rss = Inst.getOperand(1); in processInstruction() local
2126 unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg()); in processInstruction()
2129 Rss.setReg(matchRegister(Reg1)); in processInstruction()
2135 TmpInst.addOperand(Rss); in processInstruction()
/external/chromium-trace/catapult/devil/docs/
Ddevice_utils.md929 Size, Rss, Pss, Shared_Clean, Shared_Dirty, Private_Clean,