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Searched refs:SCALAR_TO_VECTOR (Results 1 – 25 of 36) sorted by relevance

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/external/llvm/test/CodeGen/AArch64/
Dbitcast.ll3 ; PR23065: SCALAR_TO_VECTOR implies the top elements 1 to N-1 of the N-element vector are undefined.
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h300 SCALAR_TO_VECTOR, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h316 SCALAR_TO_VECTOR, enumerator
/external/llvm/test/CodeGen/AMDGPU/
Dscalar_to_vector.ll32 ; Getting a SCALAR_TO_VECTOR seems to be tricky. These cases managed
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelLowering.cpp775 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); in X86TargetLowering()
776 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); in X86TargetLowering()
777 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); in X86TargetLowering()
778 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); in X86TargetLowering()
838 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); in X86TargetLowering()
839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); in X86TargetLowering()
1072 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); in X86TargetLowering()
1461 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, in LowerReturn()
2137 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); in LowerCall()
4212 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) in isScalarLoadToVector()
[all …]
DX86ISelDAGToDAG.cpp1182 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) { in SelectScalarSSELoad()
1199 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR && in SelectScalarSSELoad()
DX86GenDAGISel.inc5845 /*12842*/ OPC_SwitchOpcode /*3 cases */, 103|128,1/*231*/, TARGET_VAL(ISD::SCALAR_TO_VECTOR),/…
6167 /*13526*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
6258 /*SwitchOpcode*/ 43|128,1/*171*/, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->13902
6443 /*14190*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
6521 /*14370*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
12496 /*26029*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
12528 /*SwitchOpcode*/ 60, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->26156
12610 /*26257*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
12642 /*SwitchOpcode*/ 60, TARGET_VAL(ISD::SCALAR_TO_VECTOR),// ->26384
12724 /*26485*/ OPC_CheckOpcode, TARGET_VAL(ISD::SCALAR_TO_VECTOR),
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DREADME_ALTIVEC.txt61 We currently codegen SCALAR_TO_VECTOR as a store of the scalar to a 16-byte
DPPCISelLowering.cpp332 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); in PPCTargetLowering()
360 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
361 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
4545 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); in LowerOperation()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp60 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; in ScalarizeVectorResult()
430 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break; in SplitVectorResult()
697 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0)); in SplitVecRes_SCALAR_TO_VECTOR()
1240 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break; in WidenVectorResult()
1907 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(), in WidenVecRes_SCALAR_TO_VECTOR()
2242 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]); in BuildVectorFromScalar()
2296 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp); in GenWidenVectorLoads()
DLegalizeDAG.cpp688 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, in ExpandINSERT_VECTOR_ELT()
2126 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); in ExpandBUILD_VECTOR()
2171 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); in ExpandBUILD_VECTOR()
2174 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); in ExpandBUILD_VECTOR()
3230 case ISD::SCALAR_TO_VECTOR: in ExpandNode()
DLegalizeIntegerTypes.cpp87 case ISD::SCALAR_TO_VECTOR: in PromoteIntegerResult()
769 case ISD::SCALAR_TO_VECTOR: in PromoteIntegerOperand()
2432 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; in ExpandIntegerOperand()
2923 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op); in PromoteIntRes_SCALAR_TO_VECTOR()
DDAGCombiner.cpp5116 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) in ConstantFoldBITCASTofBUILD_VECTOR()
5117 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, in ConstantFoldBITCASTofBUILD_VECTOR()
5216 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, in ConstantFoldBITCASTofBUILD_VECTOR()
6827 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
6872 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitEXTRACT_VECTOR_ELT()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; in ScalarizeVectorResult()
558 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_FP_ROUND()
603 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break; in SplitVectorResult()
1038 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0)); in SplitVecRes_SCALAR_TO_VECTOR()
2066 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break; in WidenVectorResult()
2932 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), in WidenVecRes_SCALAR_TO_VECTOR()
3468 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]); in BuildVectorFromScalar()
3526 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp); in GenWidenVectorLoads()
DSelectionDAGDumper.cpp223 case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector"; in getOperationName()
DLegalizeDAG.cpp367 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, in ExpandINSERT_VECTOR_ELT()
1751 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V); in ExpandBVWithShuffles()
1859 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); in ExpandBUILD_VECTOR()
1914 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); in ExpandBUILD_VECTOR()
1917 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); in ExpandBUILD_VECTOR()
2985 case ISD::SCALAR_TO_VECTOR: in ExpandNode()
4366 case ISD::SCALAR_TO_VECTOR: { in PromoteNode()
DLegalizeIntegerTypes.cpp100 case ISD::SCALAR_TO_VECTOR: in PromoteIntegerResult()
894 case ISD::SCALAR_TO_VECTOR: in PromoteIntegerOperand()
2754 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; in ExpandIntegerOperand()
3307 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op); in PromoteIntRes_SCALAR_TO_VECTOR()
DDAGCombiner.cpp1436 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N); in visit()
2764 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) && in SimplifyBinOpWithSameOpcodeHands()
7658 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) in ConstantFoldBITCASTofBUILD_VECTOR()
7659 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT, in ConstantFoldBITCASTofBUILD_VECTOR()
12340 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { in visitEXTRACT_VECTOR_ELT()
12486 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && in visitEXTRACT_VECTOR_ELT()
13082 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NVT, Scalar); in visitCONCAT_VECTORS()
13525 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR && S.hasOneUse()) { in visitVECTOR_SHUFFLE()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp431 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in SPUTargetLowering()
440 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); in SPUTargetLowering()
885 SDValue vectorizeOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, vecVT, in LowerSTORE()
2184 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, ValOp), in LowerINSERT_VECTOR_ELT()
2830 case ISD::SCALAR_TO_VECTOR: in LowerOperation()
/external/llvm/lib/Target/PowerPC/
DREADME_ALTIVEC.txt61 We currently codegen SCALAR_TO_VECTOR as a store of the scalar to a 16-byte
DPPCISelLowering.cpp487 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); in PPCTargetLowering()
545 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
546 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
560 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in PPCTargetLowering()
563 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in PPCTargetLowering()
567 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal); in PPCTargetLowering()
568 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal); in PPCTargetLowering()
569 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal); in PPCTargetLowering()
570 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal); in PPCTargetLowering()
698 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal); in PPCTargetLowering()
[all …]
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp286 case ISD::SCALAR_TO_VECTOR: in Select()
347 assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts); in Select()
DSIISelLowering.cpp150 case ISD::SCALAR_TO_VECTOR: in SITargetLowering()
174 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
175 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32); in SITargetLowering()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp319 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in SystemZTargetLowering()
381 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in SystemZTargetLowering()
382 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in SystemZTargetLowering()
3962 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value); in buildScalarToVector()
4298 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op)) in lowerBUILD_VECTOR()
4322 if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) || in lowerVECTOR_SHUFFLE()
4467 if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) || in lowerShift()
4571 case ISD::SCALAR_TO_VECTOR: in LowerOperation()
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp1517 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) { in selectScalarSSELoad()
1534 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR && in selectScalarSSELoad()

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