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Searched refs:SETEQ (Results 1 – 25 of 71) sorted by relevance

123

/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUISelLowering.cpp208 ISD::SETEQ); in LowerUDIVREM()
222 ISD::SETEQ); in LowerUDIVREM()
259 Quotient, Quotient_A_One, ISD::SETEQ); in LowerUDIVREM()
263 Quotient_S_One, Div, ISD::SETEQ); in LowerUDIVREM()
275 Remainder, Remainder_S_Den, ISD::SETEQ); in LowerUDIVREM()
279 Remainder_A_Den, Rem, ISD::SETEQ); in LowerUDIVREM()
DAMDGPUInstructions.td40 case ISD::SETEQ: return true;}}}]
DR600ISelLowering.cpp450 case ISD::SETEQ: in LowerSELECT_CC()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td43 defm EQ : ComparisonInt<SETEQ, "eq ">;
60 [(set I32:$dst, (setcc I32:$src, 0, SETEQ))],
63 [(set I32:$dst, (setcc I64:$src, 0, SETEQ))],
/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td15 IntRegs:$fval, SETEQ)),
77 // Convert Rd = selectcc(p0, p1, true_val, false_val, SETEQ) into:
88 IntRegs:$fval, SETEQ)),
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DAnalysis.cpp155 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break; in getFCmpCondCode()
163 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break; in getFCmpCondCode()
186 case ICmpInst::ICMP_EQ: return ISD::SETEQ; in getICmpCondCode()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp525 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
526 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; in InitCmpLibcallCCs()
539 CCs[RTLIB::O_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
540 CCs[RTLIB::O_F64] = ISD::SETEQ; in InitCmpLibcallCCs()
1938 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1940 if ((C1 == 0) == (Cond == ISD::SETEQ)) { in SimplifySetCC()
1947 Cond = ISD::SETEQ; in SimplifySetCC()
1972 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
1981 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { in SimplifySetCC()
2084 case ISD::SETEQ: return DAG.getConstant(0, VT); in SimplifySetCC()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp161 case ISD::SETEQ: in softenSetCCOperands()
1293 (Cond != ISD::SETEQ && Cond != ISD::SETNE)) in simplifySetCCWithAnd()
1382 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1384 if ((C1 == 0) == (Cond == ISD::SETEQ)) { in SimplifySetCC()
1391 Cond = ISD::SETEQ; in SimplifySetCC()
1416 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
1425 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1492 bool Inverse = (N1C->isNullValue() && Cond == ISD::SETEQ) || in SimplifySetCC()
1579 case ISD::SETEQ: return DAG.getConstant(0, dl, VT); in SimplifySetCC()
1598 case ISD::SETEQ: in SimplifySetCC()
[all …]
DLegalizeIntegerTypes.cpp949 case ISD::SETEQ: in PromoteSetCCOperands()
1367 N->getOperand(2), ISD::SETEQ); in ExpandIntegerResult()
1620 ISD::SETEQ); in ExpandShiftWithUnknownAmountBit()
1713 SDValue IsHiEq = DAG.getSetCC(DL, CCT, LHSH, RHSH, ISD::SETEQ); in ExpandIntRes_MINMAX()
2285 ISD::SETEQ : ISD::SETNE); in ExpandIntRes_SADDSUBO()
2557 RHS, DAG.getConstant(0, dl, VT), ISD::SETEQ); in ExpandIntRes_XMULO()
2799 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { in IntegerExpandSetCCOperands()
2927 LHSHi, RHSHi, ISD::SETEQ, false, in IntegerExpandSetCCOperands()
2931 LHSHi, RHSHi, ISD::SETEQ); in IntegerExpandSetCCOperands()
DSelectionDAGDumper.cpp347 case ISD::SETEQ: return "seteq"; in getOperationName()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp453 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
494 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
553 case ISD::SETEQ: return PPC::PRED_EQ; in getPredicateForSetCC()
588 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ in getCRIdxForSetCC()
624 case ISD::SETEQ: { in SelectSETCC()
653 case ISD::SETEQ: in SelectSETCC()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp763 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
764 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; in InitCmpLibcallCCs()
765 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; in InitCmpLibcallCCs()
766 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; in InitCmpLibcallCCs()
791 CCs[RTLIB::O_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
792 CCs[RTLIB::O_F64] = ISD::SETEQ; in InitCmpLibcallCCs()
793 CCs[RTLIB::O_F128] = ISD::SETEQ; in InitCmpLibcallCCs()
794 CCs[RTLIB::O_PPCF128] = ISD::SETEQ; in InitCmpLibcallCCs()
DAnalysis.cpp186 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; in getFCmpCodeWithoutNaN()
201 case ICmpInst::ICMP_EQ: return ISD::SETEQ; in getICmpCondCode()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h732 SETEQ, // 1 X 0 0 1 True if equal enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h870 SETEQ, // 1 X 0 0 1 True if equal enumerator
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp970 case ISD::SETEQ: in CombineFMinMaxLegacy()
1374 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ); in LowerUDIVREM64()
1378 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ); in LowerUDIVREM64()
1448 ISD::SETEQ); in LowerUDIVREM()
1462 ISD::SETEQ); in LowerUDIVREM()
1499 Quotient, Quotient_A_One, ISD::SETEQ); in LowerUDIVREM()
1503 Quotient_S_One, Div, ISD::SETEQ); in LowerUDIVREM()
1515 Remainder, Remainder_S_Den, ISD::SETEQ); in LowerUDIVREM()
1519 Remainder_A_Den, Rem, ISD::SETEQ); in LowerUDIVREM()
1797 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ); in LowerFROUND64()
[all …]
DAMDGPUInstructions.td86 [{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}]
151 [{return N->get() == ISD::SETEQ || N->get() == ISD::SETUEQ;}]
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp1992 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
2036 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
2098 case ISD::SETEQ: return PPC::PRED_EQ; in getPredicateForSetCC()
2129 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ in getCRIdxForSetCC()
2170 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break; in getVCmpInst()
2178 case ISD::SETEQ: in getVCmpInst()
2214 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break; in getVCmpInst()
2222 case ISD::SETEQ: in getVCmpInst()
2277 case ISD::SETEQ: { in trySETCC()
2312 case ISD::SETEQ: in trySETCC()
[all …]
DPPCInstrInfo.td2974 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
3072 defm : ExtSetCCPat<SETEQ,
3161 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
3163 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
3177 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
3206 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3229 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3231 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3245 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
3274 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
[all …]
DPPCInstrQPX.td1023 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETEQ),
1070 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETEQ),
1125 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETEQ)),
1146 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETEQ)),
1167 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETEQ)),
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaISelDAGToDAG.cpp311 case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ: in Select()
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
DPTXISelLowering.cpp161 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeInstrInfo.td754 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ),
791 (i32 GPR:$T), (i32 GPR:$F), SETEQ),
830 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETEQ), bb:$T),
DMBlazeInstrFPU.td140 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETEQ),
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td1394 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1400 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1407 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1413 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;

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