| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 724 SETUGT, // 1 0 1 0 True if unordered or greater than enumerator
752 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 862 SETUGT, // 1 0 1 0 True if unordered or greater than enumerator
890 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | Analysis.cpp | 164 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break; in getFCmpCondCode()
195 case ICmpInst::ICMP_UGT: return ISD::SETUGT; in getICmpCondCode()
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| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 174 case FCmpInst::FCMP_UGT: return ISD::SETUGT; in getFCmpCondCode()
190 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
210 case ICmpInst::ICMP_UGT: return ISD::SETUGT; in getICmpCondCode()
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelDAGToDAG.cpp | 317 case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT: in Select()
337 case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE: in Select()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 238 case ISD::SETUGT: in softenSetCCOperands()
1412 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
1577 case ISD::SETUGT: in SimplifySetCC()
1600 case ISD::SETUGT: in SimplifySetCC()
1752 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; in SimplifySetCC()
1782 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) in SimplifySetCC()
1788 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) in SimplifySetCC()
1800 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) in SimplifySetCC()
1809 if (Cond == ISD::SETUGT && in SimplifySetCC()
1877 Cond == ISD::SETULE || Cond == ISD::SETUGT) { in SimplifySetCC()
[all …]
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| D | LegalizeIntegerTypes.cpp | 971 case ISD::SETUGT: in PromoteSetCCOperands()
1683 return std::make_pair(ISD::SETUGT, ISD::UMAX); in getExpandedMinMaxOps()
2536 ISD::SETULT : ISD::SETUGT); in ExpandIntRes_UADDSUBO()
2836 case ISD::SETUGT: LowCC = ISD::SETUGT; break; in IntegerExpandSetCCOperands()
2876 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { in IntegerExpandSetCCOperands()
2903 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
|
| D | SelectionDAGDumper.cpp | 341 case ISD::SETUGT: return "setugt"; in getOperationName()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 1968 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
2082 case ISD::SETUGT: in SimplifySetCC()
2105 case ISD::SETUGT: in SimplifySetCC()
2244 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); in SimplifySetCC()
2259 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) in SimplifySetCC()
2265 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) in SimplifySetCC()
2277 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) in SimplifySetCC()
2286 if (Cond == ISD::SETUGT && in SimplifySetCC()
2371 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) in SimplifySetCC()
2372 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); in SimplifySetCC()
[all …]
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| D | LegalizeIntegerTypes.cpp | 818 case ISD::SETUGT: in PromoteSetCCOperands()
2235 ISD::SETULT : ISD::SETUGT); in ExpandIntRes_UADDSUBO()
2513 case ISD::SETUGT: LowCC = ISD::SETUGT; break; in IntegerExpandSetCCOperands()
2548 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { in IntegerExpandSetCCOperands()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | README.txt | 76 SETUGT unimplemented
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstructions.td | 52 case ISD::SETOGT: case ISD::SETUGT:
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInteger.td | 52 defm GT_U : ComparisonInt<SETUGT, "gt_u">;
|
| D | WebAssemblyISelLowering.cpp | 78 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSelectCCInfo.td | 30 IntRegs:$fval, SETUGT)),
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXInstrInfo.td | 551 defm SETPGTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGT, "gt">;
564 defm SETPGTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGT, "gt">;
577 defm SETPGTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGT, "gt">;
590 defm SETPGTf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUGT, SETOGT, "gt">;
599 defm SETPGTf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUGT, SETOGT, "gt">;
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrQPX.td | 1007 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETUGT),
1054 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETUGT),
1133 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETUGT)),
1154 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETUGT)),
1175 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETUGT)),
|
| D | PPCISelDAGToDAG.cpp | 2113 case ISD::SETUGT: return PPC::PRED_GT; in getPredicateForSetCC()
2145 case ISD::SETUGT: return 1; in getCRIdxForSetCC()
2165 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
2209 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break; in getVCmpInst()
2217 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break; in getVCmpInst()
2243 case ISD::SETUGT: in getVCmpInst()
|
| D | PPCInstrInfo.td | 3006 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
3013 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3157 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
3202 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3225 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3270 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3382 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),
3406 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),
3427 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
3448 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.td | 772 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT),
809 (i32 GPR:$T), (i32 GPR:$F), SETUGT),
842 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETUGT), bb:$T),
|
| D | MBlazeInstrFPU.td | 188 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETUGT),
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 568 case ISD::SETUGT: return PPC::PRED_GT; in getPredicateForSetCC()
604 case ISD::SETUGT: return 1; in getCRIdxForSetCC()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 542 case ISD::SETUGT: in EmitInstrWithCustomInserter()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 194 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in MipsSETargetLowering()
199 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); in MipsSETargetLowering()
290 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAIntType()
326 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAFloatType()
965 case ISD::SETUGT: in isLegalDSPCondCode()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 656 case ISD::SETUGT: return SPCC::ICC_GU; in IntCondCCodeToICC()
680 case ISD::SETUGT: return SPCC::FCC_UG; in FPCondCCodeToFCC()
|