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Searched refs:ShiftImm (Results 1 – 7 of 7) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp334 unsigned ShiftImm; // shift for OffsetReg. member
344 unsigned ShiftImm; member
355 unsigned ShiftImm; member
360 unsigned ShiftImm; member
746 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || in isMemTBH()
763 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) in isT2MemRegOffset()
974 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands()
982 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm))); in addRegShiftedImmOperands()
1176 Memory.ShiftImm, Memory.ShiftType); in addAddrMode2Operands()
1326 Memory.ShiftImm, Memory.ShiftType); in addMemRegOffsetOperands()
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/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp170 uint64_t ShiftImm, bool SetFlags = false,
175 uint64_t ShiftImm, bool SetFlags = false,
201 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
209 uint64_t ShiftImm);
1277 unsigned ShiftImm; in emitAddSub_ri() local
1279 ShiftImm = 0; in emitAddSub_ri()
1281 ShiftImm = 12; in emitAddSub_ri()
1310 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitAddSub_ri()
1318 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rs() argument
1326 if (ShiftImm >= RetVT.getSizeInBits()) in emitAddSub_rs()
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DAArch64ISelDAGToDAG.cpp1526 uint64_t ShiftImm; in isBitfieldExtractOpFromSExtInReg() local
1527 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) && in isBitfieldExtractOpFromSExtInReg()
1528 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in isBitfieldExtractOpFromSExtInReg()
1532 if (ShiftImm + Width > BitWidth) in isBitfieldExtractOpFromSExtInReg()
1537 Immr = ShiftImm; in isBitfieldExtractOpFromSExtInReg()
1538 Imms = ShiftImm + Width - 1; in isBitfieldExtractOpFromSExtInReg()
1662 uint64_t ShiftImm; in tryBitfieldExtractOpFromSExt() local
1664 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in tryBitfieldExtractOpFromSExt()
1670 unsigned Immr = ShiftImm; in tryBitfieldExtractOpFromSExt()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp516 unsigned ShiftImm; // shift for OffsetReg. member
526 unsigned ShiftImm; member
538 unsigned ShiftImm; member
544 unsigned ShiftImm; member
1254 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || in isMemTBH()
1271 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) in isT2MemRegOffset()
1808 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands()
1817 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); in addRegShiftedImmOperands()
2131 Memory.ShiftImm, Memory.ShiftType); in addAddrMode2Operands()
2340 Memory.ShiftImm, Memory.ShiftType); in addMemRegOffsetOperands()
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsISelLowering.cpp1083 int64_t ShiftImm = (Size == 1) ? 24 : 16; in EmitAtomicBinaryPartword() local
1090 .addReg(SrlRes).addImm(ShiftImm); in EmitAtomicBinaryPartword()
1092 .addReg(SllRes).addImm(ShiftImm); in EmitAtomicBinaryPartword()
1294 int64_t ShiftImm = (Size == 1) ? 24 : 16; in EmitAtomicCmpSwapPartword() local
1299 .addReg(SrlRes).addImm(ShiftImm); in EmitAtomicCmpSwapPartword()
1301 .addReg(SllRes).addImm(ShiftImm); in EmitAtomicCmpSwapPartword()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp2759 unsigned ShiftImm; in SelectShift() local
2762 ShiftImm = CI->getZExtValue(); in SelectShift()
2766 if (ShiftImm == 0 || ShiftImm >=32) in SelectShift()
2790 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp1218 int64_t ShiftImm = 32 - (Size * 8); in emitSignExtendToI32InReg() local
1220 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
1221 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); in emitSignExtendToI32InReg()