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Searched refs:SubIdx (Results 1 – 25 of 81) sorted by relevance

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/external/llvm/lib/CodeGen/
DDetectDeadLanes.cpp245 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
246 return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
249 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
251 TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
260 MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx); in transferUsedLanes()
269 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
270 return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
319 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
320 DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes); in transferDefinedLanes()
321 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
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DTargetRegisterInfo.cpp46 unsigned SubIdx) { in PrintReg() argument
47 return Printable([Reg, TRI, SubIdx](raw_ostream &OS) { in PrintReg()
58 if (SubIdx) { in PrintReg()
60 OS << ':' << TRI->getSubRegIndexName(SubIdx); in PrintReg()
62 OS << ":sub(" << SubIdx << ')'; in PrintReg()
DExpandPostRAPseudos.cpp90 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
92 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
93 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
DPeepholeOptimizer.cpp414 unsigned SrcReg, DstReg, SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
415 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
429 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
439 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
465 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
542 .addReg(DstReg, 0, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
545 Copy->getOperand(0).setSubReg(SubIdx); in INITIALIZE_PASS_DEPENDENCY()
1749 if (RegSeqInput.SubIdx == DefSubReg) { in getNextSourceFromRegSequence()
1791 if (InsertedReg.SubIdx == DefSubReg) { in getNextSourceFromInsertSubreg()
1810 TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)) != 0) in getNextSourceFromInsertSubreg()
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DRegisterCoalescer.cpp204 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
1244 unsigned SubIdx) { in updateRegDefsUses() argument
1281 if (DstInt && !Reads && SubIdx) in updateRegDefsUses()
1291 if (SubIdx && MO.isDef()) in updateRegDefsUses()
1296 if (SubIdx != 0 && MO.isUse() && MRI->shouldTrackSubRegLiveness(DstReg)) { in updateRegDefsUses()
1306 addUndefFlag(*DstInt, UseIdx, MO, SubIdx); in updateRegDefsUses()
1312 MO.substVirtReg(DstReg, SubIdx, *TRI); in updateRegDefsUses()
1708 const unsigned SubIdx; member in __anona927d7ac0211::JoinVals
1863 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask, in JoinVals() argument
1867 : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask), in JoinVals()
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DTargetInstrInfo.cpp345 unsigned SubIdx, unsigned &Size, in getStackSlotRange() argument
348 if (!SubIdx) { in getStackSlotRange()
354 unsigned BitSize = TRI->getSubRegIdxSize(SubIdx); in getStackSlotRange()
360 int BitOffset = TRI->getSubRegIdxOffset(SubIdx); in getStackSlotRange()
377 unsigned DestReg, unsigned SubIdx, in reMaterialize() argument
381 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
1167 InputReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getExtractSubregInputs()
1193 InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getInsertSubregInputs()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegisterCoalescer.h42 unsigned SubIdx; variable
60 : TII(tii), TRI(tri), DstReg(0), SrcReg(0), SubIdx(0), in CoalescerPair()
99 unsigned getSubIdx() const { return SubIdx; } in getSubIdx()
DExpandPostRAPseudos.cpp110 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
112 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
113 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
DVirtRegRewriter.cpp706 unsigned SubIdx, const TargetRegisterInfo *TRI) { in findSuperReg() argument
710 if (TRI->getSubReg(Reg, SubIdx) == SubReg) in findSuperReg()
914 unsigned SubIdx = 0; in GetRegForReload() local
919 SubIdx = TRI->getSubRegIndex(PRRU, RealPhysRegUsed); in GetRegForReload()
920 assert(SubIdx && in GetRegForReload()
956 unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) :NewPhysReg; in GetRegForReload()
1975 unsigned SubIdx = MI.getOperand(i).getSubReg(); in ProcessUses() local
2022 if (PhysReg && !AvoidReload && SubIdx) { in ProcessUses()
2070 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; in ProcessUses()
2156 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; in ProcessUses()
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DLiveDebugVariables.cpp251 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx,
338 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx);
701 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx, in renameRegister() argument
711 Loc.substVirtReg(NewReg, SubIdx, *TRI); in renameRegister()
717 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { in renameRegister() argument
727 UV->renameRegister(OldReg, NewReg, SubIdx, TRI); in renameRegister()
733 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { in renameRegister() argument
735 static_cast<LDVImpl*>(pImpl)->renameRegister(OldReg, NewReg, SubIdx); in renameRegister()
DTwoAddressInstructionPass.cpp1257 unsigned SubIdx = mi->getOperand(3).getImm(); in runOnMachineFunction() local
1260 mi->getOperand(0).setSubReg(SubIdx); in runOnMachineFunction()
1290 unsigned DstReg, unsigned SubIdx, in UpdateRegSequenceSrcs() argument
1297 MO.substVirtReg(DstReg, SubIdx, TRI); in UpdateRegSequenceSrcs()
1455 unsigned SubIdx = MI->getOperand(i+1).getImm(); in EliminateRegSequences() local
1477 MRI->getRegClass(SrcReg), SubIdx)) { in EliminateRegSequences()
1506 .addReg(DstReg, RegState::Define, SubIdx) in EliminateRegSequences()
1518 unsigned SubIdx = MI->getOperand(i+1).getImm(); in EliminateRegSequences() local
1519 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI); in EliminateRegSequences()
DMachineVerifier.cpp735 unsigned SubIdx = MO->getSubReg(); in visitMachineOperand() local
738 if (SubIdx) { in visitMachineOperand()
752 if (SubIdx) { in visitMachineOperand()
754 TRI->getSubClassWithSubReg(RC, SubIdx); in visitMachineOperand()
758 << " does not support subreg index " << SubIdx << "\n"; in visitMachineOperand()
764 << " does not fully support subreg index " << SubIdx << "\n"; in visitMachineOperand()
769 if (SubIdx) { in visitMachineOperand()
776 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetRegisterInfo.h324 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
325 assert(SubIdx && "This is not a subregister index"); in getSubRegIndexName()
326 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
382 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
385 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) in getMatchingSuperReg()
703 unsigned SubIdx; variable
706 : TRI(tri), Reg(reg), SubIdx(subidx) {} in TRI()
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h370 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
371 assert(SubIdx && SubIdx < getNumSubRegIndices() && in getSubRegIndexName()
373 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
380 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask() argument
381 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); in getSubRegIndexLaneMask()
382 return SubRegIndexLaneMasks[SubIdx]; in getSubRegIndexLaneMask()
499 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
501 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
DTargetInstrInfo.h171 unsigned &SubIdx) const { in isCoalescableExtInstr() argument
250 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
281 unsigned SubIdx, const MachineInstr &Orig,
367 unsigned SubIdx; member
369 unsigned SubIdx = 0)
370 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
/external/swiftshader/third_party/LLVM/utils/TableGen/
DCodeGenRegisters.h153 CodeGenRegisterClass *getSubClassWithSubReg(Record *SubIdx) const { in getSubClassWithSubReg() argument
154 return SubClassWithSubReg.lookup(SubIdx); in getSubClassWithSubReg()
157 void setSubClassWithSubReg(Record *SubIdx, CodeGenRegisterClass *SubRC) { in setSubClassWithSubReg() argument
158 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
/external/swiftshader/third_party/LLVM/lib/Target/
DTargetRegisterInfo.cpp43 if (SubIdx) { in print()
45 OS << ':' << TRI->getSubRegIndexName(SubIdx); in print()
47 OS << ":sub(" << SubIdx << ')'; in print()
/external/llvm/utils/TableGen/
DCodeGenRegisters.h349 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() argument
350 return SubClassWithSubReg.lookup(SubIdx); in getSubClassWithSubReg()
353 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg() argument
355 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
360 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
364 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass() argument
366 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
DCodeGenRegisters.cpp469 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs() local
470 if (!SubIdx) in computeSecondarySubRegs()
473 NewIdx->addComposite(SI->first, SubIdx); in computeSecondarySubRegs()
898 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, in getSuperRegClasses() argument
900 auto FindI = SuperRegClasses.find(SubIdx); in getSuperRegClasses()
1565 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); in pruneUnitSets() local
1566 SubIdx != EndIdx; ++SubIdx) { in pruneUnitSets()
1567 const RegUnitSet &SubSet = RegUnitSets[SubIdx]; in pruneUnitSets()
1570 if (SuperIdx == SubIdx) in pruneUnitSets()
1579 DEBUG(dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdx in pruneUnitSets()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DThumb2RegisterInfo.cpp38 unsigned DestReg, unsigned SubIdx, in emitLoadConstPool() argument
49 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp400 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg() argument
403 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
416 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
451 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
459 SubIdx == DefSubIdx) { in EmitSubregNode()
472 VReg = ConstrainForSubReg(VReg, SubIdx, in EmitSubregNode()
482 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); in EmitSubregNode()
489 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
506 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
527 MI->addOperand(MachineOperand::CreateImm(SubIdx)); in EmitSubregNode()
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/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp444 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg() argument
447 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
460 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
493 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
502 SubIdx == DefSubIdx && in EmitSubregNode()
517 VReg = ConstrainForSubReg(VReg, SubIdx, in EmitSubregNode()
527 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); in EmitSubregNode()
534 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
551 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
572 MIB.addImm(SubIdx); in EmitSubregNode()
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/external/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp65 unsigned SubIdx, int Val, in emitThumb1LoadConstPool() argument
77 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
85 unsigned SubIdx, int Val, in emitThumb2LoadConstPool() argument
96 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
/external/llvm/lib/MC/
DMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp251 unsigned &SubIdx) const { in isCoalescableExtInstr()
258 SubIdx = PPC::sub_32; in isCoalescableExtInstr()
752 unsigned SubIdx = 0; in insertSelect() local
758 SubIdx = PPC::sub_eq; SwapOps = false; break; in insertSelect()
762 SubIdx = PPC::sub_eq; SwapOps = true; break; in insertSelect()
766 SubIdx = PPC::sub_lt; SwapOps = false; break; in insertSelect()
770 SubIdx = PPC::sub_lt; SwapOps = true; break; in insertSelect()
774 SubIdx = PPC::sub_gt; SwapOps = false; break; in insertSelect()
778 SubIdx = PPC::sub_gt; SwapOps = true; break; in insertSelect()
782 SubIdx = PPC::sub_un; SwapOps = false; break; in insertSelect()
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