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Searched refs:Tmp3 (Results 1 – 20 of 20) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp642 SDValue Tmp3 = Idx; in PerformInsertVectorEltInMemory() local
652 EVT IdxVT = Tmp3.getValueType(); in PerformInsertVectorEltInMemory()
665 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); in PerformInsertVectorEltInMemory()
668 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); in PerformInsertVectorEltInMemory()
669 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); in PerformInsertVectorEltInMemory()
716 SDValue Tmp3; in OptimizeFloatStore() local
724 Tmp3 = DAG.getConstant(CFP->getValueAPF(). in OptimizeFloatStore()
727 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), in OptimizeFloatStore()
734 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). in OptimizeFloatStore()
736 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), in OptimizeFloatStore()
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DLegalizeFloatTypes.cpp1308 SDValue Tmp1, Tmp2, Tmp3; in FloatExpandSetCCOperands() local
1313 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
1319 NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3); in FloatExpandSetCCOperands()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DIntrinsicLowering.cpp186 Value *Tmp3 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
192 Tmp3 = Builder.CreateAnd(Tmp3, in LowerBSWAP()
198 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or1"); in LowerBSWAP()
214 Value* Tmp3 = Builder.CreateLShr(V, in LowerBSWAP() local
239 Tmp3 = Builder.CreateAnd(Tmp3, in LowerBSWAP()
249 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or3"); in LowerBSWAP()
/external/llvm/lib/CodeGen/
DIntrinsicLowering.cpp186 Value *Tmp3 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
192 Tmp3 = Builder.CreateAnd(Tmp3, in LowerBSWAP()
198 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or1"); in LowerBSWAP()
214 Value* Tmp3 = Builder.CreateLShr(V, in LowerBSWAP() local
239 Tmp3 = Builder.CreateAnd(Tmp3, in LowerBSWAP()
249 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or3"); in LowerBSWAP()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp319 SDValue Tmp3 = Idx; in PerformInsertVectorEltInMemory() local
329 EVT IdxVT = Tmp3.getValueType(); in PerformInsertVectorEltInMemory()
342 Tmp3 = DAG.getZExtOrTrunc(Tmp3, dl, PtrVT); in PerformInsertVectorEltInMemory()
345 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3, in PerformInsertVectorEltInMemory()
347 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); in PerformInsertVectorEltInMemory()
1523 SDValue Tmp3 = Node->getOperand(2); in ExpandDYNAMIC_STACKALLOC() local
1533 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); in ExpandDYNAMIC_STACKALLOC()
2583 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; in ExpandBSWAP() local
2592 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); in ExpandBSWAP()
2595 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, in ExpandBSWAP()
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DLegalizeFloatTypes.cpp1549 SDValue Tmp1, Tmp2, Tmp3; in FloatExpandSetCCOperands() local
1554 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
1560 NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3); in FloatExpandSetCCOperands()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelDAGToDAG.cpp1331 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in SelectAtomic64() local
1332 if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) in SelectAtomic64()
1336 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain}; in SelectAtomic64()
1359 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in SelectAtomicLoadAdd() local
1360 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) in SelectAtomicLoadAdd()
1482 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain }; in SelectAtomicLoadAdd()
1488 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain }; in SelectAtomicLoadAdd()
1571 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in SelectAtomicLoadArith() local
1572 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) in SelectAtomicLoadArith()
1643 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain }; in SelectAtomicLoadArith()
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DX86ISelLowering.cpp7558 SDValue Tmp2, Tmp3; in LowerShiftParts() local
7561 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); in LowerShiftParts()
7564 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); in LowerShiftParts()
7574 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; in LowerShiftParts()
7575 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; in LowerShiftParts()
/external/llvm/lib/Transforms/Utils/
DIntegerDivision.cpp135 Value *Tmp3 = Builder.CreateXor(Tmp1, Divisor); in generateSignedDivisionCode() local
136 Value *U_Dvsr = Builder.CreateSub(Tmp3, Tmp1); in generateSignedDivisionCode()
283 Value *Tmp3 = Builder.CreateLShr(Dividend, SR_1); in generateUnsignedDivisionCode() local
351 R_1->addIncoming(Tmp3, Preheader); in generateUnsignedDivisionCode()
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp2211 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
2212 bool foldedLoad = tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2215 foldedLoad = tryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2227 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), in Select()
2364 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
2365 bool foldedLoad = tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2372 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain; in Select() local
2373 if (tryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in Select()
2374 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) }; in Select()
2428 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), in Select()
/external/webrtc/webrtc/modules/audio_coding/codecs/isac/main/source/
Dstructs.h255 double Tmp3[MAXFFTSIZE]; member
Dfft.c343 Sin = (REAL *) fftstate->Tmp3; in FFTRADIX()
/external/clang/lib/CodeGen/
DCGExprComplex.cpp782 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd in EmitBinDiv() local
793 DSTr = Builder.CreateUDiv(Tmp3, Tmp6); in EmitBinDiv()
796 DSTr = Builder.CreateSDiv(Tmp3, Tmp6); in EmitBinDiv()
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreISelLowering.cpp757 SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList, in LowerVAARG() local
761 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1), in LowerVAARG()
764 return DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(), in LowerVAARG()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp2017 SDValue Tmp3 = ST->getValue(); in LowerSTOREi1() local
2018 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only"); in LowerSTOREi1()
2022 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3); in LowerSTOREi1()
2023 SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, in LowerSTOREi1()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelLowering.cpp3812 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); in LowerSHL_PARTS() local
3813 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); in LowerSHL_PARTS()
3841 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRL_PARTS() local
3842 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRL_PARTS()
3869 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRA_PARTS() local
3870 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRA_PARTS()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp6942 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); in LowerSHL_PARTS() local
6943 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); in LowerSHL_PARTS()
6971 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRL_PARTS() local
6972 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRL_PARTS()
6999 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRA_PARTS() local
7000 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRA_PARTS()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp1972 SDValue Tmp3 = in lowerVAARG() local
1977 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, in lowerVAARG()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.cpp3313 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); in LowerShiftLeftParts() local
3320 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc, in LowerShiftLeftParts()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp4571 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); in LowerShiftLeftParts() local
4578 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc, in LowerShiftLeftParts()