| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenAsmMatcher.inc | 1596 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
1598 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
1602 ((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
1605 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
1614 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
1619 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
1628 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
1640 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
1649 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
1658 ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 963 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon92cf716e0311::ARMOperand
2806 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); in cvtT2LdrdPre()
2807 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); in cvtT2LdrdPre()
2826 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); in cvtT2StrdPre()
2827 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); in cvtT2StrdPre()
2841 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); in cvtLdWriteBackRegT2AddrModeImm8()
2859 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); in cvtStWriteBackRegT2AddrModeImm8()
2871 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); in cvtLdWriteBackRegAddrMode2()
2887 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); in cvtLdWriteBackRegAddrModeImm12()
2906 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); in cvtStWriteBackRegAddrModeImm12()
[all …]
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 391 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon2fa8e53e0111::AMDGPUOperand
397 addRegOperands(Inst, N); in addRegOrImmOperands()
408 addRegOperands(Inst, N); in addRegOrImmWithInputModsOperands()
1668 Op.addRegOperands(Inst, 1); in cvtDSOffset01()
1693 Op.addRegOperands(Inst, 1); in cvtDS()
2137 Op.addRegOperands(Inst, 1); in cvtMubufImpl()
2180 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtMIMG()
2213 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtMIMGAtomic()
2217 ((AMDGPUOperand &)*Operands[I]).addRegOperands(Inst, 1); in cvtMIMGAtomic()
2395 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtId()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/AsmParser/ |
| D | MBlazeAsmParser.cpp | 187 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.td | 43 let RenderMethod = "addRegOperands";
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86Operand.h | 385 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 164 let RenderMethod = "addRegOperands";
620 let RenderMethod = "addRegOperands", ParserMethod="tryParseGPRSeqPair" in {
|
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 268 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon920606c00111::SystemZOperand
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 295 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /external/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 385 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 302 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anoncba7d3b40111::SparcOperand
|
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 352 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 551 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 1796 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anonef5d38c20311::ARMOperand
4759 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); in cvtThumbMultiply()
4768 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); in cvtThumbMultiply()
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1159 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon26fd99540211::AArch64Operand
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 810 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anond0efcad40311::MipsOperand
|