/external/llvm/test/MC/X86/ |
D | x86-64.s | 327 fdivrp label 580 fdivrp %st(0), %st(1) // CHECK: encoding: [0xde,0xf9] label 581 fdivrp %st(1), %st(0) // CHECK: encoding: [0xde,0xf9] label 1386 fdivrp %st(0), %st(1) label 1399 fdivrp %st(1), %st(0) label 1412 fdivrp %st(1) label 1425 fdivrp label
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D | intel-syntax.s | 512 fdivrp ST(1), ST(0) label 525 fdivrp ST(0), ST(1) label 538 fdivrp ST(1) label 565 fdivrp label
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D | x86-32-coverage.s | 2605 fdivrp %st(2)
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/external/valgrind/none/tests/x86/ |
D | insn_fpu.def | 169 fdivrp st0.ps[1234.5678] st2.ps[8765.4321] => st1.ps[7.10000058320005] 170 fdivrp st0.ps[-1234.5678] st2.ps[8765.4321] => st1.ps[-7.10000058320005] 171 fdivrp st0.ps[1234.5678] st2.ps[-8765.4321] => st1.ps[-7.10000058320005] 172 fdivrp st0.ps[-1234.5678] st2.ps[-8765.4321] => st1.ps[7.10000058320005] 173 fdivrp st0.pd[1234567.7654321] st2.pd[7654321.1234567] => st1.pd[6.20000079200001] 174 fdivrp st0.pd[-1234567.7654321] st2.pd[7654321.1234567] => st1.pd[-6.20000079200001] 175 fdivrp st0.pd[1234567.7654321] st2.pd[-7654321.1234567] => st1.pd[-6.20000079200001] 176 fdivrp st0.pd[-1234567.7654321] st2.pd[-7654321.1234567] => st1.pd[6.20000079200001] 177 fdivrp st0.ps[1234.5678] st1.ps[8765.4321] : => st0.ps[7.10000058320005] 178 fdivrp st0.ps[-1234.5678] st1.ps[8765.4321] : => st0.ps[-7.10000058320005] [all …]
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/external/valgrind/none/tests/amd64/ |
D | insn_fpu.def | 169 fdivrp st0.ps[1234.5678] st2.ps[8765.4321] => st1.ps[7.10000058320005] 170 fdivrp st0.ps[-1234.5678] st2.ps[8765.4321] => st1.ps[-7.10000058320005] 171 fdivrp st0.ps[1234.5678] st2.ps[-8765.4321] => st1.ps[-7.10000058320005] 172 fdivrp st0.ps[-1234.5678] st2.ps[-8765.4321] => st1.ps[7.10000058320005] 173 fdivrp st0.pd[1234567.7654321] st2.pd[7654321.1234567] => st1.pd[6.20000079200001] 174 fdivrp st0.pd[-1234567.7654321] st2.pd[7654321.1234567] => st1.pd[-6.20000079200001] 175 fdivrp st0.pd[1234567.7654321] st2.pd[-7654321.1234567] => st1.pd[-6.20000079200001] 176 fdivrp st0.pd[-1234567.7654321] st2.pd[-7654321.1234567] => st1.pd[6.20000079200001] 177 fdivrp st0.ps[1234.5678] st1.ps[8765.4321] : => st0.ps[7.10000058320005] 178 fdivrp st0.ps[-1234.5678] st1.ps[8765.4321] : => st0.ps[-7.10000058320005] [all …]
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/external/llvm/test/MC/Disassembler/X86/ |
D | fp-stack.txt | 964 # CHECK: fdivrp %st(0) 967 # CHECK: fdivrp %st(1) 970 # CHECK: fdivrp %st(2) 973 # CHECK: fdivrp %st(3) 976 # CHECK: fdivrp %st(4) 979 # CHECK: fdivrp %st(5) 982 # CHECK: fdivrp %st(6) 985 # CHECK: fdivrp %st(7)
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/external/swiftshader/third_party/LLVM/test/MC/X86/ |
D | x86-64.s | 303 fdivrp label 542 fdivrp %st(0), %st(1) // CHECK: encoding: [0xde,0xf9] label 543 fdivrp %st(1), %st(0) // CHECK: encoding: [0xde,0xf9] label
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D | x86-32-coverage.s | 4230 fdivrp %st(2) 13971 fdivrp %st(2)
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/external/elfutils/libcpu/defs/ |
D | i386 | 307 11011110,11111{freg}:fdivrp %st,{freg} 318 11011110,11110{freg}:fdivrp %st,{freg} 320 `11011110,11110001:fdivrp
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/external/mesa3d/src/mesa/x86/ |
D | assyntax.h | 718 #define FDIVRP(a, b) CHOICE(fdivrp ARG2(a,b), fdivrp ARG2(a,b), fdivrp ARG2(b,a)) 1439 #define FDIVRP(a, b) fdivrp b, a
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86InstrInfo.td | 1606 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>; 1637 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>; 1652 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>;
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D | X86GenAsmMatcher.inc | 3441 { X86::DIV_FPrST0, "fdivrp", Convert__regST1, { }, 0}, 3442 { X86::DIV_FPrST0, "fdivrp", Convert__Reg1_0, { MCK_RST }, 0}, 3443 { X86::DIV_FPrST0, "fdivrp", Convert__regST0, { MCK_ST0, MCK_ST0 }, 0}, 3444 { X86::DIV_FPrST0, "fdivrp", Convert__Reg1_1, { MCK_ST0, MCK_RST }, 0}, 3445 { X86::DIV_FPrST0, "fdivrp", Convert__Reg1_0, { MCK_RST, MCK_ST0 }, 0},
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D | X86GenAsmWriter.inc | 3876 "fdivs\t\000fdivl\t\000fidivs\t\000fidivl\t\000fdivrp\t\000fdiv\t\000fdi" 7192 AsmString = "fdivrp";
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D | X86GenAsmWriter1.inc | 3864 "fdivr\t\000fidivr\t\000fdivrp\t\000divsd\t\000divss\t\000fdiv\t\000fidi" 7935 AsmString = "fdivrp";
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/external/elfutils/tests/ |
D | testfile44.expect.bz2 | 1testfile44.o: elf32-elf_i386
2
3Disassembly of section .text:
4
5 0 ... |
D | testfile45.expect.bz2 | 1testfile45.o: elf64-elf_x86_64
2
3Disassembly of section .text:
4
5 0 ... |