/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMExpandPseudoInsts.cpp | 425 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) in ExpandVLD() 426 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD() 428 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD() 430 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD() 461 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD() 552 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp() 554 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp() 556 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp() 558 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp() 600 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp() [all …]
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D | MLxExpansionPass.cpp | 233 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead)); in ExpandFPMLxInstruction()
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D | ARMBaseInstrInfo.h | 306 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
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D | ARMLoadStoreOptimizer.cpp | 1056 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill)) in InsertLDR_STR() 1110 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp() 1111 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)); in FixInvalidRegPairOp()
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/external/llvm/lib/Target/ARM/ |
D | ARMExpandPseudoInsts.cpp | 409 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD() 411 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD() 413 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD() 415 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD() 446 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD() 542 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp() 544 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp() 546 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp() 548 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp() 590 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp() [all …]
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D | MLxExpansionPass.cpp | 301 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead)); in ExpandFPMLxInstruction()
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D | ARMBaseInstrInfo.h | 411 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
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D | ARMLoadStoreOptimizer.cpp | 1560 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill)) in InsertLDR_STR() 1623 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp() 1624 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)); in FixInvalidRegPairOp()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ExpandPseudoInsts.cpp | 131 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in tryOrrMovk() 209 RegState::Define | getDeadRegState(DstIsDead && CountThree)) in tryToreplicateChunks() 233 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in tryToreplicateChunks() 383 RegState::Define | getDeadRegState(DstIsDead && SingleMovk)) in trySequenceOfOnes() 399 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in trySequenceOfOnes() 556 getDeadRegState(DstIsDead && Shift == LastShift)) in expandMOVImm() 581 getDeadRegState(DstIsDead && Shift == LastShift)) in expandMOVImm()
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/external/llvm/include/llvm/CodeGen/ |
D | MachineInstrBuilder.h | 381 inline unsigned getDeadRegState(bool B) { in getDeadRegState() function 400 getDeadRegState(RegOp.isDead()) | in getRegState()
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86InstrInfo.cpp | 1411 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) in convertToThreeAddressWithLEA() 1468 .addReg(A, RegState::Define | getDeadRegState(isDead)) in convertToThreeAddress() 1485 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) in convertToThreeAddress() 1505 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) in convertToThreeAddress() 1520 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) in convertToThreeAddress() 1551 getDeadRegState(isDead)), in convertToThreeAddress() 1562 getDeadRegState(isDead)), in convertToThreeAddress() 1580 getDeadRegState(isDead)), in convertToThreeAddress() 1591 getDeadRegState(isDead)), in convertToThreeAddress() 1620 getDeadRegState(isDead)), in convertToThreeAddress() [all …]
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
D | MachineInstrBuilder.h | 255 inline unsigned getDeadRegState(bool B) { in getDeadRegState() function
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/external/llvm/lib/CodeGen/ |
D | MachineInstrBundle.cpp | 204 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | in finalizeBundle()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
D | TargetInstrInfoImpl.cpp | 100 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) in commuteInstruction()
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCInstrInfo.cpp | 142 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) in commuteInstruction()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCInstrInfo.cpp | 381 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) in commuteInstructionImpl()
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/external/llvm/lib/Target/X86/ |
D | X86InstrInfo.cpp | 2725 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) in convertToThreeAddressWithLEA() 6438 getDeadRegState(ImpOp.isDead()) | in unfoldMemoryOperand()
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