| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | Thumb2RegisterInfo.cpp | 49 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
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| D | ARMLoadStoreOptimizer.cpp | 359 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) in MergeOps()
748 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLSMultiple()
903 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLoadStore()
906 .addReg(MO.getReg(), (isLd ? getDefRegState(true) : in MergeBaseUpdateLoadStore()
1056 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill)) in InsertLDR_STR()
1110 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp()
1111 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)); in FixInvalidRegPairOp()
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| D | MLxExpansionPass.cpp | 233 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead)); in ExpandFPMLxInstruction()
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| D | ARMBaseInstrInfo.h | 306 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
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| D | Thumb1FrameLowering.cpp | 355 MIB.addReg(Reg, getDefRegState(true)); in restoreCalleeSavedRegisters()
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| D | Thumb1RegisterInfo.cpp | 78 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
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| D | ARMFrameLowering.cpp | 661 MIB.addReg(Regs[i], getDefRegState(true)); in emitPopInst()
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| D | ARMBaseRegisterInfo.cpp | 812 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 81 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
85 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb1InstrInfo.cpp | 66 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
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| D | ARMLoadStoreOptimizer.cpp | 768 MIB.addReg(Base, getDefRegState(true)) in CreateLoadStoreMulti()
785 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second)); in CreateLoadStoreMulti()
1263 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLSMultiple()
1387 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLoadStore()
1390 .addReg(MO.getReg(), (isLd ? getDefRegState(true) : in MergeBaseUpdateLoadStore()
1560 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill)) in InsertLDR_STR()
1623 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp()
1624 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)); in FixInvalidRegPairOp()
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| D | ThumbRegisterInfo.cpp | 77 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
96 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
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| D | MLxExpansionPass.cpp | 301 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead)); in ExpandFPMLxInstruction()
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| D | ARMBaseInstrInfo.h | 411 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
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| D | Thumb1FrameLowering.cpp | 646 MIB.addReg(Reg, getDefRegState(true)); in restoreCalleeSavedRegisters()
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| D | ARMBaseRegisterInfo.cpp | 423 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
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| D | ARMFrameLowering.cpp | 1020 MIB.addReg(Regs[i], getDefRegState(true)); in emitPopInst()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 372 inline unsigned getDefRegState(bool B) { in getDefRegState() function
397 return getDefRegState(RegOp.isDef()) | in getRegState()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 246 inline unsigned getDefRegState(bool B) { in getDefRegState() function
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiMemAluCombiner.cpp | 260 InstrBuilder.addReg(Dest.getReg(), getDefRegState(true)); in insertMergedInstruction()
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| /external/llvm/lib/CodeGen/ |
| D | MachineInstrBundle.cpp | 204 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | in finalizeBundle()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 469 unsigned SrcDstRegState = getDefRegState(!IsStore); in buildScratchLoadStore()
477 .addReg(SubReg, getDefRegState(!IsStore)) in buildScratchLoadStore()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 1063 MIB.addReg(Reg2, getDefRegState(true)); in restoreCalleeSavedRegisters()
1068 MIB.addReg(Reg1, getDefRegState(true)) in restoreCalleeSavedRegisters()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 368 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 166 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)); in emitSPUpdate()
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