| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 84 MIRBuilder.getMBB().addLiveIn(VA.getLocReg()); in lowerFormalArguments()
85 MIRBuilder.buildInstr(TargetOpcode::COPY, VRegs[i], VA.getLocReg()); in lowerFormalArguments()
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 186 TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ? in LowerFormalArguments()
188 assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState"); in LowerFormalArguments()
192 MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg); in LowerFormalArguments()
244 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
269 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Opi, SDValue()); in LowerReturn()
330 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
391 unsigned Reg = RV.getLocReg(); in LowerCall()
|
| /external/llvm/lib/CodeGen/ |
| D | CallingConvLower.cpp | 222 Regs.push_back(MCPhysReg(Locs[I].getLocReg())); in getRemainingRegParmsForType()
279 if (Loc1.getLocReg() != Loc2.getLocReg()) in resultsCompatible()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1636 VA.getLocReg()) in ProcessCallArgs()
1638 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1649 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
1650 .addReg(NextVA.getLocReg(), RegState::Define) in ProcessCallArgs()
1652 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1653 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
1692 .addReg(RVLocs[0].getLocReg()) in FinishCall()
1693 .addReg(RVLocs[1].getLocReg())); in FinishCall()
1695 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
1696 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
[all …]
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| D | ARMISelLowering.cpp | 1123 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1128 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1140 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1144 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1152 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), in LowerCallResult()
1197 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); in PassF64ArgInRegs()
1200 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1))); in PassF64ArgInRegs()
1322 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
1700 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) in IsEligibleForTailCallOptimization()
1787 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
[all …]
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 183 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
291 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
375 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
380 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
413 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(), in LowerCallResult()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 249 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag); in LowerReturn_32()
251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
253 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
256 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); in LowerReturn_32()
260 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
343 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
351 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn_64()
355 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
420 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
435 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments_32()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 104 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
114 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
187 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments()
202 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments()
213 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
479 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); in LowerCall()
483 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); in LowerCall()
517 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
521 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
600 unsigned Reg = RVLocs[i].getLocReg(); in LowerCall()
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86FastISel.cpp | 750 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) in X86SelectRet()
779 unsigned DstReg = VA.getLocReg(); in X86SelectRet()
788 MRI.addLiveOut(VA.getLocReg()); in X86SelectRet()
1724 VA.getLocReg()).addReg(Arg); in DoSelectCall()
1725 RegArgs.push_back(VA.getLocReg()); in DoSelectCall()
1879 if ((RVLocs[i].getLocReg() == X86::ST0 || in DoSelectCall()
1880 RVLocs[i].getLocReg() == X86::ST1)) { in DoSelectCall()
1889 CopyReg).addReg(RVLocs[i].getLocReg()); in DoSelectCall()
1890 UsedRegs.push_back(RVLocs[i].getLocReg()); in DoSelectCall()
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 331 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
429 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
528 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), in LowerCallResult()
575 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
595 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag); in LowerReturn()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1977 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg); in ProcessCallArgs()
1978 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1990 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
1991 .addReg(NextVA.getLocReg(), RegState::Define) in ProcessCallArgs()
1993 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1994 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
2040 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2041 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2043 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2044 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 742 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
849 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
897 ArgRegEnd = VA.getLocReg(); in LowerFormalArguments()
1028 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
1038 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 339 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
410 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
420 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
492 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
583 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 448 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
533 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
539 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
604 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
705 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1175 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
1176 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
1243 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1244 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
1482 unsigned DestReg = VA.getLocReg(); in selectRet()
1517 RetRegs.push_back(VA.getLocReg()); in selectRet()
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 121 unsigned getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg() function
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 579 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
583 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
633 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
643 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
785 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
1109 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1114 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1122 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1129 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1137 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
[all …]
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 448 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
542 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
546 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
674 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
775 Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(), in LowerCallResult()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1207 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in X86SelectRet()
1236 unsigned DstReg = VA.getLocReg(); in X86SelectRet()
1245 RetRegs.push_back(VA.getLocReg()); in X86SelectRet()
3214 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in fastLowerCall()
3215 OutRegs.push_back(VA.getLocReg()); in fastLowerCall()
3366 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) && in fastLowerCall()
3374 TII.get(TargetOpcode::COPY), CopyReg).addReg(VA.getLocReg()); in fastLowerCall()
3375 InRegs.push_back(VA.getLocReg()); in fastLowerCall()
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| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 947 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
1036 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
1117 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
1226 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
1236 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 148 unsigned getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg() function
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2022 unsigned LocRegLo = VA.getLocReg(); in LowerCall()
2044 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
2204 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
2278 unsigned ArgReg = VA.getLocReg(); in LowerFormalArguments()
2440 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
2450 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1079 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), in LowerCallResult()
1174 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
1324 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
1514 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
1519 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelLowering.cpp | 281 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
365 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), in LowerCallResult()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 1420 unsigned SourcePhysReg = VA.getLocReg(); in finishCall()
1630 unsigned RetReg = VA.getLocReg(); in SelectRet()
1654 RetRegs.push_back(VA.getLocReg()); in SelectRet()
|