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Searched refs:getLocVT (Results 1 – 25 of 35) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelLowering.cpp185 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
211 unsigned ObjSize = VA.getLocVT().getStoreSize(); in LowerFormalArguments()
260 Opi = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Opi); in LowerReturn()
263 Opi = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Opi); in LowerReturn()
266 Opi = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Opi); in LowerReturn()
317 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
320 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
323 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
335 assert(VA.getLocVT()==MVT::i32 && "Illegal CCValAssign type"); in LowerCall()
394 RVLocs[i].getLocVT(), InFlag); in LowerCall()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZISelLowering.cpp307 EVT LocVT = VA.getLocVT(); in LowerCCCArguments()
416 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
419 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
422 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
529 VA.getLocVT(), InFlag).getValue(1); in LowerCallResult()
537 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue, in LowerCallResult()
540 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue, in LowerCallResult()
589 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue); in LowerReturn()
591 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue); in LowerReturn()
593 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue); in LowerReturn()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp238 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
260 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
323 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
326 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
329 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
355 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
417 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerFormalArguments_32()
445 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue); in LowerFormalArguments_32()
452 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments_32()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86FastISel.cpp1679 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in DoSelectCall()
1681 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), in DoSelectCall()
1684 ArgVT = VA.getLocVT(); in DoSelectCall()
1688 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in DoSelectCall()
1690 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), in DoSelectCall()
1693 ArgVT = VA.getLocVT(); in DoSelectCall()
1697 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in DoSelectCall()
1699 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), in DoSelectCall()
1702 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), in DoSelectCall()
1705 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), in DoSelectCall()
[all …]
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp174 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
203 InVals.push_back(DAG.getConstant(0, DL, VA.getLocVT())); in LowerFormalArguments()
279 Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
282 Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
285 Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
380 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparcISelLowering.cpp185 assert(VA.getLocVT() == MVT::f64); in LowerFormalArguments()
215 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments()
217 else if (VA.getLocVT() != MVT::i32) { in LowerFormalArguments()
219 DAG.getValueType(VA.getLocVT())); in LowerFormalArguments()
220 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); in LowerFormalArguments()
421 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
424 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
427 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
430 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
448 assert(VA.getLocVT() == MVT::f64); in LowerCall()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMFastISel.cpp1593 bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), in ProcessCallArgs()
1597 ArgVT = VA.getLocVT(); in ProcessCallArgs()
1601 bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), in ProcessCallArgs()
1605 ArgVT = VA.getLocVT(); in ProcessCallArgs()
1609 bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), in ProcessCallArgs()
1612 Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), in ProcessCallArgs()
1615 Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), in ProcessCallArgs()
1619 ArgVT = VA.getLocVT(); in ProcessCallArgs()
1623 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg, in ProcessCallArgs()
1627 ArgVT = VA.getLocVT(); in ProcessCallArgs()
[all …]
DARMISelLowering.cpp1134 if (VA.getLocVT() == MVT::v2f64) { in LowerCallResult()
1152 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), in LowerCallResult()
1283 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1286 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1289 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1292 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
1298 if (VA.getLocVT() == MVT::v2f64) { in LowerCall()
1732 EVT RegVT = VA.getLocVT(); in IsEligibleForTailCallOptimization()
1805 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerReturn()
1810 if (VA.getLocVT() == MVT::v2f64) { in LowerReturn()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
DMSP430ISelLowering.cpp326 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
361 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
364 << EVT(VA.getLocVT()).getEVTString() in LowerCCCArguments()
373 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
479 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
482 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
485 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp436 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
479 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
482 << EVT(VA.getLocVT()).getEVTString() in LowerCCCArguments()
492 VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
539 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
591 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
594 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
597 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp2722 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); in LowerCall()
2794 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCall()
2796 ISD::SHL, DL, VA.getLocVT(), Arg, in LowerCall()
2797 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in LowerCall()
2915 RVLocs[i].getLocVT(), InFlag); in LowerCallResult()
2921 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCallResult()
2925 Shift, DL, VA.getLocVT(), Val, in LowerCallResult()
2926 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in LowerCallResult()
2943 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
2949 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult()
[all …]
/external/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp444 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
476 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8; in LowerCCCArguments()
480 << EVT(VA.getLocVT()).getEVTString() << "\n"; in LowerCCCArguments()
489 VA.getLocVT(), DL, Chain, FIN, in LowerCCCArguments()
546 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
655 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
658 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
661 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaISelLowering.cpp268 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
271 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
274 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
366 VA.getLocVT(), InFlag).getValue(1); in LowerCallResult()
374 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue, in LowerCallResult()
377 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue, in LowerCallResult()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp3142 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3148 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3151 ArgVT = VA.getLocVT(); in fastLowerCall()
3155 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3168 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3171 ArgVT = VA.getLocVT(); in fastLowerCall()
3175 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3177 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3180 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3183 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreISelLowering.cpp934 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
937 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
940 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1104 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
1124 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
1127 << EVT(VA.getLocVT()).getEVTString() in LowerCCCArguments()
1138 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1161 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1164 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1167 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1312 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
1332 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
1335 << EVT(VA.getLocVT()).getEVTString() in LowerCCCArguments()
1346 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
1490 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8; in LowerReturn()
1519 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DCallingConvLower.h123 MVT getLocVT() const { return LocVT; } in getLocVT() function
/external/llvm/lib/Target/ARM/
DARMCallingConv.h188 assert(PendingMembers[0].getLocVT() == LocVT); in CC_ARM_AAPCS_Custom_Aggregate()
DARMFastISel.cpp1898 if (VA.getLocVT() != MVT::f64 || in ProcessCallArgs()
1948 MVT DestVT = VA.getLocVT(); in ProcessCallArgs()
1957 MVT DestVT = VA.getLocVT(); in ProcessCallArgs()
1964 unsigned BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg, in ProcessCallArgs()
1968 ArgVT = VA.getLocVT(); in ProcessCallArgs()
1981 assert(VA.getLocVT() == MVT::f64 && in ProcessCallArgs()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeISelLowering.cpp721 MVT RegVT = VA.getLocVT(); in LowerCall()
896 MVT RegVT = VA.getLocVT(); in LowerFormalArguments()
944 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8; in LowerFormalArguments()
/external/llvm/include/llvm/CodeGen/
DCallingConvLower.h151 MVT getLocVT() const { return LocVT; } in getLocVT() function
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp815 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
818 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
826 assert(VA.getLocVT() == MVT::i64); in convertLocVTToValVT()
842 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
844 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
846 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
850 assert(VA.getLocVT() == MVT::i64); in convertValVTToLocVT()
853 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value, in convertValVTToLocVT()
889 EVT LocVT = VA.getLocVT(); in LowerFormalArguments()
937 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32) in LowerFormalArguments()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp583 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
749 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
752 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
755 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
766 VA.getLocVT().getStoreSizeInBits() >> 3); in LowerCall()
1104 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
1166 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3; in LowerFormalArguments()
1183 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerFormalArguments()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsISelLowering.cpp2013 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32) in LowerCall()
2015 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) { in LowerCall()
2031 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
2034 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
2037 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
2277 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1345 MVT DestVT = VA.getLocVT(); in processCallArgs()
1357 MVT DestVT = VA.getLocVT(); in processCallArgs()
1661 MVT DestVT = VA.getLocVT(); in SelectRet()

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