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Searched refs:getOperandIdx (Results 1 – 9 of 9) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DR600ClauseMergePass.cpp77 .getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::COUNT)) in getCFAluSize()
84 .getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::Enabled)) in isCFAluEnabled()
90 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT); in cleanPotentialDisabledCFAlu()
109 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT); in mergeIfPossible()
121 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE0); in mergeIfPossible()
123 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK0); in mergeIfPossible()
125 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR0); in mergeIfPossible()
137 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE1); in mergeIfPossible()
139 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK1); in mergeIfPossible()
141 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR1); in mergeIfPossible()
DR600ExpandSpecialInstrs.cpp60 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI()
83 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); in runOnMachineFunction()
89 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(), in runOnMachineFunction()
91 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(), in runOnMachineFunction()
223 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0)) in runOnMachineFunction()
226 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1)) in runOnMachineFunction()
273 TII->getOperandIdx(MI, AMDGPU::OpName::dst)).getReg(); in runOnMachineFunction()
275 TII->getOperandIdx(MI, AMDGPU::OpName::src0)).getReg(); in runOnMachineFunction()
280 int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::src1); in runOnMachineFunction()
DR600InstrInfo.cpp71 NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0)) in copyPhysReg()
148 return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) == -1; in isLDSNoRetInstr()
152 return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) != -1; in isLDSRetInstr()
259 return getOperandIdx(Opcode, OpTable[SrcNum]); in getSrcIdx()
278 if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) { in getSelIdx()
279 return getOperandIdx(Opcode, Row[1]); in getSelIdx()
303 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][0])); in getSrcs()
307 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1])); in getSrcs()
323 int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]); in getSrcs()
330 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1])); in getSrcs()
[all …]
DR600Packetizer.cpp89 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write); in getPreviousVector()
92 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst); in getPreviousVector()
139 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Ops[i]); in substitutePV()
190 int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel), in isLegalToPacketizeTogether()
191 OpJ = TII->getOperandIdx(MIJ->getOpcode(), AMDGPU::OpName::pred_sel); in isLegalToPacketizeTogether()
225 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::last); in setIsLastBit()
305 unsigned Op = TII->getOperandIdx(MI->getOpcode(), in addToPacket()
310 TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::bank_swizzle); in addToPacket()
DR600ISelLowering.cpp223 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); in EmitInstrWithCustomInserter()
288 int Idx = TII->getOperandIdx(*MIB, AMDGPU::OpName::literal); in EmitInstrWithCustomInserter()
2192 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1; in FoldOperand()
2203 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0), in FoldOperand()
2204 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1), in FoldOperand()
2205 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2), in FoldOperand()
2206 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X), in FoldOperand()
2207 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y), in FoldOperand()
2208 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z), in FoldOperand()
2209 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W), in FoldOperand()
[all …]
DR600InstrInfo.h289 int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
294 int getOperandIdx(unsigned Opcode, unsigned Op) const;
DR600MachineScheduler.cpp358 int DstIndex = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst); in AssignSlot()
DR600Instructions.td92 // and R600InstrInfo::getOperandIdx().
133 // R600InstrInfo::buildDefaultInstruction(), and R600InstrInfo::getOperandIdx().
174 // R600InstrInfo::getOperandIdx().
DR600ControlFlowFinalizer.cpp364 TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::literal)); in getLiteral()