| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 168 // t_addrmode_is4 := reg + imm5 * 4
180 // t_addrmode_is2 := reg + imm5 * 2
192 // t_addrmode_is1 := reg + imm5
575 // Loads: reg/reg and reg/imm5
587 def i : // reg/imm5
593 // Stores: reg/reg and reg/imm5
604 def i : // reg/imm5
909 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
911 "asr", "\t$Rd, $Rm, $imm5",
912 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
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| D | ARMInstrFormats.td | 1021 let Inst{10-6} = addr{7-3}; // imm5
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| D | ARMInstrInfo.td | 437 // {4-0} imm5 shift amount.
438 // asr #32 encoded as imm5 == 0.
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| D | ARMInstrThumb2.td | 35 // {4-0} imm5 shift amount.
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 214 // t_addrmode_is4 := reg + imm5 * 4
226 // t_addrmode_is2 := reg + imm5 * 2
238 // t_addrmode_is1 := reg + imm5
658 // Loads: reg/reg and reg/imm5
668 def i : // reg/imm5
680 // Stores: reg/reg and reg/imm5
686 def i : // reg/imm5
962 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
964 "asr", "\t$Rd, $Rm, $imm5",
965 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
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| D | ARMInstrFormats.td | 1178 let Inst{10-6} = addr{7-3}; // imm5
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| D | ARMInstrInfo.td | 530 // {4-0} imm5 shift amount.
531 // asr #32 encoded as imm5 == 0.
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| D | ARMInstrThumb2.td | 35 // {4-0} imm5 shift amount.
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrFormats.td | 167 bits<5> imm5;
174 let Inst{27-31} = imm5;
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| /external/valgrind/VEX/priv/ |
| D | guest_arm64_toIR.c | 3195 UInt imm5 = INSN(20,16); in dis_ARM64_data_processing_register() local
3209 assign(argR, mkU64(imm5)); in dis_ARM64_data_processing_register()
3212 assign(argR, mkU32(imm5)); in dis_ARM64_data_processing_register()
3218 imm5, nzcv, nameCC(cond)); in dis_ARM64_data_processing_register()
7658 IRExpr* srcV, UInt imm5 ) in handle_DUP_VEC_ELEM() argument
7664 if (imm5 & 1) { in handle_DUP_VEC_ELEM()
7665 *laneNo = (imm5 >> 1) & 15; in handle_DUP_VEC_ELEM()
7669 else if (imm5 & 2) { in handle_DUP_VEC_ELEM()
7670 *laneNo = (imm5 >> 2) & 7; in handle_DUP_VEC_ELEM()
7674 else if (imm5 & 4) { in handle_DUP_VEC_ELEM()
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| D | guest_arm_toIR.c | 1599 UInt imm5 ) /* saturation ceiling */ in armUnsignedSatQ() argument
1601 UInt ceil = (1 << imm5) - 1; // (2^imm5)-1 in armUnsignedSatQ()
1641 UInt imm5, /* saturation ceiling */ in armSignedSatQ() argument
1645 Int ceil = (1 << (imm5-1)) - 1; // (2^(imm5-1))-1 in armSignedSatQ()
1646 Int floor = -(1 << (imm5-1)); // -(2^(imm5-1)) in armSignedSatQ()
2389 UInt sh2, UInt imm5, in mk_EA_reg_plusminus_shifted_reg() argument
2396 vassert(imm5 < 32); in mk_EA_reg_plusminus_shifted_reg()
2402 index = binop(Iop_Shl32, getIRegA(rM), mkU8(imm5)); in mk_EA_reg_plusminus_shifted_reg()
2403 DIS(buf, "[r%u, %c r%u LSL #%u]", rN, opChar, rM, imm5); in mk_EA_reg_plusminus_shifted_reg()
2406 if (imm5 == 0) { in mk_EA_reg_plusminus_shifted_reg()
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| D | host_tilegx_defs.h | 206 UInt imm5; member
214 extern TILEGXRI5 *TILEGXRI5_I5 ( UInt imm5 );
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| D | host_arm_defs.h | 275 UInt imm5; member
284 extern ARMRI5* ARMRI5_I5 ( UInt imm5 );
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| D | host_arm_defs.c | 480 ARMRI5* ARMRI5_I5 ( UInt imm5 ) { in ARMRI5_I5() argument
483 ri5->ARMri5.I5.imm5 = imm5; in ARMRI5_I5()
484 vassert(imm5 > 0 && imm5 <= 31); // zero is not allowed in ARMRI5_I5()
497 vex_printf("%u", ri5->ARMri5.I5.imm5); in ppARMRI5()
2785 UInt imm5 = ri->ARMri5.I5.imm5; in skeletal_RI5() local
2786 vassert(imm5 >= 1 && imm5 <= 31); in skeletal_RI5()
2788 instr |= imm5 << 7; in skeletal_RI5()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrFormats.td | 229 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
238 bits<5> imm5;
245 let Inst{4-0} = imm5;
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | README.txt | 80 | Ks5 | imm5 | |
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 2796 static Instr ImmPrefetchOperation(int imm5) { in ImmPrefetchOperation() argument
2797 VIXL_ASSERT(IsUint5(imm5)); in ImmPrefetchOperation()
2798 return imm5 << ImmPrefetchOperation_offset; in ImmPrefetchOperation()
3018 int imm5 = (index << (s + 1)) | (1 << s); in ImmNEON5() local
3019 return imm5 << ImmNEON5_offset; in ImmNEON5()
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| D | simulator-aarch64.cc | 3876 int imm5 = instr->GetImmNEON5(); in VisitNEONCopy() local
3877 int tz = CountTrailingZeros(imm5, 32); in VisitNEONCopy()
3878 int reg_index = imm5 >> (tz + 1); in VisitNEONCopy()
4786 int imm5 = instr->GetImmNEON5(); in VisitNEONScalarCopy() local
4787 int tz = CountTrailingZeros(imm5, 32); in VisitNEONScalarCopy()
4788 int rn_index = imm5 >> (tz + 1); in VisitNEONScalarCopy()
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| D | disasm-aarch64.cc | 4442 unsigned imm5 = instr->GetImmNEON5(); in SubstituteImmediateField() local
4444 int tz = CountTrailingZeros(imm5, 32); in SubstituteImmediateField()
4446 rd_index = imm5 >> (tz + 1); in SubstituteImmediateField()
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| /external/v8/src/arm/ |
| D | assembler-arm.cc | 3177 int imm5 = 32 - fraction_bits; in vcvt_f64_s32() local
3178 int i = imm5 & 1; in vcvt_f64_s32()
3179 int imm4 = (imm5 >> 1) & 0xf; in vcvt_f64_s32()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 6104 class SIMDDupFromMain<bit Q, bits<5> imm5, string size, ValueType vectype,
6110 let Inst{20-16} = imm5;
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| /external/valgrind/none/tests/arm/ |
| D | v6intThumb.stdout.exp | 757 LSLS-16 Rd, Rm, imm5
782 LSRS-16 Rd, Rm, imm5
807 ASRS-16 Rd, Rm, imm5
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