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/external/llvm/lib/Target/XCore/
DXCoreInstrFormats.td36 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
38 let Inst{15-11} = opc;
45 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
46 : _F3R<opc, outs, ins, asmstr, pattern> {
50 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
52 let Inst{31-27} = opc{8-4};
54 let Inst{19-16} = opc{3-0};
61 class _FL3RSrcDst<bits<9> opc, dag outs, dag ins, string asmstr,
62 list<dag> pattern> : _FL3R<opc, outs, ins, asmstr, pattern> {
66 class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
[all …]
/external/valgrind/auxprogs/
Ds390-check-opcodes.pl202 foreach my $opc (keys %opc_desc) {
203 if (! $csv_desc{$opc}) {
204 print "*** opcode $opc not listed in $csv_file\n";
207 foreach my $opc (keys %csv_desc) {
208 if (! $opc_desc{$opc}) {
209 print "*** opcode $opc not listed in $opc_file\n";
216 foreach my $opc (keys %opc_desc) {
217 if (defined $csv_desc{$opc}) {
218 if ($opc_desc{$opc} ne $csv_desc{$opc}) {
219 print "*** opcode $opc differs:\n";
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrEnc.td1 class Enc_COPROC_VX_3op_v<bits<15> opc> : OpcodeHexagon {
6 let Inst{31-16} = { opc{14-4}, src2};
7 let Inst{13-0} = { opc{3}, src1, opc{2-0}, dst};
196 class Enc_COPROC_VX_cmp<bits<13> opc> : OpcodeHexagon {
201 let Inst{31-16} = { 0b00011, opc{12-7}, src2{4-0} };
202 let Inst{13-0} = { opc{6}, src1{4-0}, opc{5-0}, dst{1-0} };
244 class Enc_COPROC_VX_p2op<bits<5> opc> : OpcodeHexagon {
249 let Inst{31-16} = { 0b00011110, src1{1-0}, 0b0000, opc{4-3} };
250 let Inst{13-0} = { 1, src2{4-0}, opc{2-0}, dst{4-0} };
266 class Enc_COPROC_VX_2op<bits<6> opc> : OpcodeHexagon {
[all …]
/external/wpa_supplicant_8/src/crypto/
Dmilenage.c36 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f1() argument
44 tmp1[i] = _rand[i] ^ opc[i]; in milenage_f1()
57 tmp3[(i + 8) % 16] = tmp2[i] ^ opc[i]; in milenage_f1()
67 tmp1[i] ^= opc[i]; in milenage_f1()
88 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand, in milenage_f2345() argument
96 tmp1[i] = _rand[i] ^ opc[i]; in milenage_f2345()
108 tmp1[i] = tmp2[i] ^ opc[i]; in milenage_f2345()
114 tmp3[i] ^= opc[i]; in milenage_f2345()
124 tmp1[(i + 12) % 16] = tmp2[i] ^ opc[i]; in milenage_f2345()
129 ck[i] ^= opc[i]; in milenage_f2345()
[all …]
Dmilenage.h12 void milenage_generate(const u8 *opc, const u8 *amf, const u8 *k,
15 int milenage_auts(const u8 *opc, const u8 *k, const u8 *_rand, const u8 *auts,
17 int gsm_milenage(const u8 *opc, const u8 *k, const u8 *_rand, u8 *sres,
19 int milenage_check(const u8 *opc, const u8 *k, const u8 *sqn, const u8 *_rand,
22 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand,
24 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand,
/external/swiftshader/third_party/LLVM/test/TableGen/
DDefmInsideMultiClass.td4 class Instruction<bits<4> opc, string Name> {
5 bits<4> opcode = opc;
9 multiclass basic_r<bits<4> opc> {
10 def rr : Instruction<opc, "rr">;
11 def rm : Instruction<opc, "rm">;
14 multiclass basic_s<bits<4> opc> {
15 defm SS : basic_r<opc>;
16 defm SD : basic_r<opc>;
19 multiclass basic_p<bits<4> opc> {
20 defm PS : basic_r<opc>;
[all …]
DLetInsideMultiClasses.td4 class Instruction<bits<4> opc, string Name> {
5 bits<4> opcode = opc;
10 multiclass basic_r<bits<4> opc> {
12 def rr : Instruction<opc, "rr">;
13 def rm : Instruction<opc, "rm">;
17 def rx : Instruction<opc, "rx">;
20 multiclass basic_ss<bits<4> opc> {
22 defm SS : basic_r<opc>;
25 defm SD : basic_r<opc>;
/external/llvm/test/TableGen/
DDefmInsideMultiClass.td7 class Instruction<bits<4> opc, string Name> {
8 bits<4> opcode = opc;
12 multiclass basic_r<bits<4> opc> {
13 def rr : Instruction<opc, "rr">;
14 def rm : Instruction<opc, "rm">;
17 multiclass basic_s<bits<4> opc> {
18 defm SS : basic_r<opc>;
19 defm SD : basic_r<opc>;
22 multiclass basic_p<bits<4> opc> {
23 defm PS : basic_r<opc>;
[all …]
DLetInsideMultiClasses.td9 class Instruction<bits<4> opc, string Name> {
10 bits<4> opcode = opc;
15 multiclass basic_r<bits<4> opc> {
17 def rr : Instruction<opc, "rr">;
18 def rm : Instruction<opc, "rm">;
22 def rx : Instruction<opc, "rx">;
25 multiclass basic_ss<bits<4> opc> {
27 defm SS : basic_r<opc>;
30 defm SD : basic_r<opc>;
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUInstrInfo.cpp33 unsigned opc = I->getOpcode(); in isUncondBranch() local
35 return (opc == SPU::BR in isUncondBranch()
36 || opc == SPU::BRA in isUncondBranch()
37 || opc == SPU::BI); in isUncondBranch()
42 unsigned opc = I->getOpcode(); in isCondBranch() local
44 return (opc == SPU::BRNZr32 in isCondBranch()
45 || opc == SPU::BRNZv4i32 in isCondBranch()
46 || opc == SPU::BRZr32 in isCondBranch()
47 || opc == SPU::BRZv4i32 in isCondBranch()
48 || opc == SPU::BRHNZr16 in isCondBranch()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrAVX512.td798 multiclass avx512_broadcast_scalar<bits<8> opc, string OpcodeStr,
802 def r_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst),
808 def rk_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst),
817 def rkz_s : I< opc, MRMSrcReg, (outs DestInfo.RC:$dst),
828 multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
831 defm r : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
835 defm m : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
842 defm m_Int : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
851 multiclass avx512_fp_broadcast_vl<bits<8> opc, string OpcodeStr,
853 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
[all …]
DX86InstrXOP.td14 multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
18 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
42 multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
44 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
47 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
52 multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
54 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
57 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
62 multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
[all …]
DX86Instr3DNow.td36 multiclass I3DNow_binop_rm<bits<8> opc, string Mn> {
37 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, []>;
38 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn, []>;
41 multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn, string Ver = ""> {
42 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
45 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn,
51 multiclass I3DNow_conv_rm<bits<8> opc, string Mn> {
52 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src1), Mn, []>;
53 def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src1), Mn, []>;
56 multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn, string Ver = ""> {
[all …]
DX86InstrMPX.td16 multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> {
17 def 32rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins i32mem:$src),
20 def 64rm: RI<opc, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
27 multiclass mpx_bound_check<bits<8> opc, string OpcodeStr> {
28 def 32rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, i32mem:$src2),
31 def 64rm: RI<opc, MRMSrcMem, (outs), (ins BNDR:$src1, i64mem:$src2),
34 def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2),
37 def 64rr: RI<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2),
DX86InstrFMA.td38 multiclass fma3p_rm<bits<8> opc, string OpcodeStr,
43 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
51 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
59 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
67 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
143 multiclass fma3s_rm<bits<8> opc, string OpcodeStr,
147 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
154 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
177 multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr,
179 def r_Int : FMA3<opc, MRMSrcReg, (outs RC:$dst),
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DX86InstrCMovSetCC.td17 multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
21 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
27 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
33 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
43 : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
49 : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
55 :RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
83 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
85 def r : I<opc, MRMXr, (outs GR8:$dst), (ins),
89 def m : I<opc, MRMXm, (outs), (ins i8mem:$dst),
/external/llvm/lib/Target/ARM/
DARMInstrFormats.td430 string opc, string asm, string cstr,
437 let AsmString = !strconcat(opc, "${p}", asm);
445 string opc, string asm, string cstr,
450 let AsmString = !strconcat(opc, asm);
461 string opc, string asm, string cstr,
471 let AsmString = !strconcat(opc, "${s}${p}", asm);
489 string opc, string asm, list<dag> pattern>
491 opc, asm, "", pattern>;
493 string opc, string asm, list<dag> pattern>
495 opc, asm, "", pattern>;
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrFormats.td348 string opc, string asm, string cstr,
355 let AsmString = !strconcat(opc, "${p}", asm);
363 string opc, string asm, string cstr,
368 let AsmString = !strconcat(opc, asm);
379 string opc, string asm, string cstr,
389 let AsmString = !strconcat(opc, "${s}${p}", asm);
407 string opc, string asm, list<dag> pattern>
409 opc, asm, "", pattern>;
411 string opc, string asm, list<dag> pattern>
413 opc, asm, "", pattern>;
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td879 class CRmSystemI<Operand crmtype, bits<3> opc, string asm,
886 let Inst{7-5} = opc;
1045 // case opc of
1052 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm,
1056 let Inst{24-21} = opc;
1062 class BranchReg<bits<4> opc, string asm, list<dag> pattern>
1063 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
1069 class SpecialReturn<bits<4> opc, string asm>
1070 : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
1270 class BaseOneOperandData<bits<3> opc, RegisterClass regtype, string asm,
[all …]
/external/libunwind/src/ia64/
DGscript.c267 enum ia64_script_insn_opcode opc; in compile_reg() local
275 opc = IA64_INSN_MOVE; in compile_reg()
286 opc = IA64_INSN_MOVE_STACKED_NAT; in compile_reg()
288 opc = IA64_INSN_MOVE_STACKED; in compile_reg()
296 opc = IA64_INSN_MOVE_NAT; in compile_reg()
302 opc = IA64_INSN_MOVE_SCRATCH_NAT; in compile_reg()
304 opc = IA64_INSN_MOVE_SCRATCH; in compile_reg()
323 opc = IA64_INSN_MOVE_SCRATCH; in compile_reg()
333 opc = IA64_INSN_MOVE_NO_NAT; in compile_reg()
337 opc = IA64_INSN_MOVE_SCRATCH; in compile_reg()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86Instr3DNow.td36 multiclass I3DNow_binop_rm<bits<8> opc, string Mn> {
37 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, []>;
38 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn, []>;
41 multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn, string Ver = ""> {
42 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
45 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn,
51 multiclass I3DNow_conv_rm<bits<8> opc, string Mn> {
52 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src1), Mn, []>;
53 def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src1), Mn, []>;
56 multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn, string Ver = ""> {
[all …]
DX86InstrCMovSetCC.td17 multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
21 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
26 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
31 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
39 : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
44 : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
49 :RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
77 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
79 def r : I<opc, MRM0r, (outs GR8:$dst), (ins),
82 def m : I<opc, MRM0m, (outs), (ins i8mem:$dst),
/external/clang/lib/StaticAnalyzer/Checkers/
DMallocOverflowSecurityChecker.cpp83 BinaryOperatorKind opc = binop->getOpcode(); in CheckMallocArgument() local
85 if (mulop == nullptr && opc == BO_Mul) in CheckMallocArgument()
87 if (opc != BO_Mul && opc != BO_Add && opc != BO_Sub && opc != BO_Shl) in CheckMallocArgument()
95 if (EvaluatesToZero(maxVal, opc)) in CheckMallocArgument()
97 } else if ((opc == BO_Add || opc == BO_Mul) && in CheckMallocArgument()
100 if (EvaluatesToZero(maxVal, opc)) in CheckMallocArgument()
/external/valgrind/none/tests/tilegx/
Dgen_insn_test.c179 const struct tilegx_opcode *opc = in encode_insn_tilegx_X() local
185 int op_num = opc->num_operands; in encode_insn_tilegx_X()
188 if ((opc->pipes & 3) == 0) in encode_insn_tilegx_X()
198 insn |= opc->fixed_bit_values[p]; in encode_insn_tilegx_X()
232 &tilegx_operands[opc->operands[p][i]]; in encode_insn_tilegx_X()
279 &tilegx_operands[opc->operands[p][i]]; in encode_insn_tilegx_X()
340 &tilegx_operands[opc->operands[p][i]]; in encode_insn_tilegx_X()
382 &tilegx_operands[opc->operands[p][i]]; in encode_insn_tilegx_X()
417 const struct tilegx_opcode *opc = in encode_insn_tilegx_Y() local
424 Int op_num = opc->num_operands; in encode_insn_tilegx_Y()
[all …]
/external/autotest/client/cros/cellular/
Dprologix_scpi_driver_test_noautorun.py43 self._get_idns_and_verify(instruments=[instr], opc=True)
66 self._get_idns_and_verify(instruments=[instr], opc=True)
158 self._get_idns_and_verify(instruments=scpi_instruments, opc=True)
164 self._get_idns_and_verify(instruments=scpi_instruments, opc=False)
184 def _get_idns_and_verify(self, instruments, opc=False): argument
190 scpi_connection = self._open_prologix(instr, opc_on_stanza=opc)

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