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Searched refs:v2i16 (Results 1 – 25 of 62) sorted by relevance

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/external/clang/test/CodeGen/
Dbuiltins-mips.c12 typedef short v2i16 __attribute__ ((vector_size(4))); typedef
17 v2i16 v2i16_r, v2i16_a, v2i16_b, v2i16_c; in foo()
352 v2i16_a = (v2i16) {0xffff, 0x2468}; in foo()
353 v2i16_b = (v2i16) {0x1234, 0x1111}; in foo()
356 v2i16_a = (v2i16) {0xffff, 0x2468}; in foo()
357 v2i16_b = (v2i16) {0x1234, 0x1111}; in foo()
392 v2i16_b = (v2i16) {0xffff, 0x1555}; in foo()
393 v2i16_c = (v2i16) {0x1234, 0x3322}; in foo()
397 v2i16_b = (v2i16) {0xffff, 0x1555}; in foo()
398 v2i16_c = (v2i16) {0x1234, 0x3322}; in foo()
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Dppc64-vector.c3 typedef short v2i16 __attribute__((vector_size (4))); typedef
13 v2i16 test_v2i16(v2i16 x) in test_v2i16()
Dsystemz-abi-vector.c16 typedef __attribute__((vector_size(4))) short v2i16; typedef
70 v2i16 pass_v2i16(v2i16 arg) { return arg; } in pass_v2i16()
Dx86_32-arguments-darwin.c217 typedef unsigned short v2i16 __attribute__((__vector_size__(4))); typedef
221 v2i16 f54(v2i16 arg) { return arg+arg; } in f54()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoVector.td18 def V2I16: PatLeaf<(v2i16 IntRegs:$R)>;
40 defm : bitconvert_32<v2i16, i32>;
69 def : Pat<(v2i16 (add (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
72 def : Pat<(v2i16 (sub (v2i16 IntRegs:$src1), (v2i16 IntRegs:$src2))),
268 def: Pat<(v2i16 (select I1:$Pu, V2I16:$Rs, V2I16:$Rt)),
339 def: Pat<(v2i16 (trunc V2I32:$Rs)),
360 // Sign extends a v2i16 into a v2i32.
361 def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)),
365 // Multiplies two v2i16 and returns a v2i32. We are using here the
370 // Multiplies two v2i16 vectors: as Hexagon does not have a multiply
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/external/llvm/test/CodeGen/ARM/
D2012-08-23-legalize-vmull.ll39 ; v2i16
86 ; v2i16
121 ; v2i8 x v2i16
136 ; v2i16
137 ; v2i16 x v2i32
/external/llvm/test/CodeGen/PowerPC/
Dbitreverse.ll6 declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone
11 %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td1317 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1319 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1322 def : DSPPat<(v2i16 (load addr:$a)),
1323 (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1326 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1336 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1337 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1338 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1339 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1340 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
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/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp224 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
227 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
248 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost()
251 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost()
265 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
268 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
279 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
282 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h79 v2i16 = 31, // 2 x i16 enumerator
234 return (SimpleTy == MVT::v4i8 || SimpleTy == MVT::v2i16 || in is32BitVector()
335 case v2i16: in getVectorElementType()
413 case v2i16: in getVectorNumElements()
463 case v2i16: in getSizeInBits()
615 if (NumElements == 2) return MVT::v2i16; in getVectorVT()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DValueTypes.h59 v2i16 = 17, // 2 x i16 enumerator
195 case v2i16: in getVectorElementType()
233 case v2i16: in getVectorNumElements()
259 case v2i16: return 32; in getSizeInBits()
346 if (NumElements == 2) return MVT::v2i16; in getVectorVT()
/external/llvm/test/CodeGen/SystemZ/
Dvec-const-02.ll49 ; Test an all-zeros v2i16 that gets promoted to v8i16.
57 ; Test a mixed v2i16 that gets promoted to v8i16 (mask 0xc000).
Dvec-shift-07.ll92 ; Test a v2i16->v2i64 extension.
122 ; Test an alternative v2i16->v2i64 extension.
156 ; Test an extraction-based v2i16->v2i64 extension.
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dwiden_conv-3.ll4 ; sign to float v2i16 to v2f32
Dwiden_conv-2.ll5 ; sign extension v2i32 to v2i16
/external/llvm/test/CodeGen/X86/
D2011-12-8-bitcastintprom.ll3 ; Make sure that the conversion between v4i8 to v2i16 is not a simple bitcast.
Dbitreverse.ll7 declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone
139 %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
320 %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> <i16 15, i16 3840>)
369 %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
370 %c = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %b)
388 %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> undef)
Dwiden_compare-1.ll5 ; compare v2i16
Dwiden_conv-2.ll5 ; sign extension v2i16 to v2i32
/external/llvm/test/CodeGen/AArch64/
Dbitreverse.ll6 declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone
12 %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
/external/llvm/include/llvm/IR/
DIntrinsicsNVVM.td1836 "llvm.nvvm.suld.1d.v2i16.clamp">;
1881 "llvm.nvvm.suld.1d.array.v2i16.clamp">;
1926 "llvm.nvvm.suld.2d.v2i16.clamp">;
1971 "llvm.nvvm.suld.2d.array.v2i16.clamp">;
2016 "llvm.nvvm.suld.3d.v2i16.clamp">;
2062 "llvm.nvvm.suld.1d.v2i16.trap">;
2107 "llvm.nvvm.suld.1d.array.v2i16.trap">;
2152 "llvm.nvvm.suld.2d.v2i16.trap">;
2197 "llvm.nvvm.suld.2d.array.v2i16.trap">;
2242 "llvm.nvvm.suld.3d.v2i16.trap">;
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/external/swiftshader/third_party/LLVM/lib/VMCore/
DValueTypes.cpp125 case MVT::v2i16: return "v2i16"; in getEVTString()
172 case MVT::v2i16: return VectorType::get(Type::getInt16Ty(Context), 2); in getTypeForEVT()
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp134 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
135 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
166 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, in getCastInstrCost()
167 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, in getCastInstrCost()
/external/llvm/test/CodeGen/Hexagon/vect/
Dvect-truncate.ll2 ; Used to fail with "Cannot select: 0x16cb7f0: v2i16 = truncate"
/external/llvm/lib/Target/NVPTX/
DNVPTXVector.td25 // Extract v2i16
30 (v2i16 V2I16Regs:$src), imm:$c))],
123 // Insert v2i16
788 def : Pat<(v2i16 (vec_shuf:$op V2I16Regs:$src1, V2I16Regs:$src2)),
882 def : Pat<(v2i16 (extract_subvec V4I16Regs:$src, 0)),
885 def : Pat<(v2i16 (extract_subvec V4I16Regs:$src, 2)),
1266 // v2i16 -> i32
1292 // i32 -> v2i16
1305 // v4i8 -> v2i16
1306 def : Pat<(v2i16 (bitconvert V4I8Regs:$s)),
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