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Searched refs:v8i64 (Results 1 – 25 of 35) sorted by relevance

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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DValueTypes.h69 v8i64 = 27, // 8 x i64 enumerator
154 (SimpleTy >= MVT::v2i8 && SimpleTy <= MVT::v8i64)); in isInteger()
205 case v8i64: return i64; in getVectorElementType()
224 case v8i64: in getVectorNumElements()
284 case v8i64: return 512; in getSizeInBits()
360 if (NumElements == 8) return MVT::v8i64; in getVectorVT()
510 return isSimple() ? (V == MVT::v8i64) : isExtended512BitVector(); in is512BitVector()
DValueTypes.td50 def v8i64 : ValueType<512, 27>; // 8 x i64 vector value
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h98 v8i64 = 48, // 8 x i64 enumerator
267 SimpleTy == MVT::v8i64); in is512BitVector()
352 case v8i64: in getVectorElementType()
399 case v8i64: in getVectorNumElements()
500 case v8i64: in getSizeInBits()
636 if (NumElements == 8) return MVT::v8i64; in getVectorVT()
DValueTypes.td75 def v8i64 : ValueType<512, 48>; // 8 x i64 vector value
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp138 { ISD::SHL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
139 { ISD::SRL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
140 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
539 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, in getCastInstrCost()
540 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, in getCastInstrCost()
544 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, in getCastInstrCost()
547 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, in getCastInstrCost()
560 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, in getCastInstrCost()
561 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, in getCastInstrCost()
570 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, in getCastInstrCost()
[all …]
DX86CallingConv.td68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
122 CCIfType<[v16f32, v8f64, v16i32, v8i64],
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
346 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
366 CCIfType<[v16i32, v8i64, v16f32, v8f64],
406 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
449 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
524 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
541 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
560 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
DX86InstrFragmentsSIMD.td627 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
707 (v8i64 (alignedload512 node:$ptr))>;
781 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
782 Mgt->getBasePtr().getValueType() == MVT::v8i64);
828 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
829 Sc->getBasePtr().getValueType() == MVT::v8i64);
857 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
DX86InstrAVX512.td87 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
378 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
383 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
388 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
389 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
390 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
391 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
392 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
393 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
398 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp205 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
206 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
207 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
208 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
450 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost }, in getCmpSelInstrCost()
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp117 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
118 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
119 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
120 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
302 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 }, in getCmpSelInstrCost()
DARMRegisterInfo.td398 def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (add Tuples2QQ)> {
/external/swiftshader/third_party/LLVM/lib/VMCore/
DValueTypes.cpp135 case MVT::v8i64: return "v8i64"; in getEVTString()
182 case MVT::v8i64: return VectorType::get(Type::getInt64Ty(Context), 8); in getTypeForEVT()
/external/llvm/lib/IR/
DValueTypes.cpp180 case MVT::v8i64: return "v8i64"; in getEVTString()
258 case MVT::v8i64: return VectorType::get(Type::getInt64Ty(Context), 8); in getTypeForEVT()
/external/llvm/test/CodeGen/X86/
Dvector-popcnt-512.ll42 %out = call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> %in)
176 declare <8 x i64> @llvm.ctpop.v8i64(<8 x i64>)
Dvector-lzcnt-512.ll10 %out = call <8 x i64> @llvm.ctlz.v8i64(<8 x i64> %in, i1 0)
19 %out = call <8 x i64> @llvm.ctlz.v8i64(<8 x i64> %in, i1 -1)
217 declare <8 x i64> @llvm.ctlz.v8i64(<8 x i64>, i1)
Dvector-tzcnt-512.ll68 %out = call <8 x i64> @llvm.cttz.v8i64(<8 x i64> %in, i1 0)
109 %out = call <8 x i64> @llvm.cttz.v8i64(<8 x i64> %in, i1 -1)
511 declare <8 x i64> @llvm.cttz.v8i64(<8 x i64>, i1)
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp197 if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_Hexagon_VarArg()
337 (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_HexagonVector()
413 LocVT == MVT::v16i32 || LocVT == MVT::v8i64 || in RetCC_Hexagon()
543 return (ty == MVT::v8i64 || ty == MVT::v16i32 || ty == MVT::v32i16 || in IsHvxVectorType()
901 UseHVX && !UseHVXDbl && (VT == MVT::v16i32 || VT == MVT::v8i64 || in getIndexedAddressParts()
1118 } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 || in LowerFormalArguments()
1758 addRegisterClass(MVT::v8i64, &Hexagon::VectorRegsRegClass); in HexagonTargetLowering()
2876 case MVT::v8i64: in getRegForInlineAsmConstraint()
2886 case MVT::v8i64: in getRegForInlineAsmConstraint()
3037 case MVT::v8i64: in allowsMisalignedMemoryAccesses()
[all …]
DHexagonIntrinsicsV60.td99 def : Pat <(v512i1 (bitconvert (v8i64 VectorRegs:$src1))),
100 (v512i1 (V6_vandvrt(v8i64 VectorRegs:$src1),
119 def : Pat <(v8i64 (bitconvert (v512i1 VecPredRegs:$src1))),
120 (v8i64 (V6_vandqrt(v512i1 VecPredRegs:$src1),
DHexagonRegisterInfo.td226 def VectorRegs : RegisterClass<"Hexagon", [v64i8, v32i16, v16i32, v8i64], 512,
DHexagonISelDAGToDAG.cpp278 case MVT::v8i64: in SelectIndexedLoad()
566 case MVT::v8i64: in SelectIndexedStore()
/external/swiftshader/third_party/LLVM/utils/TableGen/
DCodeGenTarget.cpp84 case MVT::v8i64: return "MVT::v8i64"; in getEnumName()
/external/llvm/test/CodeGen/AMDGPU/
Dctpop64.ll7 declare <8 x i64> @llvm.ctpop.v8i64(<8 x i64>) nounwind readnone
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp108 case MVT::v8i64: return "MVT::v8i64"; in getEnumName()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMRegisterInfo.td339 def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (sequence "QQQQ%u", 0, 3)> {
/external/llvm/include/llvm/IR/
DIntrinsics.td208 def llvm_v8i64_ty : LLVMType<v8i64>; // 8 x i64

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